[deliverable/linux.git] / include / asm-x86_64 / pci.h

#ifndef __x8664_PCI_H
#define __x8664_PCI_H

#include <asm/io.h>

#ifdef __KERNEL__

struct pci_sysdata {
	int		node;		/* NUMA node */
	void*		iommu;		/* IOMMU private data */
};

extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);

#ifdef CONFIG_CALGARY_IOMMU
static inline void* pci_iommu(struct pci_bus *bus)
{
	struct pci_sysdata *sd = bus->sysdata;
	return sd->iommu;
}

static inline void set_pci_iommu(struct pci_bus *bus, void *val)
{
	struct pci_sysdata *sd = bus->sysdata;
	sd->iommu = val;
}
#endif /* CONFIG_CALGARY_IOMMU */

#include <linux/mm.h> /* for struct page */

/* Can be used to override the logic in pci_scan_bus for skipping
   already-configured bus numbers - to be used for buggy BIOSes
   or architectures with incomplete PCI setup by the loader */

#ifdef CONFIG_PCI
extern unsigned int pcibios_assign_all_busses(void);
#else
#define pcibios_assign_all_busses()	0
#endif
#define pcibios_scan_all_fns(a, b)	0

extern unsigned long pci_mem_start;
#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		(pci_mem_start)

#define PCIBIOS_MIN_CARDBUS_IO	0x4000

void pcibios_config_init(void);
struct pci_bus * pcibios_scan_root(int bus);
extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);

void pcibios_set_master(struct pci_dev *dev);
void pcibios_penalize_isa_irq(int irq, int active);
struct irq_routing_table *pcibios_get_irq_routing_table(void);
int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);

#include <linux/types.h>
#include <linux/slab.h>
#include <asm/scatterlist.h>
#include <linux/string.h>
#include <asm/page.h>

extern void pci_iommu_alloc(void);
extern int iommu_setup(char *opt);

/* The PCI address space does equal the physical memory
 * address space.  The networking and block device layers use
 * this boolean for bounce buffer decisions
 *
 * On AMD64 it mostly equals, but we set it to zero if a hardware
 * IOMMU (gart) of sotware IOMMU (swiotlb) is available.
 */
#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)

#if defined(CONFIG_IOMMU) || defined(CONFIG_CALGARY_IOMMU)

#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
	dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
	__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME)			\
	((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
	(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME)			\
	((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
	(((PTR)->LEN_NAME) = (VAL))

#else
/* No IOMMU */

#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
#define pci_unmap_len(PTR, LEN_NAME)		(0)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)

#endif

#include <asm-generic/pci-dma-compat.h>

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	*strat = PCI_DMA_BURST_INFINITY;
	*strategy_parameter = ~0UL;
}
#endif

#define HAVE_PCI_MMAP
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			       enum pci_mmap_state mmap_state, int write_combine);

#endif /* __KERNEL__ */

/* generic pci stuff */
#ifdef CONFIG_PCI
#include <asm-generic/pci.h>
#endif

#endif /* __x8664_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __x8664_PCI_H
	2	#define __x8664_PCI_H
	3
1da177e4 LT	4	#include <asm/io.h>
	5
	6	#ifdef __KERNEL__
	7
08f1c192 MBY	8	struct pci_sysdata {
	9	int node; /* NUMA node */
	10	void* iommu; /* IOMMU private data */
	11	};
	12
73c59afc MBY	13	extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
73c59afc MBY	14
08f1c192 MBY	15	#ifdef CONFIG_CALGARY_IOMMU
	16	static inline void* pci_iommu(struct pci_bus *bus)
	17	{
	18	struct pci_sysdata *sd = bus->sysdata;
	19	return sd->iommu;
	20	}
	21
	22	static inline void set_pci_iommu(struct pci_bus bus, void val)
	23	{
	24	struct pci_sysdata *sd = bus->sysdata;
	25	sd->iommu = val;
	26	}
	27	#endif /* CONFIG_CALGARY_IOMMU */
	28
1da177e4 LT	29	#include <linux/mm.h> /* for struct page */
	30
	31	/* Can be used to override the logic in pci_scan_bus for skipping
	32	already-configured bus numbers - to be used for buggy BIOSes
	33	or architectures with incomplete PCI setup by the loader */
	34
	35	#ifdef CONFIG_PCI
	36	extern unsigned int pcibios_assign_all_busses(void);
	37	#else
	38	#define pcibios_assign_all_busses() 0
	39	#endif
	40	#define pcibios_scan_all_fns(a, b) 0
	41
1da177e4	42	extern unsigned long pci_mem_start;
2ba84684	43	#define PCIBIOS_MIN_IO 0x1000
1da177e4 LT	44	#define PCIBIOS_MIN_MEM (pci_mem_start)
1da177e4 LT	45
2ba84684 LT	46	#define PCIBIOS_MIN_CARDBUS_IO 0x4000
2ba84684 LT	47
1da177e4 LT	48	void pcibios_config_init(void);
	49	struct pci_bus * pcibios_scan_root(int bus);
	50	extern int (pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
	51	extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
	52
	53	void pcibios_set_master(struct pci_dev *dev);
c9c3e457	54	void pcibios_penalize_isa_irq(int irq, int active);
1da177e4 LT	55	struct irq_routing_table *pcibios_get_irq_routing_table(void);
	56	int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
	57
	58	#include <linux/types.h>
	59	#include <linux/slab.h>
	60	#include <asm/scatterlist.h>
	61	#include <linux/string.h>
	62	#include <asm/page.h>
	63
0dc243ae	64	extern void pci_iommu_alloc(void);
1da177e4 LT	65	extern int iommu_setup(char *opt);
1da177e4 LT	66
1da177e4 LT	67	/* The PCI address space does equal the physical memory
	68	* address space. The networking and block device layers use
	69	* this boolean for bounce buffer decisions
	70	*
17a941d8 MBY	71	* On AMD64 it mostly equals, but we set it to zero if a hardware
17a941d8 MBY	72	* IOMMU (gart) of sotware IOMMU (swiotlb) is available.
1da177e4	73	*/
17a941d8 MBY	74	#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
17a941d8 MBY	75
e465058d	76	#if defined(CONFIG_IOMMU) \|\| defined(CONFIG_CALGARY_IOMMU)
1da177e4	77
1da177e4 LT	78	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
	79	dma_addr_t ADDR_NAME;
	80	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
	81	__u32 LEN_NAME;
	82	#define pci_unmap_addr(PTR, ADDR_NAME) \
	83	((PTR)->ADDR_NAME)
	84	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
	85	(((PTR)->ADDR_NAME) = (VAL))
	86	#define pci_unmap_len(PTR, LEN_NAME) \
	87	((PTR)->LEN_NAME)
	88	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
	89	(((PTR)->LEN_NAME) = (VAL))
	90
	91	#else
	92	/* No IOMMU */
	93
1da177e4 LT	94	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
	95	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
	96	#define pci_unmap_addr(PTR, ADDR_NAME) (0)
	97	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	98	#define pci_unmap_len(PTR, LEN_NAME) (0)
	99	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	100
	101	#endif
	102
	103	#include <asm-generic/pci-dma-compat.h>
	104
bb4a61b6	105	#ifdef CONFIG_PCI
e24c2d96 DM	106	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	107	enum pci_dma_burst_strategy *strat,
	108	unsigned long *strategy_parameter)
	109	{
	110	*strat = PCI_DMA_BURST_INFINITY;
	111	*strategy_parameter = ~0UL;
	112	}
bb4a61b6	113	#endif
e24c2d96	114
1da177e4 LT	115	#define HAVE_PCI_MMAP
	116	extern int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	117	enum pci_mmap_state mmap_state, int write_combine);
	118
1da177e4 LT	119	#endif /* __KERNEL__ */
	120
	121	/* generic pci stuff */
	122	#ifdef CONFIG_PCI
	123	#include <asm-generic/pci.h>
	124	#endif
	125
	126	#endif /* __x8664_PCI_H */