[PATCH] i386: conditionalize inclusion of some MTRR flavors
[deliverable/linux.git] / include / asm-x86_64 / pgtable.h
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1da177e4
LT
1#ifndef _X86_64_PGTABLE_H
2#define _X86_64_PGTABLE_H
3
4/*
5 * This file contains the functions and defines necessary to modify and use
6 * the x86-64 page table tree.
7 */
8#include <asm/processor.h>
9#include <asm/fixmap.h>
10#include <asm/bitops.h>
11#include <linux/threads.h>
12#include <asm/pda.h>
13
14extern pud_t level3_kernel_pgt[512];
15extern pud_t level3_physmem_pgt[512];
16extern pud_t level3_ident_pgt[512];
17extern pmd_t level2_kernel_pgt[512];
18extern pgd_t init_level4_pgt[];
f6c2e333 19extern pgd_t boot_level4_pgt[];
1da177e4
LT
20extern unsigned long __supported_pte_mask;
21
22#define swapper_pg_dir init_level4_pgt
23
1da177e4
LT
24extern void paging_init(void);
25extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
26
1da177e4
LT
27/*
28 * ZERO_PAGE is a global shared page that is always zero: used
29 * for zero-mapped memory areas etc..
30 */
31extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
32#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
33
34/*
35 * PGDIR_SHIFT determines what a top-level page table entry can map
36 */
37#define PGDIR_SHIFT 39
38#define PTRS_PER_PGD 512
39
40/*
41 * 3rd level page
42 */
43#define PUD_SHIFT 30
44#define PTRS_PER_PUD 512
45
46/*
47 * PMD_SHIFT determines the size of the area a middle-level
48 * page table can map
49 */
50#define PMD_SHIFT 21
51#define PTRS_PER_PMD 512
52
53/*
54 * entries per page directory level
55 */
56#define PTRS_PER_PTE 512
57
58#define pte_ERROR(e) \
59 printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
60#define pmd_ERROR(e) \
61 printk("%s:%d: bad pmd %p(%016lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
62#define pud_ERROR(e) \
63 printk("%s:%d: bad pud %p(%016lx).\n", __FILE__, __LINE__, &(e), pud_val(e))
64#define pgd_ERROR(e) \
65 printk("%s:%d: bad pgd %p(%016lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
66
67#define pgd_none(x) (!pgd_val(x))
68#define pud_none(x) (!pud_val(x))
69
70static inline void set_pte(pte_t *dst, pte_t val)
71{
72 pte_val(*dst) = pte_val(val);
73}
74#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
75
76static inline void set_pmd(pmd_t *dst, pmd_t val)
77{
78 pmd_val(*dst) = pmd_val(val);
79}
80
81static inline void set_pud(pud_t *dst, pud_t val)
82{
83 pud_val(*dst) = pud_val(val);
84}
85
9c0aa0f9 86static inline void pud_clear (pud_t *pud)
1da177e4
LT
87{
88 set_pud(pud, __pud(0));
89}
90
91static inline void set_pgd(pgd_t *dst, pgd_t val)
92{
93 pgd_val(*dst) = pgd_val(val);
94}
95
9c0aa0f9 96static inline void pgd_clear (pgd_t * pgd)
1da177e4
LT
97{
98 set_pgd(pgd, __pgd(0));
99}
100
1da177e4 101#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte, 0))
61e06037 102
8c65b4a6
TS
103struct mm_struct;
104
61e06037
ZA
105static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
106{
107 pte_t pte;
108 if (full) {
109 pte = *ptep;
110 *ptep = __pte(0);
111 } else {
112 pte = ptep_get_and_clear(mm, addr, ptep);
113 }
114 return pte;
115}
116
1da177e4
LT
117#define pte_same(a, b) ((a).pte == (b).pte)
118
c728252c
AV
119#define pte_pgprot(a) (__pgprot((a).pte & ~PHYSICAL_PAGE_MASK))
120
1da177e4
LT
121#define PMD_SIZE (1UL << PMD_SHIFT)
122#define PMD_MASK (~(PMD_SIZE-1))
123#define PUD_SIZE (1UL << PUD_SHIFT)
124#define PUD_MASK (~(PUD_SIZE-1))
125#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
126#define PGDIR_MASK (~(PGDIR_SIZE-1))
127
f83f2b5f 128#define USER_PTRS_PER_PGD ((TASK_SIZE-1)/PGDIR_SIZE+1)
d455a369 129#define FIRST_USER_ADDRESS 0
1da177e4
LT
130
131#ifndef __ASSEMBLY__
132#define MAXMEM 0x3fffffffffffUL
133#define VMALLOC_START 0xffffc20000000000UL
134#define VMALLOC_END 0xffffe1ffffffffffUL
135#define MODULES_VADDR 0xffffffff88000000UL
136#define MODULES_END 0xfffffffffff00000UL
137#define MODULES_LEN (MODULES_END - MODULES_VADDR)
138
139#define _PAGE_BIT_PRESENT 0
140#define _PAGE_BIT_RW 1
141#define _PAGE_BIT_USER 2
142#define _PAGE_BIT_PWT 3
143#define _PAGE_BIT_PCD 4
144#define _PAGE_BIT_ACCESSED 5
145#define _PAGE_BIT_DIRTY 6
146#define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
147#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
148#define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
149
150#define _PAGE_PRESENT 0x001
151#define _PAGE_RW 0x002
152#define _PAGE_USER 0x004
153#define _PAGE_PWT 0x008
154#define _PAGE_PCD 0x010
155#define _PAGE_ACCESSED 0x020
156#define _PAGE_DIRTY 0x040
157#define _PAGE_PSE 0x080 /* 2MB page */
9b4ee40e 158#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */
1da177e4
LT
159#define _PAGE_GLOBAL 0x100 /* Global TLB entry */
160
161#define _PAGE_PROTNONE 0x080 /* If not present */
162#define _PAGE_NX (1UL<<_PAGE_BIT_NX)
163
164#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
165#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
166
167#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
168
169#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
170#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
171#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
172#define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
173#define PAGE_COPY PAGE_COPY_NOEXEC
174#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
175#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
176#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
177#define __PAGE_KERNEL \
178 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
179#define __PAGE_KERNEL_EXEC \
180 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
181#define __PAGE_KERNEL_NOCACHE \
182 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_NX)
183#define __PAGE_KERNEL_RO \
184 (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
185#define __PAGE_KERNEL_VSYSCALL \
186 (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
187#define __PAGE_KERNEL_VSYSCALL_NOCACHE \
188 (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD)
189#define __PAGE_KERNEL_LARGE \
190 (__PAGE_KERNEL | _PAGE_PSE)
8bf27556
EB
191#define __PAGE_KERNEL_LARGE_EXEC \
192 (__PAGE_KERNEL_EXEC | _PAGE_PSE)
1da177e4
LT
193
194#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
195
196#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
197#define PAGE_KERNEL_EXEC MAKE_GLOBAL(__PAGE_KERNEL_EXEC)
198#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
199#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
200#define PAGE_KERNEL_VSYSCALL32 __pgprot(__PAGE_KERNEL_VSYSCALL)
201#define PAGE_KERNEL_VSYSCALL MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL)
202#define PAGE_KERNEL_LARGE MAKE_GLOBAL(__PAGE_KERNEL_LARGE)
203#define PAGE_KERNEL_VSYSCALL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL_NOCACHE)
204
205/* xwr */
206#define __P000 PAGE_NONE
207#define __P001 PAGE_READONLY
208#define __P010 PAGE_COPY
209#define __P011 PAGE_COPY
210#define __P100 PAGE_READONLY_EXEC
211#define __P101 PAGE_READONLY_EXEC
212#define __P110 PAGE_COPY_EXEC
213#define __P111 PAGE_COPY_EXEC
214
215#define __S000 PAGE_NONE
216#define __S001 PAGE_READONLY
217#define __S010 PAGE_SHARED
218#define __S011 PAGE_SHARED
219#define __S100 PAGE_READONLY_EXEC
220#define __S101 PAGE_READONLY_EXEC
221#define __S110 PAGE_SHARED_EXEC
222#define __S111 PAGE_SHARED_EXEC
223
224static inline unsigned long pgd_bad(pgd_t pgd)
225{
226 unsigned long val = pgd_val(pgd);
227 val &= ~PTE_MASK;
228 val &= ~(_PAGE_USER | _PAGE_DIRTY);
229 return val & ~(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED);
230}
231
232static inline unsigned long pud_bad(pud_t pud)
233{
234 unsigned long val = pud_val(pud);
235 val &= ~PTE_MASK;
236 val &= ~(_PAGE_USER | _PAGE_DIRTY);
237 return val & ~(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED);
238}
239
240#define pte_none(x) (!pte_val(x))
241#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
242#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
243
244#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) /* FIXME: is this
245 right? */
246#define pte_page(x) pfn_to_page(pte_pfn(x))
6b75aeed 247#define pte_pfn(x) ((pte_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
1da177e4
LT
248
249static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
250{
251 pte_t pte;
252 pte_val(pte) = (page_nr << PAGE_SHIFT);
253 pte_val(pte) |= pgprot_val(pgprot);
254 pte_val(pte) &= __supported_pte_mask;
255 return pte;
256}
257
258/*
259 * The following only work if pte_present() is true.
260 * Undefined behaviour if not..
261 */
32e51a8c 262#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT)
1da177e4 263static inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
4839057c 264static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
df992848 265static inline int pte_exec(pte_t pte) { return !(pte_val(pte) & _PAGE_NX); }
4839057c
AB
266static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
267static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
268static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
1da177e4 269static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
8f860591 270static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_PSE; }
1da177e4 271
4839057c
AB
272static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
273static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
274static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
275static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
276static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
277static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
df992848 278static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_NX)); return pte; }
4839057c
AB
279static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
280static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
281static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
8f860591 282static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_PSE)); return pte; }
5e6b0bfe 283static inline pte_t pte_clrhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_PSE)); return pte; }
1da177e4
LT
284
285struct vm_area_struct;
286
287static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
288{
289 if (!pte_dirty(*ptep))
290 return 0;
3d1712c9 291 return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte);
1da177e4
LT
292}
293
294static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
295{
296 if (!pte_young(*ptep))
297 return 0;
3d1712c9 298 return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte);
1da177e4
LT
299}
300
301static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
302{
3d1712c9 303 clear_bit(_PAGE_BIT_RW, &ptep->pte);
1da177e4
LT
304}
305
306/*
307 * Macro to mark a page protection value as "uncacheable".
308 */
309#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))
310
1da177e4
LT
311static inline int pmd_large(pmd_t pte) {
312 return (pmd_val(pte) & __LARGE_PTE) == __LARGE_PTE;
313}
314
315
316/*
317 * Conversion functions: convert a page and protection to a page entry,
318 * and a page entry and page directory to the page they refer to.
319 */
320
1da177e4
LT
321/*
322 * Level 4 access.
323 */
46a82b2d
DM
324#define pgd_page_vaddr(pgd) ((unsigned long) __va((unsigned long)pgd_val(pgd) & PTE_MASK))
325#define pgd_page(pgd) (pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT))
1da177e4
LT
326#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
327#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
328#define pgd_offset_k(address) (init_level4_pgt + pgd_index(address))
329#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT)
330#define mk_kernel_pgd(address) ((pgd_t){ (address) | _KERNPG_TABLE })
331
332/* PUD - Level3 access */
333/* to find an entry in a page-table-directory. */
46a82b2d
DM
334#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK))
335#define pud_page(pud) (pfn_to_page(pud_val(pud) >> PAGE_SHIFT))
1da177e4 336#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
46a82b2d 337#define pud_offset(pgd, address) ((pud_t *) pgd_page_vaddr(*(pgd)) + pud_index(address))
1da177e4
LT
338#define pud_present(pud) (pud_val(pud) & _PAGE_PRESENT)
339
1da177e4 340/* PMD - Level 2 access */
46a82b2d 341#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PTE_MASK))
1da177e4
LT
342#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
343
344#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
46a82b2d 345#define pmd_offset(dir, address) ((pmd_t *) pud_page_vaddr(*(dir)) + \
1da177e4
LT
346 pmd_index(address))
347#define pmd_none(x) (!pmd_val(x))
348#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
349#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
350#define pmd_bad(x) ((pmd_val(x) & (~PTE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE )
351#define pfn_pmd(nr,prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val(prot)))
6b75aeed 352#define pmd_pfn(x) ((pmd_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
1da177e4
LT
353
354#define pte_to_pgoff(pte) ((pte_val(pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
355#define pgoff_to_pte(off) ((pte_t) { ((off) << PAGE_SHIFT) | _PAGE_FILE })
356#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
357
358/* PTE - Level 1 access. */
359
360/* page, protection -> pte */
361#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
362#define mk_pte_huge(entry) (pte_val(entry) |= _PAGE_PRESENT | _PAGE_PSE)
363
364/* physical address -> PTE */
365static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
366{
367 pte_t pte;
368 pte_val(pte) = physpage | pgprot_val(pgprot);
7a71cef7 369 pte_val(pte) &= __supported_pte_mask;
1da177e4
LT
370 return pte;
371}
372
373/* Change flags of a PTE */
9c0aa0f9 374static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4
LT
375{
376 pte_val(pte) &= _PAGE_CHG_MASK;
377 pte_val(pte) |= pgprot_val(newprot);
378 pte_val(pte) &= __supported_pte_mask;
379 return pte;
380}
381
382#define pte_index(address) \
1294b118 383 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
46a82b2d 384#define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_vaddr(*(dir)) + \
1da177e4
LT
385 pte_index(address))
386
387/* x86-64 always has all page tables mapped. */
388#define pte_offset_map(dir,address) pte_offset_kernel(dir,address)
389#define pte_offset_map_nested(dir,address) pte_offset_kernel(dir,address)
390#define pte_unmap(pte) /* NOP */
391#define pte_unmap_nested(pte) /* NOP */
392
393#define update_mmu_cache(vma,address,pte) do { } while (0)
394
395/* We only update the dirty/accessed state if we set
396 * the dirty bit by hand in the kernel, since the hardware
397 * will do the accessed bit for us, and we don't want to
398 * race with other CPU's that might be updating the dirty
399 * bit at the same time. */
400#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
401#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
402 do { \
403 if (__dirty) { \
404 set_pte(__ptep, __entry); \
405 flush_tlb_page(__vma, __address); \
406 } \
407 } while (0)
408
409/* Encode and de-code a swap entry */
410#define __swp_type(x) (((x).val >> 1) & 0x3f)
411#define __swp_offset(x) ((x).val >> 8)
412#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
413#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
414#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
415
8c914cb7
JB
416extern spinlock_t pgd_lock;
417extern struct page *pgd_list;
418void vmalloc_sync_all(void);
419
1da177e4
LT
420#endif /* !__ASSEMBLY__ */
421
422extern int kern_addr_valid(unsigned long addr);
423
1da177e4
LT
424#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
425 remap_pfn_range(vma, vaddr, pfn, size, prot)
426
427#define MK_IOSPACE_PFN(space, pfn) (pfn)
428#define GET_IOSPACE(pfn) 0
429#define GET_PFN(pfn) (pfn)
430
431#define HAVE_ARCH_UNMAPPED_AREA
432
433#define pgtable_cache_init() do { } while (0)
434#define check_pgt_cache() do { } while (0)
435
436#define PAGE_AGP PAGE_KERNEL_NOCACHE
437#define HAVE_PAGE_AGP 1
438
439/* fs/proc/kcore.c */
440#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
441#define kc_offset_to_vaddr(o) \
442 (((o) & (1UL << (__VIRTUAL_MASK_SHIFT-1))) ? ((o) | (~__VIRTUAL_MASK)) : (o))
443
444#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
445#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
446#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
61e06037 447#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1da177e4
LT
448#define __HAVE_ARCH_PTEP_SET_WRPROTECT
449#define __HAVE_ARCH_PTE_SAME
450#include <asm-generic/pgtable.h>
451
452#endif /* _X86_64_PGTABLE_H */
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