[PATCH] xtensa: fix irq and misc fixes
[deliverable/linux.git] / include / asm-xtensa / page.h
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1/*
2 * linux/include/asm-xtensa/page.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PAGE_H
12#define _XTENSA_PAGE_H
13
14#ifdef __KERNEL__
15
16#include <asm/processor.h>
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17
18/*
19 * PAGE_SHIFT determines the page size
20 * PAGE_ALIGN(x) aligns the pointer to the (next) page boundary
21 */
22
23#define PAGE_SHIFT XCHAL_MMU_MIN_PTE_PAGE_SIZE
24#define PAGE_SIZE (1 << PAGE_SHIFT)
25#define PAGE_MASK (~(PAGE_SIZE-1))
26#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE - 1) & PAGE_MASK)
27
28#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
29#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
30
31#ifdef __ASSEMBLY__
32
33#define __pgprot(x) (x)
34
35#else
36
37/*
38 * These are used to make use of C type-checking..
39 */
40
41typedef struct { unsigned long pte; } pte_t; /* page table entry */
42typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
43typedef struct { unsigned long pgprot; } pgprot_t;
44
45#define pte_val(x) ((x).pte)
46#define pgd_val(x) ((x).pgd)
47#define pgprot_val(x) ((x).pgprot)
48
49#define __pte(x) ((pte_t) { (x) } )
50#define __pgd(x) ((pgd_t) { (x) } )
51#define __pgprot(x) ((pgprot_t) { (x) } )
52
53/*
54 * Pure 2^n version of get_order
55 */
56
d99cf715 57static inline int get_order(unsigned long size)
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58{
59 int order;
60#ifndef XCHAL_HAVE_NSU
61 unsigned long x1, x2, x4, x8, x16;
62
63 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
64 x1 = size & 0xAAAAAAAA;
65 x2 = size & 0xCCCCCCCC;
66 x4 = size & 0xF0F0F0F0;
67 x8 = size & 0xFF00FF00;
68 x16 = size & 0xFFFF0000;
69 order = x2 ? 2 : 0;
70 order += (x16 != 0) * 16;
71 order += (x8 != 0) * 8;
72 order += (x4 != 0) * 4;
73 order += (x1 != 0);
74
75 return order;
76#else
77 size = (size - 1) >> PAGE_SHIFT;
78 asm ("nsau %0, %1" : "=r" (order) : "r" (size));
79 return 32 - order;
80#endif
81}
82
83
84struct page;
85extern void clear_page(void *page);
86extern void copy_page(void *to, void *from);
87
88/*
89 * If we have cache aliasing and writeback caches, we might have to do
90 * some extra work
91 */
92
93#if (DCACHE_WAY_SIZE > PAGE_SIZE)
94void clear_user_page(void *addr, unsigned long vaddr, struct page* page);
95void copy_user_page(void *to,void* from,unsigned long vaddr,struct page* page);
96#else
97# define clear_user_page(page,vaddr,pg) clear_page(page)
98# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
99#endif
100
101/*
102 * This handles the memory map. We handle pages at
103 * XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
104 * These macros are for conversion of kernel address, not user
105 * addresses.
106 */
107
108#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
109#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
110#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr)
655a0443 111#ifdef CONFIG_DISCONTIGMEM
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112# error CONFIG_DISCONTIGMEM not supported
113#endif
114
115#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
116#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
117#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
118#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
119
120#define WANT_PAGE_VIRTUAL
121
122
123#endif /* __ASSEMBLY__ */
124
125#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
126 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
127
128#endif /* __KERNEL__ */
655a0443 129#include <asm-generic/memory_model.h>
9a8fd558 130#endif /* _XTENSA_PAGE_H */
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