drm/radeon/kms/cayman/blit: specify CP_COHER_CNTL2 with surface_sync
[deliverable/linux.git] / include / drm / drm_dp_helper.h
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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
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23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
a4fc5ed6 25
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26#include <linux/types.h>
27#include <linux/i2c.h>
28
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29/* From the VESA DisplayPort spec */
30
31#define AUX_NATIVE_WRITE 0x8
32#define AUX_NATIVE_READ 0x9
33#define AUX_I2C_WRITE 0x0
34#define AUX_I2C_READ 0x1
35#define AUX_I2C_STATUS 0x2
36#define AUX_I2C_MOT 0x4
37
38#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
39#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
40#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
41#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
42
43#define AUX_I2C_REPLY_ACK (0x0 << 6)
44#define AUX_I2C_REPLY_NACK (0x1 << 6)
45#define AUX_I2C_REPLY_DEFER (0x2 << 6)
46#define AUX_I2C_REPLY_MASK (0x3 << 6)
47
48/* AUX CH addresses */
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49/* DPCD */
50#define DP_DPCD_REV 0x000
746c1aa4 51
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52#define DP_MAX_LINK_RATE 0x001
53
54#define DP_MAX_LANE_COUNT 0x002
55# define DP_MAX_LANE_COUNT_MASK 0x1f
428c4b51 56# define DP_TPS3_SUPPORTED (1 << 6)
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57# define DP_ENHANCED_FRAME_CAP (1 << 7)
58
59#define DP_MAX_DOWNSPREAD 0x003
60# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
61
62#define DP_NORP 0x004
63
64#define DP_DOWNSTREAMPORT_PRESENT 0x005
65# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
66# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
67/* 00b = DisplayPort */
68/* 01b = Analog */
69/* 10b = TMDS or HDMI */
70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3)
72
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74
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75#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
76
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77#define DP_PSR_SUPPORT 0x070
78# define DP_PSR_IS_SUPPORTED 1
79#define DP_PSR_CAPS 0x071
80# define DP_PSR_NO_TRAIN_ON_EXIT 1
81# define DP_PSR_SETUP_TIME_330 (0 << 1)
82# define DP_PSR_SETUP_TIME_275 (1 << 1)
83# define DP_PSR_SETUP_TIME_220 (2 << 1)
84# define DP_PSR_SETUP_TIME_165 (3 << 1)
85# define DP_PSR_SETUP_TIME_110 (4 << 1)
86# define DP_PSR_SETUP_TIME_55 (5 << 1)
87# define DP_PSR_SETUP_TIME_0 (6 << 1)
88# define DP_PSR_SETUP_TIME_MASK (7 << 1)
89# define DP_PSR_SETUP_TIME_SHIFT 1
90
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91/* link configuration */
92#define DP_LINK_BW_SET 0x100
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93# define DP_LINK_BW_1_62 0x06
94# define DP_LINK_BW_2_7 0x0a
428c4b51 95# define DP_LINK_BW_5_4 0x14
a4fc5ed6 96
5801ead6 97#define DP_LANE_COUNT_SET 0x101
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98# define DP_LANE_COUNT_MASK 0x0f
99# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
100
5801ead6 101#define DP_TRAINING_PATTERN_SET 0x102
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102# define DP_TRAINING_PATTERN_DISABLE 0
103# define DP_TRAINING_PATTERN_1 1
104# define DP_TRAINING_PATTERN_2 2
428c4b51 105# define DP_TRAINING_PATTERN_3 3
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106# define DP_TRAINING_PATTERN_MASK 0x3
107
108# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
109# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
110# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
111# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
112# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
113
114# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
115# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
116
117# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
118# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
119# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
120# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
121
122#define DP_TRAINING_LANE0_SET 0x103
123#define DP_TRAINING_LANE1_SET 0x104
124#define DP_TRAINING_LANE2_SET 0x105
125#define DP_TRAINING_LANE3_SET 0x106
126
127# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
128# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
129# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
130# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
131# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
132# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
133# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
134
135# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
136# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
137# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
138# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
139# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
140
141# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
142# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
143
144#define DP_DOWNSPREAD_CTRL 0x107
145# define DP_SPREAD_AMP_0_5 (1 << 4)
146
147#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
148# define DP_SET_ANSI_8B10B (1 << 0)
149
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150#define DP_PSR_EN_CFG 0x170
151# define DP_PSR_ENABLE (1 << 0)
152# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
153# define DP_PSR_CRC_VERIFICATION (1 << 2)
154# define DP_PSR_FRAME_CAPTURE (1 << 3)
155
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156#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
157# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
158# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
159# define DP_CP_IRQ (1 << 2)
160# define DP_SINK_SPECIFIC_IRQ (1 << 6)
161
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162#define DP_LANE0_1_STATUS 0x202
163#define DP_LANE2_3_STATUS 0x203
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164# define DP_LANE_CR_DONE (1 << 0)
165# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
166# define DP_LANE_SYMBOL_LOCKED (1 << 2)
167
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168#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
169 DP_LANE_CHANNEL_EQ_DONE | \
170 DP_LANE_SYMBOL_LOCKED)
171
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172#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
173
174#define DP_INTERLANE_ALIGN_DONE (1 << 0)
175#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
176#define DP_LINK_STATUS_UPDATED (1 << 7)
177
178#define DP_SINK_STATUS 0x205
179
180#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
181#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
182
183#define DP_ADJUST_REQUEST_LANE0_1 0x206
184#define DP_ADJUST_REQUEST_LANE2_3 0x207
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185# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
186# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
187# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
188# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
189# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
190# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
191# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
192# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
a4fc5ed6 193
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194#define DP_TEST_REQUEST 0x218
195# define DP_TEST_LINK_TRAINING (1 << 0)
196# define DP_TEST_LINK_PATTERN (1 << 1)
197# define DP_TEST_LINK_EDID_READ (1 << 2)
198# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
199
200#define DP_TEST_LINK_RATE 0x219
201# define DP_LINK_RATE_162 (0x6)
202# define DP_LINK_RATE_27 (0xa)
203
204#define DP_TEST_LANE_COUNT 0x220
205
206#define DP_TEST_PATTERN 0x221
207
208#define DP_TEST_RESPONSE 0x260
209# define DP_TEST_ACK (1 << 0)
210# define DP_TEST_NAK (1 << 1)
211# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
212
1a66c95a 213#define DP_SET_POWER 0x600
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214# define DP_SET_POWER_D0 0x1
215# define DP_SET_POWER_D3 0x2
1a66c95a 216
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217#define DP_PSR_ERROR_STATUS 0x2006
218# define DP_PSR_LINK_CRC_ERROR (1 << 0)
219# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
220
221#define DP_PSR_ESI 0x2007
222# define DP_PSR_CAPS_CHANGE (1 << 0)
223
224#define DP_PSR_STATUS 0x2008
225# define DP_PSR_SINK_INACTIVE 0
226# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
227# define DP_PSR_SINK_ACTIVE_RFB 2
228# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
229# define DP_PSR_SINK_ACTIVE_RESYNC 4
230# define DP_PSR_SINK_INTERNAL_ERROR 7
231# define DP_PSR_SINK_STATE_MASK 0x07
232
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233#define MODE_I2C_START 1
234#define MODE_I2C_WRITE 2
235#define MODE_I2C_READ 4
236#define MODE_I2C_STOP 8
237
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238struct i2c_algo_dp_aux_data {
239 bool running;
240 u16 address;
241 int (*aux_ch) (struct i2c_adapter *adapter,
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242 int mode, uint8_t write_byte,
243 uint8_t *read_byte);
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244};
245
246int
247i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
248
ab2c0672 249#endif /* _DRM_DP_HELPER_H_ */
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