[deliverable/linux.git] / include / drm / drm_mode.h

/*
 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
 * Copyright (c) 2008 Red Hat Inc.
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * Copyright (c) 2007-2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _DRM_MODE_H
#define _DRM_MODE_H

#define DRM_DISPLAY_INFO_LEN	32
#define DRM_CONNECTOR_NAME_LEN	32
#define DRM_DISPLAY_MODE_LEN	32
#define DRM_PROP_NAME_LEN	32

#define DRM_MODE_TYPE_BUILTIN	(1<<0)
#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_PREFERRED	(1<<3)
#define DRM_MODE_TYPE_DEFAULT	(1<<4)
#define DRM_MODE_TYPE_USERDEF	(1<<5)
#define DRM_MODE_TYPE_DRIVER	(1<<6)

/* Video mode flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_FLAG_PHSYNC	(1<<0)
#define DRM_MODE_FLAG_NHSYNC	(1<<1)
#define DRM_MODE_FLAG_PVSYNC	(1<<2)
#define DRM_MODE_FLAG_NVSYNC	(1<<3)
#define DRM_MODE_FLAG_INTERLACE	(1<<4)
#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
#define DRM_MODE_FLAG_CSYNC	(1<<6)
#define DRM_MODE_FLAG_PCSYNC	(1<<7)
#define DRM_MODE_FLAG_NCSYNC	(1<<8)
#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
#define DRM_MODE_FLAG_BCAST	(1<<10)
#define DRM_MODE_FLAG_PIXMUX	(1<<11)
#define DRM_MODE_FLAG_DBLCLK	(1<<12)
#define DRM_MODE_FLAG_CLKDIV2	(1<<13)

/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON	0
#define DRM_MODE_DPMS_STANDBY	1
#define DRM_MODE_DPMS_SUSPEND	2
#define DRM_MODE_DPMS_OFF	3

/* Scaling mode options */
#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
					     software can still scale) */
#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */

/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF	0
#define DRM_MODE_DITHERING_ON	1
#define DRM_MODE_DITHERING_AUTO 2

/* Dirty info options */
#define DRM_MODE_DIRTY_OFF      0
#define DRM_MODE_DIRTY_ON       1
#define DRM_MODE_DIRTY_ANNOTATE 2

struct drm_mode_modeinfo {
	__u32 clock;
	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;

	__u32 vrefresh;

	__u32 flags;
	__u32 type;
	char name[DRM_DISPLAY_MODE_LEN];
};

struct drm_mode_card_res {
	__u64 fb_id_ptr;
	__u64 crtc_id_ptr;
	__u64 connector_id_ptr;
	__u64 encoder_id_ptr;
	__u32 count_fbs;
	__u32 count_crtcs;
	__u32 count_connectors;
	__u32 count_encoders;
	__u32 min_width, max_width;
	__u32 min_height, max_height;
};

struct drm_mode_crtc {
	__u64 set_connectors_ptr;
	__u32 count_connectors;

	__u32 crtc_id; /**< Id */
	__u32 fb_id; /**< Id of framebuffer */

	__u32 x, y; /**< Position on the frameuffer */

	__u32 gamma_size;
	__u32 mode_valid;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_PRESENT_TOP_FIELD	(1<<0)
#define DRM_MODE_PRESENT_BOTTOM_FIELD	(1<<1)

/* Planes blend with or override other bits on the CRTC */
struct drm_mode_set_plane {
	__u32 plane_id;
	__u32 crtc_id;
	__u32 fb_id; /* fb object contains surface format type */
	__u32 flags; /* see above flags */

	/* Signed dest location allows it to be partially off screen */
	__s32 crtc_x, crtc_y;
	__u32 crtc_w, crtc_h;

	/* Source values are 16.16 fixed point */
	__u32 src_x, src_y;
	__u32 src_h, src_w;
};

struct drm_mode_get_plane {
	__u32 plane_id;

	__u32 crtc_id;
	__u32 fb_id;

	__u32 possible_crtcs;
	__u32 gamma_size;

	__u32 count_format_types;
	__u64 format_type_ptr;
};

struct drm_mode_get_plane_res {
	__u64 plane_id_ptr;
	__u32 count_planes;
};

#define DRM_MODE_ENCODER_NONE	0
#define DRM_MODE_ENCODER_DAC	1
#define DRM_MODE_ENCODER_TMDS	2
#define DRM_MODE_ENCODER_LVDS	3
#define DRM_MODE_ENCODER_TVDAC	4
#define DRM_MODE_ENCODER_VIRTUAL 5

struct drm_mode_get_encoder {
	__u32 encoder_id;
	__u32 encoder_type;

	__u32 crtc_id; /**< Id of crtc */

	__u32 possible_crtcs;
	__u32 possible_clones;
};

/* This is for connectors with multiple signal types. */
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
#define DRM_MODE_SUBCONNECTOR_Automatic	0
#define DRM_MODE_SUBCONNECTOR_Unknown	0
#define DRM_MODE_SUBCONNECTOR_DVID	3
#define DRM_MODE_SUBCONNECTOR_DVIA	4
#define DRM_MODE_SUBCONNECTOR_Composite	5
#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
#define DRM_MODE_SUBCONNECTOR_Component	8
#define DRM_MODE_SUBCONNECTOR_SCART	9

#define DRM_MODE_CONNECTOR_Unknown	0
#define DRM_MODE_CONNECTOR_VGA		1
#define DRM_MODE_CONNECTOR_DVII		2
#define DRM_MODE_CONNECTOR_DVID		3
#define DRM_MODE_CONNECTOR_DVIA		4
#define DRM_MODE_CONNECTOR_Composite	5
#define DRM_MODE_CONNECTOR_SVIDEO	6
#define DRM_MODE_CONNECTOR_LVDS		7
#define DRM_MODE_CONNECTOR_Component	8
#define DRM_MODE_CONNECTOR_9PinDIN	9
#define DRM_MODE_CONNECTOR_DisplayPort	10
#define DRM_MODE_CONNECTOR_HDMIA	11
#define DRM_MODE_CONNECTOR_HDMIB	12
#define DRM_MODE_CONNECTOR_TV		13
#define DRM_MODE_CONNECTOR_eDP		14
#define DRM_MODE_CONNECTOR_VIRTUAL      15

struct drm_mode_get_connector {

	__u64 encoders_ptr;
	__u64 modes_ptr;
	__u64 props_ptr;
	__u64 prop_values_ptr;

	__u32 count_modes;
	__u32 count_props;
	__u32 count_encoders;

	__u32 encoder_id; /**< Current Encoder */
	__u32 connector_id; /**< Id */
	__u32 connector_type;
	__u32 connector_type_id;

	__u32 connection;
	__u32 mm_width, mm_height; /**< HxW in millimeters */
	__u32 subpixel;
};

#define DRM_MODE_PROP_PENDING	(1<<0)
#define DRM_MODE_PROP_RANGE	(1<<1)
#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
#define DRM_MODE_PROP_BLOB	(1<<4)

struct drm_mode_property_enum {
	__u64 value;
	char name[DRM_PROP_NAME_LEN];
};

struct drm_mode_get_property {
	__u64 values_ptr; /* values and blob lengths */
	__u64 enum_blob_ptr; /* enum and blob id ptrs */

	__u32 prop_id;
	__u32 flags;
	char name[DRM_PROP_NAME_LEN];

	__u32 count_values;
	__u32 count_enum_blobs;
};

struct drm_mode_connector_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 connector_id;
};

struct drm_mode_get_blob {
	__u32 blob_id;
	__u32 length;
	__u64 data;
};

struct drm_mode_fb_cmd {
	__u32 fb_id;
	__u32 width, height;
	__u32 pitch;
	__u32 bpp;
	__u32 depth;
	/* driver specific handle */
	__u32 handle;
};

#define DRM_MODE_FB_INTERLACED	(1<<0 /* for interlaced framebuffers */

struct drm_mode_fb_cmd2 {
	__u32 fb_id;
	__u32 width, height;
	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	__u32 flags; /* see above flags */

	/*
	 * In case of planar formats, this ioctl allows up to 4
	 * buffer objects with offets and pitches per plane.
	 * The pitch and offset order is dictated by the fourcc,
	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	 *
	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
	 *   followed by an interleaved U/V plane containing
	 *   8 bit 2x2 subsampled colour difference samples.
	 *
	 * So it would consist of Y as offset[0] and UV as
	 * offeset[1].  Note that offset[0] will generally
	 * be 0.
	 */
	__u32 handles[4];
	__u32 pitches[4]; /* pitch for each plane */
	__u32 offsets[4]; /* offset of each plane */
};

#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
#define DRM_MODE_FB_DIRTY_FLAGS         0x03

/*
 * Mark a region of a framebuffer as dirty.
 *
 * Some hardware does not automatically update display contents
 * as a hardware or software draw to a framebuffer. This ioctl
 * allows userspace to tell the kernel and the hardware what
 * regions of the framebuffer have changed.
 *
 * The kernel or hardware is free to update more then just the
 * region specified by the clip rects. The kernel or hardware
 * may also delay and/or coalesce several calls to dirty into a
 * single update.
 *
 * Userspace may annotate the updates, the annotates are a
 * promise made by the caller that the change is either a copy
 * of pixels or a fill of a single color in the region specified.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 * the number of updated regions are half of num_clips given,
 * where the clip rects are paired in src and dst. The width and
 * height of each one of the pairs must match.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 * promises that the region specified of the clip rects is filled
 * completely with a single color as given in the color argument.
 */

struct drm_mode_fb_dirty_cmd {
	__u32 fb_id;
	__u32 flags;
	__u32 color;
	__u32 num_clips;
	__u64 clips_ptr;
};

struct drm_mode_mode_cmd {
	__u32 connector_id;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_CURSOR_BO	(1<<0)
#define DRM_MODE_CURSOR_MOVE	(1<<1)

/*
 * depending on the value in flags different members are used.
 *
 * CURSOR_BO uses
 *    crtc
 *    width
 *    height
 *    handle - if 0 turns the cursor of
 *
 * CURSOR_MOVE uses
 *    crtc
 *    x
 *    y
 */
struct drm_mode_cursor {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
};

struct drm_mode_crtc_lut {
	__u32 crtc_id;
	__u32 gamma_size;

	/* pointers to arrays */
	__u64 red;
	__u64 green;
	__u64 blue;
};

#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT

/*
 * Request a page flip on the specified crtc.
 *
 * This ioctl will ask KMS to schedule a page flip for the specified
 * crtc.  Once any pending rendering targeting the specified fb (as of
 * ioctl time) has completed, the crtc will be reprogrammed to display
 * that fb after the next vertical refresh.  The ioctl returns
 * immediately, but subsequent rendering to the current fb will block
 * in the execbuffer ioctl until the page flip happens.  If a page
 * flip is already pending as the ioctl is called, EBUSY will be
 * returned.
 *
 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 * request that drm sends back a vblank event (see drm.h: struct
 * drm_event_vblank) when the page flip is done.  The user_data field
 * passed in with this ioctl will be returned as the user_data field
 * in the vblank event struct.
 *
 * The reserved field must be zero until we figure out something
 * clever to use it for.
 */

struct drm_mode_crtc_page_flip {
	__u32 crtc_id;
	__u32 fb_id;
	__u32 flags;
	__u32 reserved;
	__u64 user_data;
};

/* create a dumb scanout buffer */
struct drm_mode_create_dumb {
	uint32_t height;
	uint32_t width;
	uint32_t bpp;
	uint32_t flags;
	/* handle, pitch, size will be returned */
	uint32_t handle;
	uint32_t pitch;
	uint64_t size;
};

/* set up for mmap of a dumb scanout buffer */
struct drm_mode_map_dumb {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 pad;
	/**
	 * Fake offset to use for subsequent mmap call
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 offset;
};

struct drm_mode_destroy_dumb {
	uint32_t handle;
};

#endif
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
	4	* Copyright (c) 2008 Red Hat Inc.
	5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
	6	* Copyright (c) 2007-2008 Intel Corporation
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	24	* IN THE SOFTWARE.
	25	*/
	26
	27	#ifndef _DRM_MODE_H
	28	#define _DRM_MODE_H
	29
e0c8463a JB	30	#define DRM_DISPLAY_INFO_LEN 32
	31	#define DRM_CONNECTOR_NAME_LEN 32
	32	#define DRM_DISPLAY_MODE_LEN 32
	33	#define DRM_PROP_NAME_LEN 32
f453ba04 DA	34
	35	#define DRM_MODE_TYPE_BUILTIN (1<<0)
	36	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)
	37	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)
	38	#define DRM_MODE_TYPE_PREFERRED (1<<3)
	39	#define DRM_MODE_TYPE_DEFAULT (1<<4)
	40	#define DRM_MODE_TYPE_USERDEF (1<<5)
	41	#define DRM_MODE_TYPE_DRIVER (1<<6)
	42
	43	/* Video mode flags */
	44	/* bit compatible with the xorg definitions. */
	45	#define DRM_MODE_FLAG_PHSYNC (1<<0)
	46	#define DRM_MODE_FLAG_NHSYNC (1<<1)
	47	#define DRM_MODE_FLAG_PVSYNC (1<<2)
	48	#define DRM_MODE_FLAG_NVSYNC (1<<3)
	49	#define DRM_MODE_FLAG_INTERLACE (1<<4)
	50	#define DRM_MODE_FLAG_DBLSCAN (1<<5)
	51	#define DRM_MODE_FLAG_CSYNC (1<<6)
	52	#define DRM_MODE_FLAG_PCSYNC (1<<7)
	53	#define DRM_MODE_FLAG_NCSYNC (1<<8)
	54	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
	55	#define DRM_MODE_FLAG_BCAST (1<<10)
	56	#define DRM_MODE_FLAG_PIXMUX (1<<11)
	57	#define DRM_MODE_FLAG_DBLCLK (1<<12)
	58	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
	59
	60	/* DPMS flags */
	61	/* bit compatible with the xorg definitions. */
e0c8463a JB	62	#define DRM_MODE_DPMS_ON 0
	63	#define DRM_MODE_DPMS_STANDBY 1
	64	#define DRM_MODE_DPMS_SUSPEND 2
	65	#define DRM_MODE_DPMS_OFF 3
f453ba04 DA	66
f453ba04 DA	67	/* Scaling mode options */
53bd8389 JB	68	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
	69	software can still scale) */
	70	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
	71	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
	72	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
f453ba04 DA	73
f453ba04 DA	74	/* Dithering mode options */
e0c8463a JB	75	#define DRM_MODE_DITHERING_OFF 0
e0c8463a JB	76	#define DRM_MODE_DITHERING_ON 1
92897b5c	77	#define DRM_MODE_DITHERING_AUTO 2
f453ba04	78
884840aa JB	79	/* Dirty info options */
	80	#define DRM_MODE_DIRTY_OFF 0
	81	#define DRM_MODE_DIRTY_ON 1
	82	#define DRM_MODE_DIRTY_ANNOTATE 2
	83
f453ba04	84	struct drm_mode_modeinfo {
1d7f83d5 AB	85	__u32 clock;
	86	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	87	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
f453ba04	88
fa5829b3	89	__u32 vrefresh;
f453ba04	90
1d7f83d5 AB	91	__u32 flags;
1d7f83d5 AB	92	__u32 type;
f453ba04 DA	93	char name[DRM_DISPLAY_MODE_LEN];
	94	};
	95
	96	struct drm_mode_card_res {
1d7f83d5 AB	97	__u64 fb_id_ptr;
	98	__u64 crtc_id_ptr;
	99	__u64 connector_id_ptr;
	100	__u64 encoder_id_ptr;
	101	__u32 count_fbs;
	102	__u32 count_crtcs;
	103	__u32 count_connectors;
	104	__u32 count_encoders;
	105	__u32 min_width, max_width;
	106	__u32 min_height, max_height;
f453ba04 DA	107	};
	108
	109	struct drm_mode_crtc {
1d7f83d5 AB	110	__u64 set_connectors_ptr;
1d7f83d5 AB	111	__u32 count_connectors;
f453ba04	112
1d7f83d5 AB	113	__u32 crtc_id; /*< Id /
1d7f83d5 AB	114	__u32 fb_id; /*< Id of framebuffer /
f453ba04	115
1d7f83d5	116	__u32 x, y; /*< Position on the frameuffer /
f453ba04	117
1d7f83d5 AB	118	__u32 gamma_size;
1d7f83d5 AB	119	__u32 mode_valid;
f453ba04 DA	120	struct drm_mode_modeinfo mode;
	121	};
	122
8cf5c917 JB	123	#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
	124	#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
	125
	126	/* Planes blend with or override other bits on the CRTC */
	127	struct drm_mode_set_plane {
	128	__u32 plane_id;
	129	__u32 crtc_id;
	130	__u32 fb_id; /* fb object contains surface format type */
	131	__u32 flags; /* see above flags */
	132
	133	/* Signed dest location allows it to be partially off screen */
	134	__s32 crtc_x, crtc_y;
	135	__u32 crtc_w, crtc_h;
	136
	137	/* Source values are 16.16 fixed point */
	138	__u32 src_x, src_y;
	139	__u32 src_h, src_w;
	140	};
	141
	142	struct drm_mode_get_plane {
	143	__u32 plane_id;
	144
	145	__u32 crtc_id;
	146	__u32 fb_id;
	147
	148	__u32 possible_crtcs;
	149	__u32 gamma_size;
	150
	151	__u32 count_format_types;
	152	__u64 format_type_ptr;
	153	};
	154
	155	struct drm_mode_get_plane_res {
	156	__u64 plane_id_ptr;
	157	__u32 count_planes;
	158	};
	159
	160	#define DRM_MODE_ENCODER_NONE 0
	161	#define DRM_MODE_ENCODER_DAC 1
	162	#define DRM_MODE_ENCODER_TMDS 2
	163	#define DRM_MODE_ENCODER_LVDS 3
	164	#define DRM_MODE_ENCODER_TVDAC 4
a7331e5c	165	#define DRM_MODE_ENCODER_VIRTUAL 5
f453ba04 DA	166
f453ba04 DA	167	struct drm_mode_get_encoder {
1d7f83d5 AB	168	__u32 encoder_id;
1d7f83d5 AB	169	__u32 encoder_type;
f453ba04	170
1d7f83d5	171	__u32 crtc_id; /*< Id of crtc /
f453ba04	172
1d7f83d5 AB	173	__u32 possible_crtcs;
1d7f83d5 AB	174	__u32 possible_clones;
f453ba04 DA	175	};
	176
	177	/* This is for connectors with multiple signal types. */
	178	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
e0c8463a JB	179	#define DRM_MODE_SUBCONNECTOR_Automatic 0
	180	#define DRM_MODE_SUBCONNECTOR_Unknown 0
	181	#define DRM_MODE_SUBCONNECTOR_DVID 3
	182	#define DRM_MODE_SUBCONNECTOR_DVIA 4
	183	#define DRM_MODE_SUBCONNECTOR_Composite 5
	184	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
	185	#define DRM_MODE_SUBCONNECTOR_Component 8
aeaa1ad3	186	#define DRM_MODE_SUBCONNECTOR_SCART 9
e0c8463a JB	187
	188	#define DRM_MODE_CONNECTOR_Unknown 0
	189	#define DRM_MODE_CONNECTOR_VGA 1
	190	#define DRM_MODE_CONNECTOR_DVII 2
	191	#define DRM_MODE_CONNECTOR_DVID 3
	192	#define DRM_MODE_CONNECTOR_DVIA 4
	193	#define DRM_MODE_CONNECTOR_Composite 5
	194	#define DRM_MODE_CONNECTOR_SVIDEO 6
	195	#define DRM_MODE_CONNECTOR_LVDS 7
	196	#define DRM_MODE_CONNECTOR_Component 8
	197	#define DRM_MODE_CONNECTOR_9PinDIN 9
	198	#define DRM_MODE_CONNECTOR_DisplayPort 10
	199	#define DRM_MODE_CONNECTOR_HDMIA 11
	200	#define DRM_MODE_CONNECTOR_HDMIB 12
74bd3c26	201	#define DRM_MODE_CONNECTOR_TV 13
7970e677	202	#define DRM_MODE_CONNECTOR_eDP 14
a7331e5c	203	#define DRM_MODE_CONNECTOR_VIRTUAL 15
f453ba04 DA	204
	205	struct drm_mode_get_connector {
	206
1d7f83d5 AB	207	__u64 encoders_ptr;
	208	__u64 modes_ptr;
	209	__u64 props_ptr;
	210	__u64 prop_values_ptr;
f453ba04	211
1d7f83d5 AB	212	__u32 count_modes;
	213	__u32 count_props;
	214	__u32 count_encoders;
f453ba04	215
1d7f83d5 AB	216	__u32 encoder_id; /*< Current Encoder /
	217	__u32 connector_id; /*< Id /
	218	__u32 connector_type;
	219	__u32 connector_type_id;
f453ba04	220
1d7f83d5 AB	221	__u32 connection;
	222	__u32 mm_width, mm_height; /*< HxW in millimeters /
	223	__u32 subpixel;
f453ba04 DA	224	};
f453ba04 DA	225
e0c8463a JB	226	#define DRM_MODE_PROP_PENDING (1<<0)
	227	#define DRM_MODE_PROP_RANGE (1<<1)
	228	#define DRM_MODE_PROP_IMMUTABLE (1<<2)
	229	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
	230	#define DRM_MODE_PROP_BLOB (1<<4)
f453ba04 DA	231
f453ba04 DA	232	struct drm_mode_property_enum {
1d7f83d5	233	__u64 value;
e0c8463a	234	char name[DRM_PROP_NAME_LEN];
f453ba04 DA	235	};
	236
	237	struct drm_mode_get_property {
1d7f83d5 AB	238	__u64 values_ptr; /* values and blob lengths */
1d7f83d5 AB	239	__u64 enum_blob_ptr; /* enum and blob id ptrs */
f453ba04	240
1d7f83d5 AB	241	__u32 prop_id;
1d7f83d5 AB	242	__u32 flags;
e0c8463a	243	char name[DRM_PROP_NAME_LEN];
f453ba04	244
1d7f83d5 AB	245	__u32 count_values;
1d7f83d5 AB	246	__u32 count_enum_blobs;
f453ba04 DA	247	};
	248
	249	struct drm_mode_connector_set_property {
1d7f83d5 AB	250	__u64 value;
	251	__u32 prop_id;
	252	__u32 connector_id;
f453ba04 DA	253	};
	254
	255	struct drm_mode_get_blob {
1d7f83d5 AB	256	__u32 blob_id;
	257	__u32 length;
	258	__u64 data;
f453ba04 DA	259	};
	260
	261	struct drm_mode_fb_cmd {
1d7f83d5 AB	262	__u32 fb_id;
	263	__u32 width, height;
	264	__u32 pitch;
	265	__u32 bpp;
	266	__u32 depth;
e0c8463a	267	/* driver specific handle */
1d7f83d5	268	__u32 handle;
f453ba04 DA	269	};
f453ba04 DA	270
308e5bcb JB	271	#define DRM_MODE_FB_INTERLACED (1<<0 /* for interlaced framebuffers */
	272
	273	struct drm_mode_fb_cmd2 {
	274	__u32 fb_id;
	275	__u32 width, height;
	276	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	277	__u32 flags; /* see above flags */
	278
	279	/*
	280	* In case of planar formats, this ioctl allows up to 4
	281	* buffer objects with offets and pitches per plane.
	282	* The pitch and offset order is dictated by the fourcc,
	283	* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	284	*
	285	* YUV 4:2:0 image with a plane of 8 bit Y samples
	286	* followed by an interleaved U/V plane containing
	287	* 8 bit 2x2 subsampled colour difference samples.
	288	*
	289	* So it would consist of Y as offset[0] and UV as
	290	* offeset[1]. Note that offset[0] will generally
	291	* be 0.
	292	*/
	293	__u32 handles[4];
	294	__u32 pitches[4]; /* pitch for each plane */
	295	__u32 offsets[4]; /* offset of each plane */
	296	};
	297
884840aa JB	298	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
	299	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
	300	#define DRM_MODE_FB_DIRTY_FLAGS 0x03
	301
	302	/*
	303	* Mark a region of a framebuffer as dirty.
	304	*
	305	* Some hardware does not automatically update display contents
	306	* as a hardware or software draw to a framebuffer. This ioctl
	307	* allows userspace to tell the kernel and the hardware what
	308	* regions of the framebuffer have changed.
	309	*
	310	* The kernel or hardware is free to update more then just the
	311	* region specified by the clip rects. The kernel or hardware
	312	* may also delay and/or coalesce several calls to dirty into a
	313	* single update.
	314	*
	315	* Userspace may annotate the updates, the annotates are a
	316	* promise made by the caller that the change is either a copy
	317	* of pixels or a fill of a single color in the region specified.
	318	*
	319	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
	320	* the number of updated regions are half of num_clips given,
	321	* where the clip rects are paired in src and dst. The width and
	322	* height of each one of the pairs must match.
	323	*
	324	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
	325	* promises that the region specified of the clip rects is filled
	326	* completely with a single color as given in the color argument.
	327	*/
	328
	329	struct drm_mode_fb_dirty_cmd {
	330	__u32 fb_id;
	331	__u32 flags;
	332	__u32 color;
	333	__u32 num_clips;
	334	__u64 clips_ptr;
	335	};
	336
f453ba04	337	struct drm_mode_mode_cmd {
1d7f83d5	338	__u32 connector_id;
f453ba04 DA	339	struct drm_mode_modeinfo mode;
	340	};
	341
e0c8463a JB	342	#define DRM_MODE_CURSOR_BO (1<<0)
e0c8463a JB	343	#define DRM_MODE_CURSOR_MOVE (1<<1)
f453ba04 DA	344
f453ba04 DA	345	/*
25985edc	346	* depending on the value in flags different members are used.
f453ba04 DA	347	*
	348	* CURSOR_BO uses
	349	* crtc
	350	* width
	351	* height
	352	* handle - if 0 turns the cursor of
	353	*
	354	* CURSOR_MOVE uses
	355	* crtc
	356	* x
	357	* y
	358	*/
	359	struct drm_mode_cursor {
1d7f83d5 AB	360	__u32 flags;
	361	__u32 crtc_id;
	362	__s32 x;
	363	__s32 y;
	364	__u32 width;
	365	__u32 height;
e0c8463a	366	/* driver specific handle */
1d7f83d5	367	__u32 handle;
f453ba04 DA	368	};
	369
	370	struct drm_mode_crtc_lut {
1d7f83d5 AB	371	__u32 crtc_id;
1d7f83d5 AB	372	__u32 gamma_size;
f453ba04 DA	373
f453ba04 DA	374	/* pointers to arrays */
1d7f83d5 AB	375	__u64 red;
	376	__u64 green;
	377	__u64 blue;
f453ba04 DA	378	};
f453ba04 DA	379
d91d8a3f KH	380	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
	381	#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
	382
	383	/*
	384	* Request a page flip on the specified crtc.
	385	*
	386	* This ioctl will ask KMS to schedule a page flip for the specified
	387	* crtc. Once any pending rendering targeting the specified fb (as of
	388	* ioctl time) has completed, the crtc will be reprogrammed to display
	389	* that fb after the next vertical refresh. The ioctl returns
	390	* immediately, but subsequent rendering to the current fb will block
	391	* in the execbuffer ioctl until the page flip happens. If a page
	392	* flip is already pending as the ioctl is called, EBUSY will be
	393	* returned.
	394	*
	395	* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
	396	* request that drm sends back a vblank event (see drm.h: struct
	397	* drm_event_vblank) when the page flip is done. The user_data field
	398	* passed in with this ioctl will be returned as the user_data field
	399	* in the vblank event struct.
	400	*
	401	* The reserved field must be zero until we figure out something
	402	* clever to use it for.
	403	*/
	404
	405	struct drm_mode_crtc_page_flip {
	406	__u32 crtc_id;
	407	__u32 fb_id;
	408	__u32 flags;
	409	__u32 reserved;
	410	__u64 user_data;
	411	};
	412
ff72145b DA	413	/* create a dumb scanout buffer */
	414	struct drm_mode_create_dumb {
	415	uint32_t height;
	416	uint32_t width;
	417	uint32_t bpp;
	418	uint32_t flags;
	419	/* handle, pitch, size will be returned */
	420	uint32_t handle;
	421	uint32_t pitch;
	422	uint64_t size;
	423	};
	424
	425	/* set up for mmap of a dumb scanout buffer */
	426	struct drm_mode_map_dumb {
	427	/** Handle for the object being mapped. */
	428	__u32 handle;
	429	__u32 pad;
	430	/**
	431	* Fake offset to use for subsequent mmap call
	432	*
	433	* This is a fixed-size type for 32/64 compatibility.
	434	*/
	435	__u64 offset;
	436	};
	437
	438	struct drm_mode_destroy_dumb {
	439	uint32_t handle;
	440	};
	441
f453ba04	442	#endif