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1 | /* |
2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #ifndef __DT_BINDINGS_CLOCK_IMX27_H | |
11 | #define __DT_BINDINGS_CLOCK_IMX27_H | |
12 | ||
13 | #define IMX27_CLK_DUMMY 0 | |
14 | #define IMX27_CLK_CKIH 1 | |
15 | #define IMX27_CLK_CKIL 2 | |
16 | #define IMX27_CLK_MPLL 3 | |
17 | #define IMX27_CLK_SPLL 4 | |
18 | #define IMX27_CLK_MPLL_MAIN2 5 | |
19 | #define IMX27_CLK_AHB 6 | |
20 | #define IMX27_CLK_IPG 7 | |
21 | #define IMX27_CLK_NFC_DIV 8 | |
22 | #define IMX27_CLK_PER1_DIV 9 | |
23 | #define IMX27_CLK_PER2_DIV 10 | |
24 | #define IMX27_CLK_PER3_DIV 11 | |
25 | #define IMX27_CLK_PER4_DIV 12 | |
26 | #define IMX27_CLK_VPU_SEL 13 | |
27 | #define IMX27_CLK_VPU_DIV 14 | |
28 | #define IMX27_CLK_USB_DIV 15 | |
29 | #define IMX27_CLK_CPU_SEL 16 | |
30 | #define IMX27_CLK_CLKO_SEL 17 | |
31 | #define IMX27_CLK_CPU_DIV 18 | |
32 | #define IMX27_CLK_CLKO_DIV 19 | |
33 | #define IMX27_CLK_SSI1_SEL 20 | |
34 | #define IMX27_CLK_SSI2_SEL 21 | |
35 | #define IMX27_CLK_SSI1_DIV 22 | |
36 | #define IMX27_CLK_SSI2_DIV 23 | |
37 | #define IMX27_CLK_CLKO_EN 24 | |
38 | #define IMX27_CLK_SSI2_IPG_GATE 25 | |
39 | #define IMX27_CLK_SSI1_IPG_GATE 26 | |
40 | #define IMX27_CLK_SLCDC_IPG_GATE 27 | |
41 | #define IMX27_CLK_SDHC3_IPG_GATE 28 | |
42 | #define IMX27_CLK_SDHC2_IPG_GATE 29 | |
43 | #define IMX27_CLK_SDHC1_IPG_GATE 30 | |
44 | #define IMX27_CLK_SCC_IPG_GATE 31 | |
45 | #define IMX27_CLK_SAHARA_IPG_GATE 32 | |
46 | #define IMX27_CLK_RTC_IPG_GATE 33 | |
47 | #define IMX27_CLK_PWM_IPG_GATE 34 | |
48 | #define IMX27_CLK_OWIRE_IPG_GATE 35 | |
49 | #define IMX27_CLK_LCDC_IPG_GATE 36 | |
50 | #define IMX27_CLK_KPP_IPG_GATE 37 | |
51 | #define IMX27_CLK_IIM_IPG_GATE 38 | |
52 | #define IMX27_CLK_I2C2_IPG_GATE 39 | |
53 | #define IMX27_CLK_I2C1_IPG_GATE 40 | |
54 | #define IMX27_CLK_GPT6_IPG_GATE 41 | |
55 | #define IMX27_CLK_GPT5_IPG_GATE 42 | |
56 | #define IMX27_CLK_GPT4_IPG_GATE 43 | |
57 | #define IMX27_CLK_GPT3_IPG_GATE 44 | |
58 | #define IMX27_CLK_GPT2_IPG_GATE 45 | |
59 | #define IMX27_CLK_GPT1_IPG_GATE 46 | |
60 | #define IMX27_CLK_GPIO_IPG_GATE 47 | |
61 | #define IMX27_CLK_FEC_IPG_GATE 48 | |
62 | #define IMX27_CLK_EMMA_IPG_GATE 49 | |
63 | #define IMX27_CLK_DMA_IPG_GATE 50 | |
64 | #define IMX27_CLK_CSPI3_IPG_GATE 51 | |
65 | #define IMX27_CLK_CSPI2_IPG_GATE 52 | |
66 | #define IMX27_CLK_CSPI1_IPG_GATE 53 | |
67 | #define IMX27_CLK_NFC_BAUD_GATE 54 | |
68 | #define IMX27_CLK_SSI2_BAUD_GATE 55 | |
69 | #define IMX27_CLK_SSI1_BAUD_GATE 56 | |
70 | #define IMX27_CLK_VPU_BAUD_GATE 57 | |
71 | #define IMX27_CLK_PER4_GATE 58 | |
72 | #define IMX27_CLK_PER3_GATE 59 | |
73 | #define IMX27_CLK_PER2_GATE 60 | |
74 | #define IMX27_CLK_PER1_GATE 61 | |
75 | #define IMX27_CLK_USB_AHB_GATE 62 | |
76 | #define IMX27_CLK_SLCDC_AHB_GATE 63 | |
77 | #define IMX27_CLK_SAHARA_AHB_GATE 64 | |
78 | #define IMX27_CLK_LCDC_AHB_GATE 65 | |
79 | #define IMX27_CLK_VPU_AHB_GATE 66 | |
80 | #define IMX27_CLK_FEC_AHB_GATE 67 | |
81 | #define IMX27_CLK_EMMA_AHB_GATE 68 | |
82 | #define IMX27_CLK_EMI_AHB_GATE 69 | |
83 | #define IMX27_CLK_DMA_AHB_GATE 70 | |
84 | #define IMX27_CLK_CSI_AHB_GATE 71 | |
85 | #define IMX27_CLK_BROM_AHB_GATE 72 | |
86 | #define IMX27_CLK_ATA_AHB_GATE 73 | |
87 | #define IMX27_CLK_WDOG_IPG_GATE 74 | |
88 | #define IMX27_CLK_USB_IPG_GATE 75 | |
89 | #define IMX27_CLK_UART6_IPG_GATE 76 | |
90 | #define IMX27_CLK_UART5_IPG_GATE 77 | |
91 | #define IMX27_CLK_UART4_IPG_GATE 78 | |
92 | #define IMX27_CLK_UART3_IPG_GATE 79 | |
93 | #define IMX27_CLK_UART2_IPG_GATE 80 | |
94 | #define IMX27_CLK_UART1_IPG_GATE 81 | |
95 | #define IMX27_CLK_CKIH_DIV1P5 82 | |
96 | #define IMX27_CLK_FPM 83 | |
97 | #define IMX27_CLK_MPLL_OSC_SEL 84 | |
98 | #define IMX27_CLK_MPLL_SEL 85 | |
99 | #define IMX27_CLK_SPLL_GATE 86 | |
100 | #define IMX27_CLK_MSHC_DIV 87 | |
101 | #define IMX27_CLK_RTIC_IPG_GATE 88 | |
102 | #define IMX27_CLK_MSHC_IPG_GATE 89 | |
103 | #define IMX27_CLK_RTIC_AHB_GATE 90 | |
104 | #define IMX27_CLK_MSHC_BAUD_GATE 91 | |
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105 | #define IMX27_CLK_CKIH_GATE 92 |
106 | #define IMX27_CLK_MAX 93 | |
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107 | |
108 | #endif |