Commit | Line | Data |
---|---|---|
04d11269 CF |
1 | /** |
2 | * This header provides index for the reset controller | |
3 | * based on hi6220 SoC. | |
4 | */ | |
5 | #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 | |
6 | #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 | |
7 | ||
8 | #define PERIPH_RSTDIS0_MMC0 0x000 | |
9 | #define PERIPH_RSTDIS0_MMC1 0x001 | |
10 | #define PERIPH_RSTDIS0_MMC2 0x002 | |
11 | #define PERIPH_RSTDIS0_NANDC 0x003 | |
12 | #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 | |
13 | #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 | |
14 | #define PERIPH_RSTDIS0_USBOTG 0x006 | |
15 | #define PERIPH_RSTDIS0_USBOTG_32K 0x007 | |
16 | #define PERIPH_RSTDIS1_HIFI 0x100 | |
17 | #define PERIPH_RSTDIS1_DIGACODEC 0x105 | |
18 | #define PERIPH_RSTEN2_IPF 0x200 | |
19 | #define PERIPH_RSTEN2_SOCP 0x201 | |
20 | #define PERIPH_RSTEN2_DMAC 0x202 | |
21 | #define PERIPH_RSTEN2_SECENG 0x203 | |
22 | #define PERIPH_RSTEN2_ABB 0x204 | |
23 | #define PERIPH_RSTEN2_HPM0 0x205 | |
24 | #define PERIPH_RSTEN2_HPM1 0x206 | |
25 | #define PERIPH_RSTEN2_HPM2 0x207 | |
26 | #define PERIPH_RSTEN2_HPM3 0x208 | |
27 | #define PERIPH_RSTEN3_CSSYS 0x300 | |
28 | #define PERIPH_RSTEN3_I2C0 0x301 | |
29 | #define PERIPH_RSTEN3_I2C1 0x302 | |
30 | #define PERIPH_RSTEN3_I2C2 0x303 | |
31 | #define PERIPH_RSTEN3_I2C3 0x304 | |
32 | #define PERIPH_RSTEN3_UART1 0x305 | |
33 | #define PERIPH_RSTEN3_UART2 0x306 | |
34 | #define PERIPH_RSTEN3_UART3 0x307 | |
35 | #define PERIPH_RSTEN3_UART4 0x308 | |
36 | #define PERIPH_RSTEN3_SSP 0x309 | |
37 | #define PERIPH_RSTEN3_PWM 0x30a | |
38 | #define PERIPH_RSTEN3_BLPWM 0x30b | |
39 | #define PERIPH_RSTEN3_TSENSOR 0x30c | |
40 | #define PERIPH_RSTEN3_DAPB 0x312 | |
41 | #define PERIPH_RSTEN3_HKADC 0x313 | |
42 | #define PERIPH_RSTEN3_CODEC_SSI 0x314 | |
43 | #define PERIPH_RSTEN3_PMUSSI1 0x316 | |
44 | #define PERIPH_RSTEN8_RS0 0x400 | |
45 | #define PERIPH_RSTEN8_RS2 0x401 | |
46 | #define PERIPH_RSTEN8_RS3 0x402 | |
47 | #define PERIPH_RSTEN8_MS0 0x403 | |
48 | #define PERIPH_RSTEN8_MS2 0x405 | |
49 | #define PERIPH_RSTEN8_XG2RAM0 0x406 | |
50 | #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 | |
51 | #define PERIPH_RSTEN8_SRAM 0x408 | |
52 | #define PERIPH_RSTEN8_HARQ 0x40a | |
53 | #define PERIPH_RSTEN8_DDRC 0x40c | |
54 | #define PERIPH_RSTEN8_DDRC_APB 0x40d | |
55 | #define PERIPH_RSTEN8_DDRPACK_APB 0x40e | |
56 | #define PERIPH_RSTEN8_DDRT 0x411 | |
57 | #define PERIPH_RSDIST9_CARM_DAP 0x500 | |
58 | #define PERIPH_RSDIST9_CARM_ATB 0x501 | |
59 | #define PERIPH_RSDIST9_CARM_LBUS 0x502 | |
60 | #define PERIPH_RSDIST9_CARM_POR 0x503 | |
61 | #define PERIPH_RSDIST9_CARM_CORE 0x504 | |
62 | #define PERIPH_RSDIST9_CARM_DBG 0x505 | |
63 | #define PERIPH_RSDIST9_CARM_L2 0x506 | |
64 | #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 | |
65 | #define PERIPH_RSDIST9_CARM_ETM 0x508 | |
66 | ||
339d00cb XL |
67 | #define MEDIA_G3D 0 |
68 | #define MEDIA_CODEC_VPU 2 | |
69 | #define MEDIA_CODEC_JPEG 3 | |
70 | #define MEDIA_ISP 4 | |
71 | #define MEDIA_ADE 5 | |
72 | #define MEDIA_MMU 6 | |
73 | #define MEDIA_XG2RAM1 7 | |
74 | ||
04d11269 | 75 | #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ |