Commit | Line | Data |
---|---|---|
26f59a9e | 1 | /* This file defines the interface between the d10v simulator and gdb. |
18c0df9e | 2 | |
4b95cf5c | 3 | Copyright (C) 1999-2014 Free Software Foundation, Inc. |
26f59a9e | 4 | |
1d52ba21 | 5 | This file is part of GDB. |
26f59a9e | 6 | |
1d52ba21 JB |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
26f59a9e | 11 | |
1d52ba21 JB |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
26f59a9e | 16 | |
1d52ba21 JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
26f59a9e MM |
19 | |
20 | #if !defined (SIM_D10V_H) | |
21 | #define SIM_D10V_H | |
22 | ||
23 | #ifdef __cplusplus | |
24 | extern "C" { // } | |
25 | #endif | |
26 | ||
27 | /* GDB interprets addresses as: | |
28 | ||
29 | 0x00xxxxxx: Physical unified memory segment (Unified memory) | |
30 | 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) | |
31 | 0x02xxxxxx: Physical data memory segment (On-chip data memory) | |
32 | 0x10xxxxxx: Logical data address segment (DMAP translated memory) | |
33 | 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) | |
34 | ||
35 | The remote d10v board interprets addresses as: | |
36 | ||
37 | 0x00xxxxxx: Physical unified memory segment (Unified memory) | |
38 | 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) | |
39 | 0x02xxxxxx: Physical data memory segment (On-chip data memory) | |
40 | ||
41 | The following translate a virtual DMAP/IMAP offset into a physical | |
42 | memory segment assigning the translated address to PHYS. Since a | |
43 | memory access may cross a page boundrary the number of bytes for | |
44 | which the translation is applicable (or 0 for an invalid virtual | |
45 | offset) is returned. */ | |
46 | ||
47 | enum | |
48 | { | |
49 | SIM_D10V_MEMORY_UNIFIED = 0x00000000, | |
50 | SIM_D10V_MEMORY_INSN = 0x01000000, | |
51 | SIM_D10V_MEMORY_DATA = 0x02000000, | |
52 | SIM_D10V_MEMORY_DMAP = 0x10000000, | |
53 | SIM_D10V_MEMORY_IMAP = 0x11000000 | |
54 | }; | |
55 | ||
56 | extern unsigned long sim_d10v_translate_dmap_addr | |
57 | (unsigned long offset, | |
58 | int nr_bytes, | |
59 | unsigned long *phys, | |
f6684c31 AC |
60 | void *regcache, |
61 | unsigned long (*dmap_register) (void *regcache, int reg_nr)); | |
26f59a9e MM |
62 | |
63 | extern unsigned long sim_d10v_translate_imap_addr | |
64 | (unsigned long offset, | |
65 | int nr_bytes, | |
66 | unsigned long *phys, | |
f6684c31 AC |
67 | void *regcache, |
68 | unsigned long (*imap_register) (void *regcache, int reg_nr)); | |
26f59a9e MM |
69 | |
70 | extern unsigned long sim_d10v_translate_addr | |
71 | (unsigned long vaddr, | |
72 | int nr_bytes, | |
73 | unsigned long *phys, | |
f6684c31 AC |
74 | void *regcache, |
75 | unsigned long (*dmap_register) (void *regcache, int reg_nr), | |
76 | unsigned long (*imap_register) (void *regcache, int reg_nr)); | |
26f59a9e MM |
77 | |
78 | ||
79 | /* The simulator makes use of the following register information. */ | |
80 | ||
18c0df9e AC |
81 | enum sim_d10v_regs |
82 | { | |
83 | SIM_D10V_R0_REGNUM, | |
84 | SIM_D10V_R1_REGNUM, | |
85 | SIM_D10V_R2_REGNUM, | |
86 | SIM_D10V_R3_REGNUM, | |
87 | SIM_D10V_R4_REGNUM, | |
88 | SIM_D10V_R5_REGNUM, | |
89 | SIM_D10V_R6_REGNUM, | |
90 | SIM_D10V_R7_REGNUM, | |
91 | SIM_D10V_R8_REGNUM, | |
92 | SIM_D10V_R9_REGNUM, | |
93 | SIM_D10V_R10_REGNUM, | |
94 | SIM_D10V_R11_REGNUM, | |
95 | SIM_D10V_R12_REGNUM, | |
96 | SIM_D10V_R13_REGNUM, | |
97 | SIM_D10V_R14_REGNUM, | |
98 | SIM_D10V_R15_REGNUM, | |
99 | SIM_D10V_CR0_REGNUM, | |
100 | SIM_D10V_CR1_REGNUM, | |
101 | SIM_D10V_CR2_REGNUM, | |
102 | SIM_D10V_CR3_REGNUM, | |
103 | SIM_D10V_CR4_REGNUM, | |
104 | SIM_D10V_CR5_REGNUM, | |
105 | SIM_D10V_CR6_REGNUM, | |
106 | SIM_D10V_CR7_REGNUM, | |
107 | SIM_D10V_CR8_REGNUM, | |
108 | SIM_D10V_CR9_REGNUM, | |
109 | SIM_D10V_CR10_REGNUM, | |
110 | SIM_D10V_CR11_REGNUM, | |
111 | SIM_D10V_CR12_REGNUM, | |
112 | SIM_D10V_CR13_REGNUM, | |
113 | SIM_D10V_CR14_REGNUM, | |
114 | SIM_D10V_CR15_REGNUM, | |
115 | SIM_D10V_A0_REGNUM, | |
116 | SIM_D10V_A1_REGNUM, | |
117 | SIM_D10V_SPI_REGNUM, | |
118 | SIM_D10V_SPU_REGNUM, | |
119 | SIM_D10V_IMAP0_REGNUM, | |
120 | SIM_D10V_IMAP1_REGNUM, | |
121 | SIM_D10V_DMAP0_REGNUM, | |
122 | SIM_D10V_DMAP1_REGNUM, | |
123 | SIM_D10V_DMAP2_REGNUM, | |
124 | SIM_D10V_DMAP3_REGNUM, | |
125 | SIM_D10V_TS2_DMAP_REGNUM | |
126 | }; | |
127 | ||
26f59a9e | 128 | enum |
18c0df9e AC |
129 | { |
130 | SIM_D10V_NR_R_REGS = 16, | |
131 | SIM_D10V_NR_A_REGS = 2, | |
132 | SIM_D10V_NR_IMAP_REGS = 2, | |
133 | SIM_D10V_NR_DMAP_REGS = 4, | |
134 | SIM_D10V_NR_CR_REGS = 16 | |
135 | }; | |
26f59a9e MM |
136 | |
137 | #ifdef __cplusplus | |
138 | } | |
139 | #endif | |
140 | ||
141 | #endif |