[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/irqchip/arm-gic-common.h>

#define VGIC_NR_IRQS_LEGACY	256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_MAX_IRQS		1024
#define VGIC_V2_MAX_CPUS	8
#define VGIC_V3_MAX_CPUS	255

#if (VGIC_NR_IRQS_LEGACY & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	/*
	 * - One UL per VCPU for private interrupts (assumes UL is at
	 *   least 32 bits)
	 * - As many UL as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, one UL per vcpu (the state for vcpu n is in
	 * private[n]). The shared interrupts are accessed via the
	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	 */
	unsigned long *private;
	unsigned long *shared;
};

struct vgic_bytemap {
	/*
	 * - 8 u32 per VCPU for private interrupts
	 * - As many u32 as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, (the state for vcpu n is in private[n*8] to
	 * private[n*8 + 7]). The shared interrupts are accessed via
	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	 * shared[(n-32)/4] word).
	 */
	u32 *private;
	u32 *shared;
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)
#define LR_HW			(1 << 3)

struct vgic_lr {
	unsigned irq:10;
	union {
		unsigned hwirq:10;
		unsigned source:3;
	};
	unsigned state:4;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	void	(*clear_eisr)(struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
	int		max_gic_vcpus;
	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool		can_emulate_gicv2;
};

struct vgic_vm_ops {
	bool	(*queue_sgi)(struct kvm_vcpu *, int irq);
	void	(*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
	int	(*init_model)(struct kvm *);
	int	(*map_resources)(struct kvm *, const struct vgic_params *);
};

struct vgic_io_device {
	gpa_t addr;
	int len;
	const struct vgic_io_range *reg_ranges;
	struct kvm_vcpu *redist_vcpu;
	struct kvm_io_device dev;
};

struct irq_phys_map {
	u32			virt_irq;
	u32			phys_irq;
	u32			irq;
};

struct irq_phys_map_entry {
	struct list_head	entry;
	struct rcu_head		rcu;
	struct irq_phys_map	map;
};

struct vgic_dist {
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	int			nr_cpus;
	int			nr_irqs;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	/* GICv2 and GICv3 use different mapped register blocks */
	union {
		phys_addr_t		vgic_cpu_base;
		phys_addr_t		vgic_redist_base;
	};

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Level-triggered interrupt external input is asserted */
	struct vgic_bitmap	irq_level;

	/*
	 * Interrupt state is pending on the distributor
	 */
	struct vgic_bitmap	irq_pending;

	/*
	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	 * interrupts.  Essentially holds the state of the flip-flop in
	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	 * Once set, it is only cleared for level-triggered interrupts on
	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	 */
	struct vgic_bitmap	irq_soft_pend;

	/* Level-triggered interrupt queued on VCPU interface */
	struct vgic_bitmap	irq_queued;

	/* Interrupt was active when unqueue from VCPU interface */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/*
	 * Source CPU per SGI and target CPU:
	 *
	 * Each byte represent a SGI observable on a VCPU, each bit of
	 * this byte indicating if the corresponding VCPU has
	 * generated this interrupt. This is a GICv2 feature only.
	 *
	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
	 * the SGIs observable on VCPUn.
	 */
	u8			*irq_sgi_sources;

	/*
	 * Target CPU for each SPI:
	 *
	 * Array of available SPI, each byte indicating the target
	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	 */
	u8			*irq_spi_cpu;

	/*
	 * Reverse lookup of irq_spi_cpu for faster compute pending:
	 *
	 * Array of bitmaps, one per VCPU, describing if IRQn is
	 * routed to a particular VCPU.
	 */
	struct vgic_bitmap	*irq_spi_target;

	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	u32			*irq_spi_mpidr;

	/* Bitmap indicating which CPU has something pending */
	unsigned long		*irq_pending_on_cpu;

	/* Bitmap indicating which CPU has active IRQs */
	unsigned long		*irq_active_on_cpu;

	struct vgic_vm_ops	vm_ops;
	struct vgic_io_device	dist_iodev;
	struct vgic_io_device	*redist_iodevs;

	/* Virtual irq to hwirq mapping */
	spinlock_t		irq_phys_map_lock;
	struct list_head	irq_phys_map_list;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_KVM_ARM_VGIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* Pending/active/both interrupts on this VCPU */
	DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);

	/* Pending/active/both shared interrupts, dynamically sized */
	unsigned long	*pending_shared;
	unsigned long   *active_shared;
	unsigned long   *pend_act_shared;

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	/* Protected by the distributor's irq_phys_map_lock */
	struct list_head	irq_phys_map_list;

	u64		live_lrs;
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_get_max_vcpus(void);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
			       struct irq_phys_map *map, bool level);
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
					   int virt_irq, int irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, struct irq_phys_map *map);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	(!!((k)->arch.vgic.nr_cpus))
#define vgic_ready(k)		((k)->arch.vgic.ready)

int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_KVM_ARM_VGIC_V3
int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
6777f77f	27	#include <kvm/iodev.h>
503a6286	28	#include <linux/irqchip/arm-gic-common.h>
1a89dd91	29
5fb66da6	30	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	31	#define VGIC_NR_SGIS 16
	32	#define VGIC_NR_PPIS 16
	33	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
8f186d52 MZ	34
8f186d52 MZ	35	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	36	#define VGIC_V3_MAX_LRS 16
c3c91836	37	#define VGIC_MAX_IRQS 1024
3caa2d8c	38	#define VGIC_V2_MAX_CPUS 8
ef748917	39	#define VGIC_V3_MAX_CPUS 255
b47ef92a	40
5fb66da6	41	#if (VGIC_NR_IRQS_LEGACY & 31)
b47ef92a MZ	42	#error "VGIC_NR_IRQS must be a multiple of 32"
	43	#endif
	44
5fb66da6	45	#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
b47ef92a MZ	46	#error "VGIC_NR_IRQS must be <= 1024"
	47	#endif
	48
	49	/*
	50	* The GIC distributor registers describing interrupts have two parts:
	51	* - 32 per-CPU interrupts (SGI + PPI)
	52	* - a bunch of shared interrupts (SPI)
	53	*/
	54	struct vgic_bitmap {
c1bfb577 MZ	55	/*
	56	* - One UL per VCPU for private interrupts (assumes UL is at
	57	* least 32 bits)
	58	* - As many UL as necessary for shared interrupts.
	59	*
	60	* The private interrupts are accessed via the "private"
	61	* field, one UL per vcpu (the state for vcpu n is in
	62	* private[n]). The shared interrupts are accessed via the
	63	* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	64	*/
	65	unsigned long *private;
	66	unsigned long *shared;
b47ef92a MZ	67	};
	68
	69	struct vgic_bytemap {
c1bfb577 MZ	70	/*
	71	* - 8 u32 per VCPU for private interrupts
	72	* - As many u32 as necessary for shared interrupts.
	73	*
	74	* The private interrupts are accessed via the "private"
	75	* field, (the state for vcpu n is in private[n*8] to
	76	* private[n*8 + 7]). The shared interrupts are accessed via
	77	* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	78	* shared[(n-32)/4] word).
	79	*/
	80	u32 *private;
	81	u32 *shared;
b47ef92a MZ	82	};
b47ef92a MZ	83
8d5c6b06 MZ	84	struct kvm_vcpu;
8d5c6b06 MZ	85
1a9b1305 MZ	86	enum vgic_type {
1a9b1305 MZ	87	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	88	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	89	};
1a9b1305 MZ	90
8d5c6b06 MZ	91	#define LR_STATE_PENDING (1 << 0)
	92	#define LR_STATE_ACTIVE (1 << 1)
	93	#define LR_STATE_MASK (3 << 0)
	94	#define LR_EOI_INT (1 << 2)
32d2d801	95	#define LR_HW (1 << 3)
8d5c6b06 MZ	96
8d5c6b06 MZ	97	struct vgic_lr {
32d2d801 MZ	98	unsigned irq:10;
	99	union {
	100	unsigned hwirq:10;
	101	unsigned source:3;
	102	};
	103	unsigned state:4;
8d5c6b06 MZ	104	};
8d5c6b06 MZ	105
beee38b9 MZ	106	struct vgic_vmcr {
	107	u32 ctlr;
	108	u32 abpr;
	109	u32 bpr;
	110	u32 pmr;
	111	};
	112
8d5c6b06 MZ	113	struct vgic_ops {
	114	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	115	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f	116	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	117	u64 (get_eisr)(const struct kvm_vcpu vcpu);
ae705930	118	void (clear_eisr)(struct kvm_vcpu vcpu);
495dd859	119	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	120	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	121	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	122	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	123	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	124	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	125	};
8d5c6b06 MZ	126
ca85f623	127	struct vgic_params {
1a9b1305 MZ	128	/* vgic type */
1a9b1305 MZ	129	enum vgic_type type;
ca85f623 MZ	130	/* Physical address of vgic virtual cpu interface */
	131	phys_addr_t vcpu_base;
	132	/* Number of list registers */
	133	u32 nr_lr;
	134	/* Interrupt number */
	135	unsigned int maint_irq;
	136	/* Virtual control interface base address */
	137	void __iomem *vctrl_base;
3caa2d8c	138	int max_gic_vcpus;
b5d84ff6 AP	139	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
b5d84ff6 AP	140	bool can_emulate_gicv2;
ca85f623 MZ	141	};
ca85f623 MZ	142
b26e5fda	143	struct vgic_vm_ops {
b26e5fda AP	144	bool (queue_sgi)(struct kvm_vcpu , int irq);
	145	void (add_sgi_source)(struct kvm_vcpu , int irq, int source);
	146	int (init_model)(struct kvm );
	147	int (map_resources)(struct kvm , const struct vgic_params *);
	148	};
	149
6777f77f AP	150	struct vgic_io_device {
	151	gpa_t addr;
	152	int len;
	153	const struct vgic_io_range *reg_ranges;
	154	struct kvm_vcpu *redist_vcpu;
	155	struct kvm_io_device dev;
	156	};
	157
6c3d63c9 MZ	158	struct irq_phys_map {
	159	u32 virt_irq;
	160	u32 phys_irq;
	161	u32 irq;
6c3d63c9 MZ	162	};
	163
	164	struct irq_phys_map_entry {
	165	struct list_head entry;
	166	struct rcu_head rcu;
	167	struct irq_phys_map map;
	168	};
	169
1a89dd91	170	struct vgic_dist {
b47ef92a	171	spinlock_t lock;
f982cf4e	172	bool in_kernel;
01ac5e34	173	bool ready;
b47ef92a	174
59892136 AP	175	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	176	u32 vgic_model;
	177
c1bfb577 MZ	178	int nr_cpus;
	179	int nr_irqs;
	180
b47ef92a MZ	181	/* Virtual control interface mapping */
	182	void __iomem *vctrl_base;
	183
330690cd CD	184	/* Distributor and vcpu interface mapping in the guest */
330690cd CD	185	phys_addr_t vgic_dist_base;
a0675c25 AP	186	/* GICv2 and GICv3 use different mapped register blocks */
	187	union {
	188	phys_addr_t vgic_cpu_base;
	189	phys_addr_t vgic_redist_base;
	190	};
b47ef92a MZ	191
	192	/* Distributor enabled */
	193	u32 enabled;
	194
	195	/* Interrupt enabled (one bit per IRQ) */
	196	struct vgic_bitmap irq_enabled;
	197
faa1b46c CD	198	/* Level-triggered interrupt external input is asserted */
	199	struct vgic_bitmap irq_level;
	200
	201	/*
	202	* Interrupt state is pending on the distributor
	203	*/
227844f5	204	struct vgic_bitmap irq_pending;
b47ef92a	205
faa1b46c CD	206	/*
	207	* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	208	* interrupts. Essentially holds the state of the flip-flop in
	209	* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	210	* Once set, it is only cleared for level-triggered interrupts on
	211	* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	212	*/
	213	struct vgic_bitmap irq_soft_pend;
	214
dbf20f9d CD	215	/* Level-triggered interrupt queued on VCPU interface */
dbf20f9d CD	216	struct vgic_bitmap irq_queued;
b47ef92a	217
47a98b15 CD	218	/* Interrupt was active when unqueue from VCPU interface */
	219	struct vgic_bitmap irq_active;
	220
b47ef92a MZ	221	/* Interrupt priority. Not used yet. */
	222	struct vgic_bytemap irq_priority;
	223
	224	/* Level/edge triggered */
	225	struct vgic_bitmap irq_cfg;
	226
c1bfb577 MZ	227	/*
	228	* Source CPU per SGI and target CPU:
	229	*
	230	* Each byte represent a SGI observable on a VCPU, each bit of
	231	* this byte indicating if the corresponding VCPU has
	232	* generated this interrupt. This is a GICv2 feature only.
	233	*
	234	* For VCPUn (n < 8), irq_sgi_sources[n16] to [n16 + 15] are
	235	* the SGIs observable on VCPUn.
	236	*/
	237	u8 *irq_sgi_sources;
b47ef92a	238
c1bfb577 MZ	239	/*
	240	* Target CPU for each SPI:
	241	*
	242	* Array of available SPI, each byte indicating the target
	243	* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	244	*/
	245	u8 *irq_spi_cpu;
	246
	247	/*
	248	* Reverse lookup of irq_spi_cpu for faster compute pending:
	249	*
	250	* Array of bitmaps, one per VCPU, describing if IRQn is
	251	* routed to a particular VCPU.
	252	*/
	253	struct vgic_bitmap *irq_spi_target;
b47ef92a	254
a0675c25 AP	255	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	256	u32 *irq_spi_mpidr;
	257
b47ef92a	258	/* Bitmap indicating which CPU has something pending */
c1bfb577	259	unsigned long *irq_pending_on_cpu;
b26e5fda	260
47a98b15 CD	261	/* Bitmap indicating which CPU has active IRQs */
	262	unsigned long *irq_active_on_cpu;
	263
b26e5fda	264	struct vgic_vm_ops vm_ops;
a9cf86f6	265	struct vgic_io_device dist_iodev;
fb8f61ab	266	struct vgic_io_device *redist_iodevs;
6c3d63c9 MZ	267
	268	/* Virtual irq to hwirq mapping */
	269	spinlock_t irq_phys_map_lock;
	270	struct list_head irq_phys_map_list;
1a89dd91 MZ	271	};
1a89dd91 MZ	272
eede821d MZ	273	struct vgic_v2_cpu_if {
	274	u32 vgic_hcr;
	275	u32 vgic_vmcr;
	276	u32 vgic_misr; /* Saved only */
2df36a5d CD	277	u64 vgic_eisr; /* Saved only */
2df36a5d CD	278	u64 vgic_elrsr; /* Saved only */
eede821d	279	u32 vgic_apr;
8f186d52	280	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	281	};
eede821d MZ	282
b2fb1c0d	283	struct vgic_v3_cpu_if {
4f64cb65	284	#ifdef CONFIG_KVM_ARM_VGIC_V3
b2fb1c0d MZ	285	u32 vgic_hcr;
b2fb1c0d MZ	286	u32 vgic_vmcr;
2f5fa41a	287	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	288	u32 vgic_misr; /* Saved only */
	289	u32 vgic_eisr; /* Saved only */
	290	u32 vgic_elrsr; /* Saved only */
	291	u32 vgic_ap0r[4];
	292	u32 vgic_ap1r[4];
	293	u64 vgic_lr[VGIC_V3_MAX_LRS];
	294	#endif
	295	};
	296
1a89dd91	297	struct vgic_cpu {
47a98b15	298	/* Pending/active/both interrupts on this VCPU */
5fdf876d MM	299	DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
	300	DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
	301	DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
47a98b15 CD	302
47a98b15 CD	303	/* Pending/active/both shared interrupts, dynamically sized */
c1bfb577	304	unsigned long *pending_shared;
47a98b15 CD	305	unsigned long *active_shared;
47a98b15 CD	306	unsigned long *pend_act_shared;
9d949dce	307
9d949dce MZ	308	/* Number of list registers on this CPU */
	309	int nr_lr;
	310
	311	/* CPU vif control registers for world switch */
eede821d MZ	312	union {
eede821d MZ	313	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	314	struct vgic_v3_cpu_if vgic_v3;
eede821d	315	};
6c3d63c9 MZ	316
	317	/* Protected by the distributor's irq_phys_map_lock */
	318	struct list_head irq_phys_map_list;
59f00ff9 MZ	319
59f00ff9 MZ	320	u64 live_lrs;
1a89dd91 MZ	321	};
1a89dd91 MZ	322
9d949dce MZ	323	#define LR_EMPTY 0xff
9d949dce MZ	324
495dd859 MZ	325	#define INT_STATUS_EOI (1 << 0)
	326	#define INT_STATUS_UNDERFLOW (1 << 1)
	327
1a89dd91 MZ	328	struct kvm;
1a89dd91 MZ	329	struct kvm_vcpu;
1a89dd91	330
ce01e4e8	331	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34	332	int kvm_vgic_hyp_init(void);
6d3cfbe2	333	int kvm_vgic_map_resources(struct kvm *kvm);
3caa2d8c	334	int kvm_vgic_get_max_vcpus(void);
6c3d63c9	335	void kvm_vgic_early_init(struct kvm *kvm);
59892136	336	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	337	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	338	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	339	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
9d949dce MZ	340	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	341	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	342	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	343	bool level);
773299a5 MZ	344	int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
773299a5 MZ	345	struct irq_phys_map *map, bool level);
6d52f35a	346	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
9d949dce	347	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
6c3d63c9 MZ	348	struct irq_phys_map kvm_vgic_map_phys_irq(struct kvm_vcpu vcpu,
	349	int virt_irq, int irq);
	350	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu vcpu, struct irq_phys_map map);
0e3dfda9	351	bool kvm_vgic_map_is_active(struct kvm_vcpu vcpu, struct irq_phys_map map);
1a89dd91	352
f982cf4e	353	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
1f57be28	354	#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
c52edf5f	355	#define vgic_ready(k) ((k)->arch.vgic.ready)
9d949dce	356
503a6286	357	int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
8f186d52 MZ	358	const struct vgic_ops **ops,
8f186d52 MZ	359	const struct vgic_params **params);
4f64cb65	360	#ifdef CONFIG_KVM_ARM_VGIC_V3
503a6286	361	int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
b2fb1c0d MZ	362	const struct vgic_ops **ops,
	363	const struct vgic_params **params);
	364	#else
503a6286	365	static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
b2fb1c0d MZ	366	const struct vgic_ops **ops,
	367	const struct vgic_params **params)
	368	{
	369	return -ENODEV;
	370	}
	371	#endif
8f186d52	372
1a89dd91	373	#endif