Commit | Line | Data |
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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARM_KVM_VGIC_H | |
20 | #define __ASM_ARM_KVM_VGIC_H | |
21 | ||
b18b5778 CD |
22 | #ifdef CONFIG_KVM_NEW_VGIC |
23 | #include <kvm/vgic/vgic.h> | |
24 | #else | |
25 | ||
b47ef92a MZ |
26 | #include <linux/kernel.h> |
27 | #include <linux/kvm.h> | |
b47ef92a MZ |
28 | #include <linux/irqreturn.h> |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/types.h> | |
6777f77f | 31 | #include <kvm/iodev.h> |
503a6286 | 32 | #include <linux/irqchip/arm-gic-common.h> |
1a89dd91 | 33 | |
5fb66da6 | 34 | #define VGIC_NR_IRQS_LEGACY 256 |
b47ef92a MZ |
35 | #define VGIC_NR_SGIS 16 |
36 | #define VGIC_NR_PPIS 16 | |
37 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
8f186d52 MZ |
38 | |
39 | #define VGIC_V2_MAX_LRS (1 << 6) | |
b2fb1c0d | 40 | #define VGIC_V3_MAX_LRS 16 |
c3c91836 | 41 | #define VGIC_MAX_IRQS 1024 |
3caa2d8c | 42 | #define VGIC_V2_MAX_CPUS 8 |
ef748917 | 43 | #define VGIC_V3_MAX_CPUS 255 |
b47ef92a | 44 | |
5fb66da6 | 45 | #if (VGIC_NR_IRQS_LEGACY & 31) |
b47ef92a MZ |
46 | #error "VGIC_NR_IRQS must be a multiple of 32" |
47 | #endif | |
48 | ||
5fb66da6 | 49 | #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) |
b47ef92a MZ |
50 | #error "VGIC_NR_IRQS must be <= 1024" |
51 | #endif | |
52 | ||
53 | /* | |
54 | * The GIC distributor registers describing interrupts have two parts: | |
55 | * - 32 per-CPU interrupts (SGI + PPI) | |
56 | * - a bunch of shared interrupts (SPI) | |
57 | */ | |
58 | struct vgic_bitmap { | |
c1bfb577 MZ |
59 | /* |
60 | * - One UL per VCPU for private interrupts (assumes UL is at | |
61 | * least 32 bits) | |
62 | * - As many UL as necessary for shared interrupts. | |
63 | * | |
64 | * The private interrupts are accessed via the "private" | |
65 | * field, one UL per vcpu (the state for vcpu n is in | |
66 | * private[n]). The shared interrupts are accessed via the | |
67 | * "shared" pointer (IRQn state is at bit n-32 in the bitmap). | |
68 | */ | |
69 | unsigned long *private; | |
70 | unsigned long *shared; | |
b47ef92a MZ |
71 | }; |
72 | ||
73 | struct vgic_bytemap { | |
c1bfb577 MZ |
74 | /* |
75 | * - 8 u32 per VCPU for private interrupts | |
76 | * - As many u32 as necessary for shared interrupts. | |
77 | * | |
78 | * The private interrupts are accessed via the "private" | |
79 | * field, (the state for vcpu n is in private[n*8] to | |
80 | * private[n*8 + 7]). The shared interrupts are accessed via | |
81 | * the "shared" pointer (IRQn state is at byte (n-32)%4 of the | |
82 | * shared[(n-32)/4] word). | |
83 | */ | |
84 | u32 *private; | |
85 | u32 *shared; | |
b47ef92a MZ |
86 | }; |
87 | ||
8d5c6b06 MZ |
88 | struct kvm_vcpu; |
89 | ||
1a9b1305 MZ |
90 | enum vgic_type { |
91 | VGIC_V2, /* Good ol' GICv2 */ | |
b2fb1c0d | 92 | VGIC_V3, /* New fancy GICv3 */ |
1a9b1305 MZ |
93 | }; |
94 | ||
8d5c6b06 MZ |
95 | #define LR_STATE_PENDING (1 << 0) |
96 | #define LR_STATE_ACTIVE (1 << 1) | |
97 | #define LR_STATE_MASK (3 << 0) | |
98 | #define LR_EOI_INT (1 << 2) | |
32d2d801 | 99 | #define LR_HW (1 << 3) |
8d5c6b06 MZ |
100 | |
101 | struct vgic_lr { | |
32d2d801 MZ |
102 | unsigned irq:10; |
103 | union { | |
104 | unsigned hwirq:10; | |
105 | unsigned source:3; | |
106 | }; | |
107 | unsigned state:4; | |
8d5c6b06 MZ |
108 | }; |
109 | ||
beee38b9 MZ |
110 | struct vgic_vmcr { |
111 | u32 ctlr; | |
112 | u32 abpr; | |
113 | u32 bpr; | |
114 | u32 pmr; | |
115 | }; | |
116 | ||
8d5c6b06 MZ |
117 | struct vgic_ops { |
118 | struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); | |
119 | void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); | |
69bb2c9f | 120 | u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); |
8d6a0313 | 121 | u64 (*get_eisr)(const struct kvm_vcpu *vcpu); |
ae705930 | 122 | void (*clear_eisr)(struct kvm_vcpu *vcpu); |
495dd859 | 123 | u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); |
909d9b50 MZ |
124 | void (*enable_underflow)(struct kvm_vcpu *vcpu); |
125 | void (*disable_underflow)(struct kvm_vcpu *vcpu); | |
beee38b9 MZ |
126 | void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
127 | void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
da8dafd1 | 128 | void (*enable)(struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
129 | }; |
130 | ||
ca85f623 | 131 | struct vgic_params { |
1a9b1305 MZ |
132 | /* vgic type */ |
133 | enum vgic_type type; | |
ca85f623 MZ |
134 | /* Physical address of vgic virtual cpu interface */ |
135 | phys_addr_t vcpu_base; | |
136 | /* Number of list registers */ | |
137 | u32 nr_lr; | |
138 | /* Interrupt number */ | |
139 | unsigned int maint_irq; | |
140 | /* Virtual control interface base address */ | |
141 | void __iomem *vctrl_base; | |
3caa2d8c | 142 | int max_gic_vcpus; |
b5d84ff6 AP |
143 | /* Only needed for the legacy KVM_CREATE_IRQCHIP */ |
144 | bool can_emulate_gicv2; | |
ca85f623 MZ |
145 | }; |
146 | ||
b26e5fda | 147 | struct vgic_vm_ops { |
b26e5fda AP |
148 | bool (*queue_sgi)(struct kvm_vcpu *, int irq); |
149 | void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); | |
150 | int (*init_model)(struct kvm *); | |
151 | int (*map_resources)(struct kvm *, const struct vgic_params *); | |
152 | }; | |
153 | ||
6777f77f AP |
154 | struct vgic_io_device { |
155 | gpa_t addr; | |
156 | int len; | |
157 | const struct vgic_io_range *reg_ranges; | |
158 | struct kvm_vcpu *redist_vcpu; | |
159 | struct kvm_io_device dev; | |
160 | }; | |
161 | ||
6c3d63c9 MZ |
162 | struct irq_phys_map { |
163 | u32 virt_irq; | |
164 | u32 phys_irq; | |
6c3d63c9 MZ |
165 | }; |
166 | ||
167 | struct irq_phys_map_entry { | |
168 | struct list_head entry; | |
169 | struct rcu_head rcu; | |
170 | struct irq_phys_map map; | |
171 | }; | |
172 | ||
1a89dd91 | 173 | struct vgic_dist { |
b47ef92a | 174 | spinlock_t lock; |
f982cf4e | 175 | bool in_kernel; |
01ac5e34 | 176 | bool ready; |
b47ef92a | 177 | |
59892136 AP |
178 | /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ |
179 | u32 vgic_model; | |
180 | ||
c1bfb577 MZ |
181 | int nr_cpus; |
182 | int nr_irqs; | |
183 | ||
b47ef92a MZ |
184 | /* Virtual control interface mapping */ |
185 | void __iomem *vctrl_base; | |
186 | ||
330690cd CD |
187 | /* Distributor and vcpu interface mapping in the guest */ |
188 | phys_addr_t vgic_dist_base; | |
a0675c25 AP |
189 | /* GICv2 and GICv3 use different mapped register blocks */ |
190 | union { | |
191 | phys_addr_t vgic_cpu_base; | |
192 | phys_addr_t vgic_redist_base; | |
193 | }; | |
b47ef92a MZ |
194 | |
195 | /* Distributor enabled */ | |
196 | u32 enabled; | |
197 | ||
198 | /* Interrupt enabled (one bit per IRQ) */ | |
199 | struct vgic_bitmap irq_enabled; | |
200 | ||
faa1b46c CD |
201 | /* Level-triggered interrupt external input is asserted */ |
202 | struct vgic_bitmap irq_level; | |
203 | ||
204 | /* | |
205 | * Interrupt state is pending on the distributor | |
206 | */ | |
227844f5 | 207 | struct vgic_bitmap irq_pending; |
b47ef92a | 208 | |
faa1b46c CD |
209 | /* |
210 | * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered | |
211 | * interrupts. Essentially holds the state of the flip-flop in | |
212 | * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. | |
213 | * Once set, it is only cleared for level-triggered interrupts on | |
214 | * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. | |
215 | */ | |
216 | struct vgic_bitmap irq_soft_pend; | |
217 | ||
dbf20f9d CD |
218 | /* Level-triggered interrupt queued on VCPU interface */ |
219 | struct vgic_bitmap irq_queued; | |
b47ef92a | 220 | |
47a98b15 CD |
221 | /* Interrupt was active when unqueue from VCPU interface */ |
222 | struct vgic_bitmap irq_active; | |
223 | ||
b47ef92a MZ |
224 | /* Interrupt priority. Not used yet. */ |
225 | struct vgic_bytemap irq_priority; | |
226 | ||
227 | /* Level/edge triggered */ | |
228 | struct vgic_bitmap irq_cfg; | |
229 | ||
c1bfb577 MZ |
230 | /* |
231 | * Source CPU per SGI and target CPU: | |
232 | * | |
233 | * Each byte represent a SGI observable on a VCPU, each bit of | |
234 | * this byte indicating if the corresponding VCPU has | |
235 | * generated this interrupt. This is a GICv2 feature only. | |
236 | * | |
237 | * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are | |
238 | * the SGIs observable on VCPUn. | |
239 | */ | |
240 | u8 *irq_sgi_sources; | |
b47ef92a | 241 | |
c1bfb577 MZ |
242 | /* |
243 | * Target CPU for each SPI: | |
244 | * | |
245 | * Array of available SPI, each byte indicating the target | |
246 | * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. | |
247 | */ | |
248 | u8 *irq_spi_cpu; | |
249 | ||
250 | /* | |
251 | * Reverse lookup of irq_spi_cpu for faster compute pending: | |
252 | * | |
253 | * Array of bitmaps, one per VCPU, describing if IRQn is | |
254 | * routed to a particular VCPU. | |
255 | */ | |
256 | struct vgic_bitmap *irq_spi_target; | |
b47ef92a | 257 | |
a0675c25 AP |
258 | /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ |
259 | u32 *irq_spi_mpidr; | |
260 | ||
b47ef92a | 261 | /* Bitmap indicating which CPU has something pending */ |
c1bfb577 | 262 | unsigned long *irq_pending_on_cpu; |
b26e5fda | 263 | |
47a98b15 CD |
264 | /* Bitmap indicating which CPU has active IRQs */ |
265 | unsigned long *irq_active_on_cpu; | |
266 | ||
b26e5fda | 267 | struct vgic_vm_ops vm_ops; |
a9cf86f6 | 268 | struct vgic_io_device dist_iodev; |
fb8f61ab | 269 | struct vgic_io_device *redist_iodevs; |
6c3d63c9 MZ |
270 | |
271 | /* Virtual irq to hwirq mapping */ | |
272 | spinlock_t irq_phys_map_lock; | |
273 | struct list_head irq_phys_map_list; | |
1a89dd91 MZ |
274 | }; |
275 | ||
eede821d MZ |
276 | struct vgic_v2_cpu_if { |
277 | u32 vgic_hcr; | |
278 | u32 vgic_vmcr; | |
279 | u32 vgic_misr; /* Saved only */ | |
2df36a5d CD |
280 | u64 vgic_eisr; /* Saved only */ |
281 | u64 vgic_elrsr; /* Saved only */ | |
eede821d | 282 | u32 vgic_apr; |
8f186d52 | 283 | u32 vgic_lr[VGIC_V2_MAX_LRS]; |
eede821d MZ |
284 | }; |
285 | ||
b2fb1c0d | 286 | struct vgic_v3_cpu_if { |
4f64cb65 | 287 | #ifdef CONFIG_KVM_ARM_VGIC_V3 |
b2fb1c0d MZ |
288 | u32 vgic_hcr; |
289 | u32 vgic_vmcr; | |
2f5fa41a | 290 | u32 vgic_sre; /* Restored only, change ignored */ |
b2fb1c0d MZ |
291 | u32 vgic_misr; /* Saved only */ |
292 | u32 vgic_eisr; /* Saved only */ | |
293 | u32 vgic_elrsr; /* Saved only */ | |
294 | u32 vgic_ap0r[4]; | |
295 | u32 vgic_ap1r[4]; | |
296 | u64 vgic_lr[VGIC_V3_MAX_LRS]; | |
297 | #endif | |
298 | }; | |
299 | ||
1a89dd91 | 300 | struct vgic_cpu { |
47a98b15 | 301 | /* Pending/active/both interrupts on this VCPU */ |
5fdf876d MM |
302 | DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS); |
303 | DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS); | |
304 | DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS); | |
47a98b15 CD |
305 | |
306 | /* Pending/active/both shared interrupts, dynamically sized */ | |
c1bfb577 | 307 | unsigned long *pending_shared; |
47a98b15 CD |
308 | unsigned long *active_shared; |
309 | unsigned long *pend_act_shared; | |
9d949dce | 310 | |
9d949dce | 311 | /* CPU vif control registers for world switch */ |
eede821d MZ |
312 | union { |
313 | struct vgic_v2_cpu_if vgic_v2; | |
b2fb1c0d | 314 | struct vgic_v3_cpu_if vgic_v3; |
eede821d | 315 | }; |
6c3d63c9 MZ |
316 | |
317 | /* Protected by the distributor's irq_phys_map_lock */ | |
318 | struct list_head irq_phys_map_list; | |
59f00ff9 MZ |
319 | |
320 | u64 live_lrs; | |
1a89dd91 MZ |
321 | }; |
322 | ||
9d949dce MZ |
323 | #define LR_EMPTY 0xff |
324 | ||
495dd859 MZ |
325 | #define INT_STATUS_EOI (1 << 0) |
326 | #define INT_STATUS_UNDERFLOW (1 << 1) | |
327 | ||
1a89dd91 MZ |
328 | struct kvm; |
329 | struct kvm_vcpu; | |
1a89dd91 | 330 | |
ce01e4e8 | 331 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
01ac5e34 | 332 | int kvm_vgic_hyp_init(void); |
6d3cfbe2 | 333 | int kvm_vgic_map_resources(struct kvm *kvm); |
3caa2d8c | 334 | int kvm_vgic_get_max_vcpus(void); |
6c3d63c9 | 335 | void kvm_vgic_early_init(struct kvm *kvm); |
59892136 | 336 | int kvm_vgic_create(struct kvm *kvm, u32 type); |
c1bfb577 | 337 | void kvm_vgic_destroy(struct kvm *kvm); |
6c3d63c9 | 338 | void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); |
c1bfb577 | 339 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); |
9d949dce MZ |
340 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); |
341 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
5863c2ce MZ |
342 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
343 | bool level); | |
773299a5 | 344 | int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, |
4f551a3d | 345 | unsigned int virt_irq, bool level); |
6d52f35a | 346 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); |
9d949dce | 347 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
c8eb3f6b | 348 | int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, int virt_irq, int phys_irq); |
63306c28 | 349 | int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); |
e262f419 | 350 | bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); |
1a89dd91 | 351 | |
f982cf4e | 352 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) |
1f57be28 | 353 | #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) |
c52edf5f | 354 | #define vgic_ready(k) ((k)->arch.vgic.ready) |
2defaff4 AP |
355 | #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ |
356 | ((i) < (k)->arch.vgic.nr_irqs)) | |
9d949dce | 357 | |
503a6286 | 358 | int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info, |
8f186d52 MZ |
359 | const struct vgic_ops **ops, |
360 | const struct vgic_params **params); | |
4f64cb65 | 361 | #ifdef CONFIG_KVM_ARM_VGIC_V3 |
503a6286 | 362 | int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, |
b2fb1c0d MZ |
363 | const struct vgic_ops **ops, |
364 | const struct vgic_params **params); | |
365 | #else | |
503a6286 | 366 | static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, |
b2fb1c0d MZ |
367 | const struct vgic_ops **ops, |
368 | const struct vgic_params **params) | |
369 | { | |
370 | return -ENODEV; | |
371 | } | |
372 | #endif | |
8f186d52 | 373 | |
b18b5778 | 374 | #endif /* old VGIC include */ |
1a89dd91 | 375 | #endif |