[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <kvm/iodev.h>

#define VGIC_NR_IRQS_LEGACY	256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_MAX_IRQS		1024
#define VGIC_V2_MAX_CPUS	8

/* Sanity checks... */
#if (KVM_MAX_VCPUS > 255)
#error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
#endif

#if (VGIC_NR_IRQS_LEGACY & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	/*
	 * - One UL per VCPU for private interrupts (assumes UL is at
	 *   least 32 bits)
	 * - As many UL as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, one UL per vcpu (the state for vcpu n is in
	 * private[n]). The shared interrupts are accessed via the
	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	 */
	unsigned long *private;
	unsigned long *shared;
};

struct vgic_bytemap {
	/*
	 * - 8 u32 per VCPU for private interrupts
	 * - As many u32 as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, (the state for vcpu n is in private[n*8] to
	 * private[n*8 + 7]). The shared interrupts are accessed via
	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	 * shared[(n-32)/4] word).
	 */
	u32 *private;
	u32 *shared;
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)
#define LR_HW			(1 << 3)

struct vgic_lr {
	unsigned irq:10;
	union {
		unsigned hwirq:10;
		unsigned source:3;
	};
	unsigned state:4;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	void	(*clear_eisr)(struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
	int		max_gic_vcpus;
	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool		can_emulate_gicv2;
};

struct vgic_vm_ops {
	bool	(*queue_sgi)(struct kvm_vcpu *, int irq);
	void	(*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
	int	(*init_model)(struct kvm *);
	int	(*map_resources)(struct kvm *, const struct vgic_params *);
};

struct vgic_io_device {
	gpa_t addr;
	int len;
	const struct vgic_io_range *reg_ranges;
	struct kvm_vcpu *redist_vcpu;
	struct kvm_io_device dev;
};

struct vgic_dist {
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	int			nr_cpus;
	int			nr_irqs;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	/* GICv2 and GICv3 use different mapped register blocks */
	union {
		phys_addr_t		vgic_cpu_base;
		phys_addr_t		vgic_redist_base;
	};

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Level-triggered interrupt external input is asserted */
	struct vgic_bitmap	irq_level;

	/*
	 * Interrupt state is pending on the distributor
	 */
	struct vgic_bitmap	irq_pending;

	/*
	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	 * interrupts.  Essentially holds the state of the flip-flop in
	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	 * Once set, it is only cleared for level-triggered interrupts on
	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	 */
	struct vgic_bitmap	irq_soft_pend;

	/* Level-triggered interrupt queued on VCPU interface */
	struct vgic_bitmap	irq_queued;

	/* Interrupt was active when unqueue from VCPU interface */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/*
	 * Source CPU per SGI and target CPU:
	 *
	 * Each byte represent a SGI observable on a VCPU, each bit of
	 * this byte indicating if the corresponding VCPU has
	 * generated this interrupt. This is a GICv2 feature only.
	 *
	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
	 * the SGIs observable on VCPUn.
	 */
	u8			*irq_sgi_sources;

	/*
	 * Target CPU for each SPI:
	 *
	 * Array of available SPI, each byte indicating the target
	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	 */
	u8			*irq_spi_cpu;

	/*
	 * Reverse lookup of irq_spi_cpu for faster compute pending:
	 *
	 * Array of bitmaps, one per VCPU, describing if IRQn is
	 * routed to a particular VCPU.
	 */
	struct vgic_bitmap	*irq_spi_target;

	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	u32			*irq_spi_mpidr;

	/* Bitmap indicating which CPU has something pending */
	unsigned long		*irq_pending_on_cpu;

	/* Bitmap indicating which CPU has active IRQs */
	unsigned long		*irq_active_on_cpu;

	struct vgic_vm_ops	vm_ops;
	struct vgic_io_device	dist_iodev;
	struct vgic_io_device	*redist_iodevs;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* per IRQ to LR mapping */
	u8		*vgic_irq_lr_map;

	/* Pending/active/both interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	active_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	pend_act_percpu, VGIC_NR_PRIVATE_IRQS);

	/* Pending/active/both shared interrupts, dynamically sized */
	unsigned long	*pending_shared;
	unsigned long   *active_shared;
	unsigned long   *pend_act_shared;

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_get_max_vcpus(void);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	(!!((k)->arch.vgic.nr_cpus))
#define vgic_ready(k)		((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_ARM_GIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
6777f77f	27	#include <kvm/iodev.h>
1a89dd91	28
5fb66da6	29	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	30	#define VGIC_NR_SGIS 16
	31	#define VGIC_NR_PPIS 16
	32	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
8f186d52 MZ	33
8f186d52 MZ	34	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	35	#define VGIC_V3_MAX_LRS 16
c3c91836	36	#define VGIC_MAX_IRQS 1024
3caa2d8c	37	#define VGIC_V2_MAX_CPUS 8
b47ef92a MZ	38
b47ef92a MZ	39	/* Sanity checks... */
ac3d3735 AP	40	#if (KVM_MAX_VCPUS > 255)
ac3d3735 AP	41	#error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
b47ef92a MZ	42	#endif
b47ef92a MZ	43
5fb66da6	44	#if (VGIC_NR_IRQS_LEGACY & 31)
b47ef92a MZ	45	#error "VGIC_NR_IRQS must be a multiple of 32"
	46	#endif
	47
5fb66da6	48	#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
b47ef92a MZ	49	#error "VGIC_NR_IRQS must be <= 1024"
	50	#endif
	51
	52	/*
	53	* The GIC distributor registers describing interrupts have two parts:
	54	* - 32 per-CPU interrupts (SGI + PPI)
	55	* - a bunch of shared interrupts (SPI)
	56	*/
	57	struct vgic_bitmap {
c1bfb577 MZ	58	/*
	59	* - One UL per VCPU for private interrupts (assumes UL is at
	60	* least 32 bits)
	61	* - As many UL as necessary for shared interrupts.
	62	*
	63	* The private interrupts are accessed via the "private"
	64	* field, one UL per vcpu (the state for vcpu n is in
	65	* private[n]). The shared interrupts are accessed via the
	66	* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	67	*/
	68	unsigned long *private;
	69	unsigned long *shared;
b47ef92a MZ	70	};
	71
	72	struct vgic_bytemap {
c1bfb577 MZ	73	/*
	74	* - 8 u32 per VCPU for private interrupts
	75	* - As many u32 as necessary for shared interrupts.
	76	*
	77	* The private interrupts are accessed via the "private"
	78	* field, (the state for vcpu n is in private[n*8] to
	79	* private[n*8 + 7]). The shared interrupts are accessed via
	80	* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	81	* shared[(n-32)/4] word).
	82	*/
	83	u32 *private;
	84	u32 *shared;
b47ef92a MZ	85	};
b47ef92a MZ	86
8d5c6b06 MZ	87	struct kvm_vcpu;
8d5c6b06 MZ	88
1a9b1305 MZ	89	enum vgic_type {
1a9b1305 MZ	90	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	91	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	92	};
1a9b1305 MZ	93
8d5c6b06 MZ	94	#define LR_STATE_PENDING (1 << 0)
	95	#define LR_STATE_ACTIVE (1 << 1)
	96	#define LR_STATE_MASK (3 << 0)
	97	#define LR_EOI_INT (1 << 2)
32d2d801	98	#define LR_HW (1 << 3)
8d5c6b06 MZ	99
8d5c6b06 MZ	100	struct vgic_lr {
32d2d801 MZ	101	unsigned irq:10;
	102	union {
	103	unsigned hwirq:10;
	104	unsigned source:3;
	105	};
	106	unsigned state:4;
8d5c6b06 MZ	107	};
8d5c6b06 MZ	108
beee38b9 MZ	109	struct vgic_vmcr {
	110	u32 ctlr;
	111	u32 abpr;
	112	u32 bpr;
	113	u32 pmr;
	114	};
	115
8d5c6b06 MZ	116	struct vgic_ops {
	117	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	118	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	119	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	120	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	121	u64 (get_eisr)(const struct kvm_vcpu vcpu);
ae705930	122	void (clear_eisr)(struct kvm_vcpu vcpu);
495dd859	123	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	124	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	125	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	126	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	127	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	128	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	129	};
8d5c6b06 MZ	130
ca85f623	131	struct vgic_params {
1a9b1305 MZ	132	/* vgic type */
1a9b1305 MZ	133	enum vgic_type type;
ca85f623 MZ	134	/* Physical address of vgic virtual cpu interface */
	135	phys_addr_t vcpu_base;
	136	/* Number of list registers */
	137	u32 nr_lr;
	138	/* Interrupt number */
	139	unsigned int maint_irq;
	140	/* Virtual control interface base address */
	141	void __iomem *vctrl_base;
3caa2d8c	142	int max_gic_vcpus;
b5d84ff6 AP	143	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
b5d84ff6 AP	144	bool can_emulate_gicv2;
ca85f623 MZ	145	};
ca85f623 MZ	146
b26e5fda	147	struct vgic_vm_ops {
b26e5fda AP	148	bool (queue_sgi)(struct kvm_vcpu , int irq);
	149	void (add_sgi_source)(struct kvm_vcpu , int irq, int source);
	150	int (init_model)(struct kvm );
	151	int (map_resources)(struct kvm , const struct vgic_params *);
	152	};
	153
6777f77f AP	154	struct vgic_io_device {
	155	gpa_t addr;
	156	int len;
	157	const struct vgic_io_range *reg_ranges;
	158	struct kvm_vcpu *redist_vcpu;
	159	struct kvm_io_device dev;
	160	};
	161
1a89dd91	162	struct vgic_dist {
b47ef92a	163	spinlock_t lock;
f982cf4e	164	bool in_kernel;
01ac5e34	165	bool ready;
b47ef92a	166
59892136 AP	167	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	168	u32 vgic_model;
	169
c1bfb577 MZ	170	int nr_cpus;
	171	int nr_irqs;
	172
b47ef92a MZ	173	/* Virtual control interface mapping */
	174	void __iomem *vctrl_base;
	175
330690cd CD	176	/* Distributor and vcpu interface mapping in the guest */
330690cd CD	177	phys_addr_t vgic_dist_base;
a0675c25 AP	178	/* GICv2 and GICv3 use different mapped register blocks */
	179	union {
	180	phys_addr_t vgic_cpu_base;
	181	phys_addr_t vgic_redist_base;
	182	};
b47ef92a MZ	183
	184	/* Distributor enabled */
	185	u32 enabled;
	186
	187	/* Interrupt enabled (one bit per IRQ) */
	188	struct vgic_bitmap irq_enabled;
	189
faa1b46c CD	190	/* Level-triggered interrupt external input is asserted */
	191	struct vgic_bitmap irq_level;
	192
	193	/*
	194	* Interrupt state is pending on the distributor
	195	*/
227844f5	196	struct vgic_bitmap irq_pending;
b47ef92a	197
faa1b46c CD	198	/*
	199	* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	200	* interrupts. Essentially holds the state of the flip-flop in
	201	* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	202	* Once set, it is only cleared for level-triggered interrupts on
	203	* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	204	*/
	205	struct vgic_bitmap irq_soft_pend;
	206
dbf20f9d CD	207	/* Level-triggered interrupt queued on VCPU interface */
dbf20f9d CD	208	struct vgic_bitmap irq_queued;
b47ef92a	209
47a98b15 CD	210	/* Interrupt was active when unqueue from VCPU interface */
	211	struct vgic_bitmap irq_active;
	212
b47ef92a MZ	213	/* Interrupt priority. Not used yet. */
	214	struct vgic_bytemap irq_priority;
	215
	216	/* Level/edge triggered */
	217	struct vgic_bitmap irq_cfg;
	218
c1bfb577 MZ	219	/*
	220	* Source CPU per SGI and target CPU:
	221	*
	222	* Each byte represent a SGI observable on a VCPU, each bit of
	223	* this byte indicating if the corresponding VCPU has
	224	* generated this interrupt. This is a GICv2 feature only.
	225	*
	226	* For VCPUn (n < 8), irq_sgi_sources[n16] to [n16 + 15] are
	227	* the SGIs observable on VCPUn.
	228	*/
	229	u8 *irq_sgi_sources;
b47ef92a	230
c1bfb577 MZ	231	/*
	232	* Target CPU for each SPI:
	233	*
	234	* Array of available SPI, each byte indicating the target
	235	* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	236	*/
	237	u8 *irq_spi_cpu;
	238
	239	/*
	240	* Reverse lookup of irq_spi_cpu for faster compute pending:
	241	*
	242	* Array of bitmaps, one per VCPU, describing if IRQn is
	243	* routed to a particular VCPU.
	244	*/
	245	struct vgic_bitmap *irq_spi_target;
b47ef92a	246
a0675c25 AP	247	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	248	u32 *irq_spi_mpidr;
	249
b47ef92a	250	/* Bitmap indicating which CPU has something pending */
c1bfb577	251	unsigned long *irq_pending_on_cpu;
b26e5fda	252
47a98b15 CD	253	/* Bitmap indicating which CPU has active IRQs */
	254	unsigned long *irq_active_on_cpu;
	255
b26e5fda	256	struct vgic_vm_ops vm_ops;
a9cf86f6	257	struct vgic_io_device dist_iodev;
fb8f61ab	258	struct vgic_io_device *redist_iodevs;
1a89dd91 MZ	259	};
1a89dd91 MZ	260
eede821d MZ	261	struct vgic_v2_cpu_if {
	262	u32 vgic_hcr;
	263	u32 vgic_vmcr;
	264	u32 vgic_misr; /* Saved only */
2df36a5d CD	265	u64 vgic_eisr; /* Saved only */
2df36a5d CD	266	u64 vgic_elrsr; /* Saved only */
eede821d	267	u32 vgic_apr;
8f186d52	268	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	269	};
eede821d MZ	270
b2fb1c0d MZ	271	struct vgic_v3_cpu_if {
	272	#ifdef CONFIG_ARM_GIC_V3
	273	u32 vgic_hcr;
	274	u32 vgic_vmcr;
2f5fa41a	275	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	276	u32 vgic_misr; /* Saved only */
	277	u32 vgic_eisr; /* Saved only */
	278	u32 vgic_elrsr; /* Saved only */
	279	u32 vgic_ap0r[4];
	280	u32 vgic_ap1r[4];
	281	u64 vgic_lr[VGIC_V3_MAX_LRS];
	282	#endif
	283	};
	284
1a89dd91	285	struct vgic_cpu {
9d949dce	286	/* per IRQ to LR mapping */
c1bfb577	287	u8 *vgic_irq_lr_map;
9d949dce	288
47a98b15	289	/* Pending/active/both interrupts on this VCPU */
9d949dce	290	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
47a98b15 CD	291	DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS);
	292	DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
	293
	294	/* Pending/active/both shared interrupts, dynamically sized */
c1bfb577	295	unsigned long *pending_shared;
47a98b15 CD	296	unsigned long *active_shared;
47a98b15 CD	297	unsigned long *pend_act_shared;
9d949dce MZ	298
9d949dce MZ	299	/* Bitmap of used/free list registers */
8f186d52	300	DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
9d949dce MZ	301
	302	/* Number of list registers on this CPU */
	303	int nr_lr;
	304
	305	/* CPU vif control registers for world switch */
eede821d MZ	306	union {
eede821d MZ	307	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	308	struct vgic_v3_cpu_if vgic_v3;
eede821d	309	};
1a89dd91 MZ	310	};
1a89dd91 MZ	311
9d949dce MZ	312	#define LR_EMPTY 0xff
9d949dce MZ	313
495dd859 MZ	314	#define INT_STATUS_EOI (1 << 0)
	315	#define INT_STATUS_UNDERFLOW (1 << 1)
	316
1a89dd91 MZ	317	struct kvm;
1a89dd91 MZ	318	struct kvm_vcpu;
1a89dd91	319
ce01e4e8	320	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34	321	int kvm_vgic_hyp_init(void);
6d3cfbe2	322	int kvm_vgic_map_resources(struct kvm *kvm);
3caa2d8c	323	int kvm_vgic_get_max_vcpus(void);
59892136	324	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	325	void kvm_vgic_destroy(struct kvm *kvm);
c1bfb577	326	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
9d949dce MZ	327	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	328	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	329	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	330	bool level);
6d52f35a	331	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
9d949dce	332	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
47a98b15	333	int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);
1a89dd91	334
f982cf4e	335	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
1f57be28	336	#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
c52edf5f	337	#define vgic_ready(k) ((k)->arch.vgic.ready)
9d949dce	338
8f186d52 MZ	339	int vgic_v2_probe(struct device_node *vgic_node,
	340	const struct vgic_ops **ops,
	341	const struct vgic_params **params);
b2fb1c0d MZ	342	#ifdef CONFIG_ARM_GIC_V3
	343	int vgic_v3_probe(struct device_node *vgic_node,
	344	const struct vgic_ops **ops,
	345	const struct vgic_params **params);
	346	#else
	347	static inline int vgic_v3_probe(struct device_node *vgic_node,
	348	const struct vgic_ops **ops,
	349	const struct vgic_params **params)
	350	{
	351	return -ENODEV;
	352	}
	353	#endif
8f186d52	354
1a89dd91	355	#endif