[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define VGIC_NR_IRQS		256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS	(VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS		KVM_MAX_VCPUS

#define VGIC_V2_MAX_LRS		(1 << 6)

/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS > 1024)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	union {
		u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	} percpu[VGIC_MAX_CPUS];
	union {
		u32 reg[VGIC_NR_SHARED_IRQS / 32];
		DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	} shared;
};

struct vgic_bytemap {
	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	u32 shared[VGIC_NR_SHARED_IRQS  / 4];
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Interrupt 'pin' level */
	struct vgic_bitmap	irq_state;

	/* Level-triggered interrupt in progress */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/* Source CPU per SGI and target CPU */
	u8			irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];

	/* Target CPU for each IRQ */
	u8			irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	struct vgic_bitmap	irq_spi_target[VGIC_MAX_CPUS];

	/* Bitmap indicating which CPU has something pending */
	unsigned long		irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr[2];	/* Saved only */
	u32		vgic_elrsr[2];	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		vgic_irq_lr_map[VGIC_NR_IRQS];

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(	pending_shared, VGIC_NR_SHARED_IRQS);

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_init(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91	27
9b2d2e0d	28	#define VGIC_NR_IRQS 256
b47ef92a MZ	29	#define VGIC_NR_SGIS 16
	30	#define VGIC_NR_PPIS 16
	31	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	32	#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
	33	#define VGIC_MAX_CPUS KVM_MAX_VCPUS
8f186d52 MZ	34
8f186d52 MZ	35	#define VGIC_V2_MAX_LRS (1 << 6)
b47ef92a MZ	36
	37	/* Sanity checks... */
	38	#if (VGIC_MAX_CPUS > 8)
	39	#error Invalid number of CPU interfaces
	40	#endif
	41
	42	#if (VGIC_NR_IRQS & 31)
	43	#error "VGIC_NR_IRQS must be a multiple of 32"
	44	#endif
	45
	46	#if (VGIC_NR_IRQS > 1024)
	47	#error "VGIC_NR_IRQS must be <= 1024"
	48	#endif
	49
	50	/*
	51	* The GIC distributor registers describing interrupts have two parts:
	52	* - 32 per-CPU interrupts (SGI + PPI)
	53	* - a bunch of shared interrupts (SPI)
	54	*/
	55	struct vgic_bitmap {
	56	union {
	57	u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
	58	DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
	59	} percpu[VGIC_MAX_CPUS];
	60	union {
	61	u32 reg[VGIC_NR_SHARED_IRQS / 32];
	62	DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
	63	} shared;
	64	};
	65
	66	struct vgic_bytemap {
	67	u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
	68	u32 shared[VGIC_NR_SHARED_IRQS / 4];
	69	};
	70
8d5c6b06 MZ	71	struct kvm_vcpu;
8d5c6b06 MZ	72
1a9b1305 MZ	73	enum vgic_type {
	74	VGIC_V2, /* Good ol' GICv2 */
	75	};
	76
8d5c6b06 MZ	77	#define LR_STATE_PENDING (1 << 0)
	78	#define LR_STATE_ACTIVE (1 << 1)
	79	#define LR_STATE_MASK (3 << 0)
	80	#define LR_EOI_INT (1 << 2)
	81
	82	struct vgic_lr {
	83	u16 irq;
	84	u8 source;
	85	u8 state;
	86	};
	87
beee38b9 MZ	88	struct vgic_vmcr {
	89	u32 ctlr;
	90	u32 abpr;
	91	u32 bpr;
	92	u32 pmr;
	93	};
	94
8d5c6b06 MZ	95	struct vgic_ops {
	96	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	97	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	98	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	99	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	100	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	101	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	102	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	103	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	104	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	105	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	106	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	107	};
8d5c6b06 MZ	108
ca85f623	109	struct vgic_params {
1a9b1305 MZ	110	/* vgic type */
1a9b1305 MZ	111	enum vgic_type type;
ca85f623 MZ	112	/* Physical address of vgic virtual cpu interface */
	113	phys_addr_t vcpu_base;
	114	/* Number of list registers */
	115	u32 nr_lr;
	116	/* Interrupt number */
	117	unsigned int maint_irq;
	118	/* Virtual control interface base address */
	119	void __iomem *vctrl_base;
	120	};
	121
1a89dd91	122	struct vgic_dist {
b47ef92a MZ	123	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	124	spinlock_t lock;
f982cf4e	125	bool in_kernel;
01ac5e34	126	bool ready;
b47ef92a MZ	127
	128	/* Virtual control interface mapping */
	129	void __iomem *vctrl_base;
	130
330690cd CD	131	/* Distributor and vcpu interface mapping in the guest */
	132	phys_addr_t vgic_dist_base;
	133	phys_addr_t vgic_cpu_base;
b47ef92a MZ	134
	135	/* Distributor enabled */
	136	u32 enabled;
	137
	138	/* Interrupt enabled (one bit per IRQ) */
	139	struct vgic_bitmap irq_enabled;
	140
	141	/* Interrupt 'pin' level */
	142	struct vgic_bitmap irq_state;
	143
	144	/* Level-triggered interrupt in progress */
	145	struct vgic_bitmap irq_active;
	146
	147	/* Interrupt priority. Not used yet. */
	148	struct vgic_bytemap irq_priority;
	149
	150	/* Level/edge triggered */
	151	struct vgic_bitmap irq_cfg;
	152
	153	/* Source CPU per SGI and target CPU */
	154	u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
	155
	156	/* Target CPU for each IRQ */
	157	u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
	158	struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
	159
	160	/* Bitmap indicating which CPU has something pending */
	161	unsigned long irq_pending_on_cpu;
	162	#endif
1a89dd91 MZ	163	};
1a89dd91 MZ	164
eede821d MZ	165	struct vgic_v2_cpu_if {
	166	u32 vgic_hcr;
	167	u32 vgic_vmcr;
	168	u32 vgic_misr; /* Saved only */
	169	u32 vgic_eisr[2]; /* Saved only */
	170	u32 vgic_elrsr[2]; /* Saved only */
	171	u32 vgic_apr;
8f186d52	172	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	173	};
eede821d MZ	174
1a89dd91	175	struct vgic_cpu {
9d949dce MZ	176	#ifdef CONFIG_KVM_ARM_VGIC
	177	/* per IRQ to LR mapping */
	178	u8 vgic_irq_lr_map[VGIC_NR_IRQS];
	179
	180	/* Pending interrupts on this VCPU */
	181	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
	182	DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
	183
	184	/* Bitmap of used/free list registers */
8f186d52	185	DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
9d949dce MZ	186
	187	/* Number of list registers on this CPU */
	188	int nr_lr;
	189
	190	/* CPU vif control registers for world switch */
eede821d MZ	191	union {
	192	struct vgic_v2_cpu_if vgic_v2;
	193	};
9d949dce	194	#endif
1a89dd91 MZ	195	};
1a89dd91 MZ	196
9d949dce MZ	197	#define LR_EMPTY 0xff
9d949dce MZ	198
495dd859 MZ	199	#define INT_STATUS_EOI (1 << 0)
	200	#define INT_STATUS_UNDERFLOW (1 << 1)
	201
1a89dd91 MZ	202	struct kvm;
	203	struct kvm_vcpu;
	204	struct kvm_run;
	205	struct kvm_exit_mmio;
	206
	207	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	208	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34 MZ	209	int kvm_vgic_hyp_init(void);
	210	int kvm_vgic_init(struct kvm *kvm);
	211	int kvm_vgic_create(struct kvm *kvm);
	212	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
9d949dce MZ	213	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	214	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	215	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	216	bool level);
9d949dce	217	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	218	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	219	struct kvm_exit_mmio *mmio);
	220
f982cf4e	221	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
01ac5e34	222	#define vgic_initialized(k) ((k)->arch.vgic.ready)
9d949dce	223
8f186d52 MZ	224	int vgic_v2_probe(struct device_node *vgic_node,
	225	const struct vgic_ops **ops,
	226	const struct vgic_params **params);
	227
1a89dd91 MZ	228	#else
	229	static inline int kvm_vgic_hyp_init(void)
	230	{
	231	return 0;
	232	}
	233
330690cd CD	234	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	235	{
	236	return 0;
	237	}
	238
6cbde825 MZ	239	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	240	{
	241	return -ENXIO;
	242	}
	243
1a89dd91 MZ	244	static inline int kvm_vgic_init(struct kvm *kvm)
	245	{
	246	return 0;
	247	}
	248
	249	static inline int kvm_vgic_create(struct kvm *kvm)
	250	{
	251	return 0;
	252	}
	253
	254	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	255	{
	256	return 0;
	257	}
	258
	259	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	260	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	261
5863c2ce MZ	262	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	263	unsigned int irq_num, bool level)
	264	{
	265	return 0;
	266	}
	267
1a89dd91 MZ	268	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	269	{
	270	return 0;
	271	}
	272
	273	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	274	struct kvm_exit_mmio *mmio)
	275	{
	276	return false;
	277	}
	278
	279	static inline int irqchip_in_kernel(struct kvm *kvm)
	280	{
	281	return 0;
	282	}
01ac5e34 MZ	283
	284	static inline bool vgic_initialized(struct kvm *kvm)
	285	{
	286	return true;
	287	}
1a89dd91 MZ	288	#endif
	289
	290	#endif