[deliverable/linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define VGIC_NR_IRQS		256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_NR_SHARED_IRQS	(VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
#define VGIC_MAX_CPUS		KVM_MAX_VCPUS

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16

/* Sanity checks... */
#if (VGIC_MAX_CPUS > 8)
#error	Invalid number of CPU interfaces
#endif

#if (VGIC_NR_IRQS & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS > 1024)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	/*
	 * - One UL per VCPU for private interrupts (assumes UL is at
	 *   least 32 bits)
	 * - As many UL as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, one UL per vcpu (the state for vcpu n is in
	 * private[n]). The shared interrupts are accessed via the
	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	 */
	unsigned long *private;
	unsigned long *shared;
};

struct vgic_bytemap {
	/*
	 * - 8 u32 per VCPU for private interrupts
	 * - As many u32 as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, (the state for vcpu n is in private[n*8] to
	 * private[n*8 + 7]). The shared interrupts are accessed via
	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	 * shared[(n-32)/4] word).
	 */
	u32 *private;
	u32 *shared;
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)

struct vgic_lr {
	u16	irq;
	u8	source;
	u8	state;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
};

struct vgic_dist {
#ifdef CONFIG_KVM_ARM_VGIC
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	int			nr_cpus;
	int			nr_irqs;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	phys_addr_t		vgic_cpu_base;

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Level-triggered interrupt external input is asserted */
	struct vgic_bitmap	irq_level;

	/*
	 * Interrupt state is pending on the distributor
	 */
	struct vgic_bitmap	irq_pending;

	/*
	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	 * interrupts.  Essentially holds the state of the flip-flop in
	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	 * Once set, it is only cleared for level-triggered interrupts on
	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	 */
	struct vgic_bitmap	irq_soft_pend;

	/* Level-triggered interrupt queued on VCPU interface */
	struct vgic_bitmap	irq_queued;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/*
	 * Source CPU per SGI and target CPU:
	 *
	 * Each byte represent a SGI observable on a VCPU, each bit of
	 * this byte indicating if the corresponding VCPU has
	 * generated this interrupt. This is a GICv2 feature only.
	 *
	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
	 * the SGIs observable on VCPUn.
	 */
	u8			*irq_sgi_sources;

	/*
	 * Target CPU for each SPI:
	 *
	 * Array of available SPI, each byte indicating the target
	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	 */
	u8			*irq_spi_cpu;

	/*
	 * Reverse lookup of irq_spi_cpu for faster compute pending:
	 *
	 * Array of bitmaps, one per VCPU, describing if IRQn is
	 * routed to a particular VCPU.
	 */
	struct vgic_bitmap	*irq_spi_target;

	/* Bitmap indicating which CPU has something pending */
	unsigned long		*irq_pending_on_cpu;
#endif
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr[2];	/* Saved only */
	u32		vgic_elrsr[2];	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_ARM_GIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
#ifdef CONFIG_KVM_ARM_VGIC
	/* per IRQ to LR mapping */
	u8		*vgic_irq_lr_map;

	/* Pending interrupts on this VCPU */
	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
	unsigned long	*pending_shared;

	/* Bitmap of used/free list registers */
	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};
#endif
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;
struct kvm_run;
struct kvm_exit_mmio;

#ifdef CONFIG_KVM_ARM_VGIC
int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm);
void kvm_vgic_destroy(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
		      struct kvm_exit_mmio *mmio);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_ARM_GIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#else
static inline int kvm_vgic_hyp_init(void)
{
	return 0;
}

static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
{
	return 0;
}

static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
{
	return -ENXIO;
}

static inline int kvm_vgic_init(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_create(struct kvm *kvm)
{
	return 0;
}

static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}

static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
				      unsigned int irq_num, bool level)
{
	return 0;
}

static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
{
	return 0;
}

static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
				    struct kvm_exit_mmio *mmio)
{
	return false;
}

static inline int irqchip_in_kernel(struct kvm *kvm)
{
	return 0;
}

static inline bool vgic_initialized(struct kvm *kvm)
{
	return true;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
1a89dd91	27
9b2d2e0d	28	#define VGIC_NR_IRQS 256
b47ef92a MZ	29	#define VGIC_NR_SGIS 16
	30	#define VGIC_NR_PPIS 16
	31	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
	32	#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
	33	#define VGIC_MAX_CPUS KVM_MAX_VCPUS
8f186d52 MZ	34
8f186d52 MZ	35	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	36	#define VGIC_V3_MAX_LRS 16
b47ef92a MZ	37
	38	/* Sanity checks... */
	39	#if (VGIC_MAX_CPUS > 8)
	40	#error Invalid number of CPU interfaces
	41	#endif
	42
	43	#if (VGIC_NR_IRQS & 31)
	44	#error "VGIC_NR_IRQS must be a multiple of 32"
	45	#endif
	46
	47	#if (VGIC_NR_IRQS > 1024)
	48	#error "VGIC_NR_IRQS must be <= 1024"
	49	#endif
	50
	51	/*
	52	* The GIC distributor registers describing interrupts have two parts:
	53	* - 32 per-CPU interrupts (SGI + PPI)
	54	* - a bunch of shared interrupts (SPI)
	55	*/
	56	struct vgic_bitmap {
c1bfb577 MZ	57	/*
	58	* - One UL per VCPU for private interrupts (assumes UL is at
	59	* least 32 bits)
	60	* - As many UL as necessary for shared interrupts.
	61	*
	62	* The private interrupts are accessed via the "private"
	63	* field, one UL per vcpu (the state for vcpu n is in
	64	* private[n]). The shared interrupts are accessed via the
	65	* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	66	*/
	67	unsigned long *private;
	68	unsigned long *shared;
b47ef92a MZ	69	};
	70
	71	struct vgic_bytemap {
c1bfb577 MZ	72	/*
	73	* - 8 u32 per VCPU for private interrupts
	74	* - As many u32 as necessary for shared interrupts.
	75	*
	76	* The private interrupts are accessed via the "private"
	77	* field, (the state for vcpu n is in private[n*8] to
	78	* private[n*8 + 7]). The shared interrupts are accessed via
	79	* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	80	* shared[(n-32)/4] word).
	81	*/
	82	u32 *private;
	83	u32 *shared;
b47ef92a MZ	84	};
b47ef92a MZ	85
8d5c6b06 MZ	86	struct kvm_vcpu;
8d5c6b06 MZ	87
1a9b1305 MZ	88	enum vgic_type {
1a9b1305 MZ	89	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	90	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	91	};
1a9b1305 MZ	92
8d5c6b06 MZ	93	#define LR_STATE_PENDING (1 << 0)
	94	#define LR_STATE_ACTIVE (1 << 1)
	95	#define LR_STATE_MASK (3 << 0)
	96	#define LR_EOI_INT (1 << 2)
	97
	98	struct vgic_lr {
	99	u16 irq;
	100	u8 source;
	101	u8 state;
	102	};
	103
beee38b9 MZ	104	struct vgic_vmcr {
	105	u32 ctlr;
	106	u32 abpr;
	107	u32 bpr;
	108	u32 pmr;
	109	};
	110
8d5c6b06 MZ	111	struct vgic_ops {
	112	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	113	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	114	void (sync_lr_elrsr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f MZ	115	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	116	u64 (get_eisr)(const struct kvm_vcpu vcpu);
495dd859	117	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	118	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	119	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	120	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	121	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	122	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	123	};
8d5c6b06 MZ	124
ca85f623	125	struct vgic_params {
1a9b1305 MZ	126	/* vgic type */
1a9b1305 MZ	127	enum vgic_type type;
ca85f623 MZ	128	/* Physical address of vgic virtual cpu interface */
	129	phys_addr_t vcpu_base;
	130	/* Number of list registers */
	131	u32 nr_lr;
	132	/* Interrupt number */
	133	unsigned int maint_irq;
	134	/* Virtual control interface base address */
	135	void __iomem *vctrl_base;
	136	};
	137
1a89dd91	138	struct vgic_dist {
b47ef92a MZ	139	#ifdef CONFIG_KVM_ARM_VGIC
b47ef92a MZ	140	spinlock_t lock;
f982cf4e	141	bool in_kernel;
01ac5e34	142	bool ready;
b47ef92a	143
c1bfb577 MZ	144	int nr_cpus;
	145	int nr_irqs;
	146
b47ef92a MZ	147	/* Virtual control interface mapping */
	148	void __iomem *vctrl_base;
	149
330690cd CD	150	/* Distributor and vcpu interface mapping in the guest */
	151	phys_addr_t vgic_dist_base;
	152	phys_addr_t vgic_cpu_base;
b47ef92a MZ	153
	154	/* Distributor enabled */
	155	u32 enabled;
	156
	157	/* Interrupt enabled (one bit per IRQ) */
	158	struct vgic_bitmap irq_enabled;
	159
faa1b46c CD	160	/* Level-triggered interrupt external input is asserted */
	161	struct vgic_bitmap irq_level;
	162
	163	/*
	164	* Interrupt state is pending on the distributor
	165	*/
227844f5	166	struct vgic_bitmap irq_pending;
b47ef92a	167
faa1b46c CD	168	/*
	169	* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	170	* interrupts. Essentially holds the state of the flip-flop in
	171	* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	172	* Once set, it is only cleared for level-triggered interrupts on
	173	* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	174	*/
	175	struct vgic_bitmap irq_soft_pend;
	176
dbf20f9d CD	177	/* Level-triggered interrupt queued on VCPU interface */
dbf20f9d CD	178	struct vgic_bitmap irq_queued;
b47ef92a MZ	179
	180	/* Interrupt priority. Not used yet. */
	181	struct vgic_bytemap irq_priority;
	182
	183	/* Level/edge triggered */
	184	struct vgic_bitmap irq_cfg;
	185
c1bfb577 MZ	186	/*
	187	* Source CPU per SGI and target CPU:
	188	*
	189	* Each byte represent a SGI observable on a VCPU, each bit of
	190	* this byte indicating if the corresponding VCPU has
	191	* generated this interrupt. This is a GICv2 feature only.
	192	*
	193	* For VCPUn (n < 8), irq_sgi_sources[n16] to [n16 + 15] are
	194	* the SGIs observable on VCPUn.
	195	*/
	196	u8 *irq_sgi_sources;
b47ef92a	197
c1bfb577 MZ	198	/*
	199	* Target CPU for each SPI:
	200	*
	201	* Array of available SPI, each byte indicating the target
	202	* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	203	*/
	204	u8 *irq_spi_cpu;
	205
	206	/*
	207	* Reverse lookup of irq_spi_cpu for faster compute pending:
	208	*
	209	* Array of bitmaps, one per VCPU, describing if IRQn is
	210	* routed to a particular VCPU.
	211	*/
	212	struct vgic_bitmap *irq_spi_target;
b47ef92a MZ	213
b47ef92a MZ	214	/* Bitmap indicating which CPU has something pending */
c1bfb577	215	unsigned long *irq_pending_on_cpu;
b47ef92a	216	#endif
1a89dd91 MZ	217	};
1a89dd91 MZ	218
eede821d MZ	219	struct vgic_v2_cpu_if {
	220	u32 vgic_hcr;
	221	u32 vgic_vmcr;
	222	u32 vgic_misr; /* Saved only */
	223	u32 vgic_eisr[2]; /* Saved only */
	224	u32 vgic_elrsr[2]; /* Saved only */
	225	u32 vgic_apr;
8f186d52	226	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	227	};
eede821d MZ	228
b2fb1c0d MZ	229	struct vgic_v3_cpu_if {
	230	#ifdef CONFIG_ARM_GIC_V3
	231	u32 vgic_hcr;
	232	u32 vgic_vmcr;
	233	u32 vgic_misr; /* Saved only */
	234	u32 vgic_eisr; /* Saved only */
	235	u32 vgic_elrsr; /* Saved only */
	236	u32 vgic_ap0r[4];
	237	u32 vgic_ap1r[4];
	238	u64 vgic_lr[VGIC_V3_MAX_LRS];
	239	#endif
	240	};
	241
1a89dd91	242	struct vgic_cpu {
9d949dce MZ	243	#ifdef CONFIG_KVM_ARM_VGIC
9d949dce MZ	244	/* per IRQ to LR mapping */
c1bfb577	245	u8 *vgic_irq_lr_map;
9d949dce MZ	246
	247	/* Pending interrupts on this VCPU */
	248	DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
c1bfb577	249	unsigned long *pending_shared;
9d949dce MZ	250
9d949dce MZ	251	/* Bitmap of used/free list registers */
8f186d52	252	DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
9d949dce MZ	253
	254	/* Number of list registers on this CPU */
	255	int nr_lr;
	256
	257	/* CPU vif control registers for world switch */
eede821d MZ	258	union {
eede821d MZ	259	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	260	struct vgic_v3_cpu_if vgic_v3;
eede821d	261	};
9d949dce	262	#endif
1a89dd91 MZ	263	};
1a89dd91 MZ	264
9d949dce MZ	265	#define LR_EMPTY 0xff
9d949dce MZ	266
495dd859 MZ	267	#define INT_STATUS_EOI (1 << 0)
	268	#define INT_STATUS_UNDERFLOW (1 << 1)
	269
1a89dd91 MZ	270	struct kvm;
	271	struct kvm_vcpu;
	272	struct kvm_run;
	273	struct kvm_exit_mmio;
	274
	275	#ifdef CONFIG_KVM_ARM_VGIC
ce01e4e8	276	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34 MZ	277	int kvm_vgic_hyp_init(void);
	278	int kvm_vgic_init(struct kvm *kvm);
	279	int kvm_vgic_create(struct kvm *kvm);
c1bfb577	280	void kvm_vgic_destroy(struct kvm *kvm);
01ac5e34	281	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
c1bfb577	282	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
9d949dce MZ	283	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	284	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	285	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	286	bool level);
9d949dce	287	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
1a89dd91 MZ	288	bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	289	struct kvm_exit_mmio *mmio);
	290
f982cf4e	291	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
01ac5e34	292	#define vgic_initialized(k) ((k)->arch.vgic.ready)
9d949dce	293
8f186d52 MZ	294	int vgic_v2_probe(struct device_node *vgic_node,
	295	const struct vgic_ops **ops,
	296	const struct vgic_params **params);
b2fb1c0d MZ	297	#ifdef CONFIG_ARM_GIC_V3
	298	int vgic_v3_probe(struct device_node *vgic_node,
	299	const struct vgic_ops **ops,
	300	const struct vgic_params **params);
	301	#else
	302	static inline int vgic_v3_probe(struct device_node *vgic_node,
	303	const struct vgic_ops **ops,
	304	const struct vgic_params **params)
	305	{
	306	return -ENODEV;
	307	}
	308	#endif
8f186d52	309
1a89dd91 MZ	310	#else
	311	static inline int kvm_vgic_hyp_init(void)
	312	{
	313	return 0;
	314	}
	315
330690cd CD	316	static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
	317	{
	318	return 0;
	319	}
	320
6cbde825 MZ	321	static inline int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write)
	322	{
	323	return -ENXIO;
	324	}
	325
1a89dd91 MZ	326	static inline int kvm_vgic_init(struct kvm *kvm)
	327	{
	328	return 0;
	329	}
	330
	331	static inline int kvm_vgic_create(struct kvm *kvm)
	332	{
	333	return 0;
	334	}
	335
	336	static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
	337	{
	338	return 0;
	339	}
	340
	341	static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
	342	static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
	343
5863c2ce MZ	344	static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
	345	unsigned int irq_num, bool level)
	346	{
	347	return 0;
	348	}
	349
1a89dd91 MZ	350	static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
	351	{
	352	return 0;
	353	}
	354
	355	static inline bool vgic_handle_mmio(struct kvm_vcpu vcpu, struct kvm_run run,
	356	struct kvm_exit_mmio *mmio)
	357	{
	358	return false;
	359	}
	360
	361	static inline int irqchip_in_kernel(struct kvm *kvm)
	362	{
	363	return 0;
	364	}
01ac5e34 MZ	365
	366	static inline bool vgic_initialized(struct kvm *kvm)
	367	{
	368	return true;
	369	}
1a89dd91 MZ	370	#endif
	371
	372	#endif