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e8689e63 LW |
1 | /* |
2 | * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver | |
3 | * | |
4 | * Copyright (C) 2005 ARM Ltd | |
5 | * Copyright (C) 2010 ST-Ericsson SA | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * pl08x information required by platform code | |
12 | * | |
13 | * Please credit ARM.com | |
14 | * Documentation: ARM DDI 0196D | |
e8689e63 LW |
15 | */ |
16 | ||
17 | #ifndef AMBA_PL08X_H | |
18 | #define AMBA_PL08X_H | |
19 | ||
20 | /* We need sizes of structs from this header */ | |
21 | #include <linux/dmaengine.h> | |
22 | #include <linux/interrupt.h> | |
23 | ||
7cb72ad9 | 24 | struct pl08x_driver_data; |
b23f204c RK |
25 | struct pl08x_phy_chan; |
26 | struct pl08x_txd; | |
7cb72ad9 | 27 | |
30749cb4 RKAL |
28 | /* Bitmasks for selecting AHB ports for DMA transfers */ |
29 | enum { | |
30 | PL08X_AHB1 = (1 << 0), | |
31 | PL08X_AHB2 = (1 << 1) | |
32 | }; | |
33 | ||
e8689e63 LW |
34 | /** |
35 | * struct pl08x_channel_data - data structure to pass info between | |
36 | * platform and PL08x driver regarding channel configuration | |
37 | * @bus_id: name of this device channel, not just a device name since | |
38 | * devices may have more than one channel e.g. "foo_tx" | |
39 | * @min_signal: the minimum DMA signal number to be muxed in for this | |
40 | * channel (for platforms supporting muxed signals). If you have | |
41 | * static assignments, make sure this is set to the assigned signal | |
42 | * number, PL08x have 16 possible signals in number 0 thru 15 so | |
43 | * when these are not enough they often get muxed (in hardware) | |
44 | * disabling simultaneous use of the same channel for two devices. | |
45 | * @max_signal: the maximum DMA signal number to be muxed in for | |
46 | * the channel. Set to the same as min_signal for | |
47 | * devices with static assignments | |
48 | * @muxval: a number usually used to poke into some mux regiser to | |
49 | * mux in the signal to this channel | |
dc8d5f8d RK |
50 | * @cctl_memcpy: options for the channel control register for memcpy |
51 | * *** not used for slave channels *** | |
e8689e63 LW |
52 | * @addr: source/target address in physical memory for this DMA channel, |
53 | * can be the address of a FIFO register for burst requests for example. | |
54 | * This can be left undefined if the PrimeCell API is used for configuring | |
55 | * this. | |
94ae8522 RKAL |
56 | * @single: the device connected to this channel will request single DMA |
57 | * transfers, not bursts. (Bursts are default.) | |
30749cb4 RKAL |
58 | * @periph_buses: the device connected to this channel is accessible via |
59 | * these buses (use PL08X_AHB1 | PL08X_AHB2). | |
e8689e63 LW |
60 | */ |
61 | struct pl08x_channel_data { | |
550ec36f | 62 | const char *bus_id; |
e8689e63 LW |
63 | int min_signal; |
64 | int max_signal; | |
65 | u32 muxval; | |
dc8d5f8d | 66 | u32 cctl_memcpy; |
e8689e63 | 67 | dma_addr_t addr; |
e8689e63 | 68 | bool single; |
30749cb4 | 69 | u8 periph_buses; |
e8689e63 LW |
70 | }; |
71 | ||
e8689e63 | 72 | /** |
94ae8522 RKAL |
73 | * struct pl08x_platform_data - the platform configuration for the PL08x |
74 | * PrimeCells. | |
e8689e63 LW |
75 | * @slave_channels: the channels defined for the different devices on the |
76 | * platform, all inclusive, including multiplexed channels. The available | |
94ae8522 RKAL |
77 | * physical channels will be multiplexed around these signals as they are |
78 | * requested, just enumerate all possible channels. | |
d7cabeed | 79 | * @get_xfer_signal: request a physical signal to be used for a DMA transfer |
94ae8522 RKAL |
80 | * immediately: if there is some multiplexing or similar blocking the use |
81 | * of the channel the transfer can be denied by returning less than zero, | |
82 | * else it returns the allocated signal number | |
d7cabeed | 83 | * @put_xfer_signal: indicate to the platform that this physical signal is not |
e8689e63 | 84 | * running any DMA transfer and multiplexing can be recycled |
30749cb4 RKAL |
85 | * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2 |
86 | * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2 | |
e8689e63 LW |
87 | */ |
88 | struct pl08x_platform_data { | |
f9cd4761 | 89 | struct pl08x_channel_data *slave_channels; |
e8689e63 LW |
90 | unsigned int num_slave_channels; |
91 | struct pl08x_channel_data memcpy_channel; | |
d7cabeed MB |
92 | int (*get_xfer_signal)(const struct pl08x_channel_data *); |
93 | void (*put_xfer_signal)(const struct pl08x_channel_data *, int); | |
30749cb4 RKAL |
94 | u8 lli_buses; |
95 | u8 mem_buses; | |
e8689e63 LW |
96 | }; |
97 | ||
98 | #ifdef CONFIG_AMBA_PL08X | |
99 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id); | |
100 | #else | |
101 | static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
102 | { | |
103 | return false; | |
104 | } | |
105 | #endif | |
106 | ||
107 | #endif /* AMBA_PL08X_H */ |