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1e6c9c28 | 1 | /* |
fa3218d8 | 2 | * include/linux/atmel_serial.h |
1e6c9c28 AV |
3 | * |
4 | * Copyright (C) 2005 Ivan Kokshaysky | |
5 | * Copyright (C) SAN People | |
6 | * | |
7 | * USART registers. | |
8 | * Based on AT91RM9200 datasheet revision E. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | */ | |
15 | ||
7192f92c HS |
16 | #ifndef ATMEL_SERIAL_H |
17 | #define ATMEL_SERIAL_H | |
1e6c9c28 | 18 | |
7192f92c HS |
19 | #define ATMEL_US_CR 0x00 /* Control Register */ |
20 | #define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */ | |
21 | #define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */ | |
22 | #define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */ | |
23 | #define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */ | |
24 | #define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */ | |
25 | #define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */ | |
26 | #define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */ | |
27 | #define ATMEL_US_STTBRK (1 << 9) /* Start Break */ | |
28 | #define ATMEL_US_STPBRK (1 << 10) /* Stop Break */ | |
29 | #define ATMEL_US_STTTO (1 << 11) /* Start Time-out */ | |
30 | #define ATMEL_US_SENDA (1 << 12) /* Send Address */ | |
31 | #define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ | |
32 | #define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ | |
33 | #define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ | |
d7075726 AV |
34 | #define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ |
35 | #define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ | |
7192f92c HS |
36 | #define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ |
37 | #define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ | |
1e6c9c28 | 38 | |
7192f92c HS |
39 | #define ATMEL_US_MR 0x04 /* Mode Register */ |
40 | #define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */ | |
41 | #define ATMEL_US_USMODE_NORMAL 0 | |
42 | #define ATMEL_US_USMODE_RS485 1 | |
43 | #define ATMEL_US_USMODE_HWHS 2 | |
44 | #define ATMEL_US_USMODE_MODEM 3 | |
45 | #define ATMEL_US_USMODE_ISO7816_T0 4 | |
46 | #define ATMEL_US_USMODE_ISO7816_T1 6 | |
47 | #define ATMEL_US_USMODE_IRDA 8 | |
48 | #define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */ | |
03abeac0 AV |
49 | #define ATMEL_US_USCLKS_MCK (0 << 4) |
50 | #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) | |
51 | #define ATMEL_US_USCLKS_SCK (3 << 4) | |
7192f92c HS |
52 | #define ATMEL_US_CHRL (3 << 6) /* Character Length */ |
53 | #define ATMEL_US_CHRL_5 (0 << 6) | |
54 | #define ATMEL_US_CHRL_6 (1 << 6) | |
55 | #define ATMEL_US_CHRL_7 (2 << 6) | |
56 | #define ATMEL_US_CHRL_8 (3 << 6) | |
57 | #define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */ | |
58 | #define ATMEL_US_PAR (7 << 9) /* Parity Type */ | |
59 | #define ATMEL_US_PAR_EVEN (0 << 9) | |
60 | #define ATMEL_US_PAR_ODD (1 << 9) | |
61 | #define ATMEL_US_PAR_SPACE (2 << 9) | |
62 | #define ATMEL_US_PAR_MARK (3 << 9) | |
63 | #define ATMEL_US_PAR_NONE (4 << 9) | |
64 | #define ATMEL_US_PAR_MULTI_DROP (6 << 9) | |
65 | #define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */ | |
66 | #define ATMEL_US_NBSTOP_1 (0 << 12) | |
67 | #define ATMEL_US_NBSTOP_1_5 (1 << 12) | |
68 | #define ATMEL_US_NBSTOP_2 (2 << 12) | |
69 | #define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */ | |
70 | #define ATMEL_US_CHMODE_NORMAL (0 << 14) | |
71 | #define ATMEL_US_CHMODE_ECHO (1 << 14) | |
72 | #define ATMEL_US_CHMODE_LOC_LOOP (2 << 14) | |
73 | #define ATMEL_US_CHMODE_REM_LOOP (3 << 14) | |
74 | #define ATMEL_US_MSBF (1 << 16) /* Bit Order */ | |
75 | #define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */ | |
76 | #define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */ | |
77 | #define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */ | |
78 | #define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ | |
79 | #define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */ | |
80 | #define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */ | |
81 | #define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ | |
1e6c9c28 | 82 | |
7192f92c HS |
83 | #define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ |
84 | #define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */ | |
85 | #define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */ | |
86 | #define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */ | |
87 | #define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */ | |
88 | #define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ | |
89 | #define ATMEL_US_OVRE (1 << 5) /* Overrun Error */ | |
90 | #define ATMEL_US_FRAME (1 << 6) /* Framing Error */ | |
91 | #define ATMEL_US_PARE (1 << 7) /* Parity Error */ | |
92 | #define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */ | |
93 | #define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */ | |
94 | #define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ | |
95 | #define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ | |
96 | #define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ | |
97 | #define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ | |
d7075726 AV |
98 | #define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ |
99 | #define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ | |
100 | #define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ | |
7192f92c HS |
101 | #define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ |
102 | #define ATMEL_US_RI (1 << 20) /* RI */ | |
103 | #define ATMEL_US_DSR (1 << 21) /* DSR */ | |
104 | #define ATMEL_US_DCD (1 << 22) /* DCD */ | |
105 | #define ATMEL_US_CTS (1 << 23) /* CTS */ | |
1e6c9c28 | 106 | |
7192f92c HS |
107 | #define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */ |
108 | #define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */ | |
109 | #define ATMEL_US_CSR 0x14 /* Channel Status Register */ | |
110 | #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ | |
111 | #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ | |
a14d5273 | 112 | #define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ |
1e6c9c28 | 113 | |
7192f92c HS |
114 | #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ |
115 | #define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ | |
1e6c9c28 | 116 | |
7192f92c HS |
117 | #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */ |
118 | #define ATMEL_US_TO (0xffff << 0) /* Time-out Value */ | |
1e6c9c28 | 119 | |
7192f92c HS |
120 | #define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */ |
121 | #define ATMEL_US_TG (0xff << 0) /* Timeguard Value */ | |
1e6c9c28 | 122 | |
7192f92c HS |
123 | #define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */ |
124 | #define ATMEL_US_NER 0x44 /* Number of Errors Register */ | |
125 | #define ATMEL_US_IF 0x4c /* IrDA Filter Register */ | |
1e6c9c28 | 126 | |
055560b0 | 127 | #define ATMEL_US_NAME 0xf0 /* Ip Name */ |
731d9cae | 128 | #define ATMEL_US_VERSION 0xfc /* Ip Version */ |
055560b0 | 129 | |
1e6c9c28 | 130 | #endif |