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8369ae33 RM |
1 | #ifndef LINUX_BCMA_REGS_H_ |
2 | #define LINUX_BCMA_REGS_H_ | |
3 | ||
bb932ad9 RM |
4 | /* Some single registers are shared between many cores */ |
5 | /* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */ | |
6 | #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */ | |
7 | #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */ | |
8 | #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */ | |
9 | #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */ | |
10 | #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ | |
11 | #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ | |
12 | #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ | |
13 | #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */ | |
3213e1a5 | 14 | #define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8 |
bb932ad9 RM |
15 | #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
16 | #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */ | |
17 | #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */ | |
18 | #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */ | |
19 | #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */ | |
3213e1a5 | 20 | #define BCMA_CLKCTLST_EXTRESST_SHIFT 24 |
bb932ad9 RM |
21 | /* Is there any BCM4328 on BCMA bus? */ |
22 | #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ | |
23 | #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ | |
24 | ||
8369ae33 | 25 | /* Agent registers (common for every core) */ |
2b5e3322 | 26 | #define BCMA_IOCTL 0x0408 /* IO control */ |
8369ae33 RM |
27 | #define BCMA_IOCTL_CLK 0x0001 |
28 | #define BCMA_IOCTL_FGC 0x0002 | |
29 | #define BCMA_IOCTL_CORE_BITS 0x3FFC | |
30 | #define BCMA_IOCTL_PME_EN 0x4000 | |
31 | #define BCMA_IOCTL_BIST_EN 0x8000 | |
2b5e3322 RM |
32 | #define BCMA_IOST 0x0500 /* IO status */ |
33 | #define BCMA_IOST_CORE_BITS 0x0FFF | |
34 | #define BCMA_IOST_DMA64 0x1000 | |
35 | #define BCMA_IOST_GATED_CLK 0x2000 | |
36 | #define BCMA_IOST_BIST_ERROR 0x4000 | |
37 | #define BCMA_IOST_BIST_DONE 0x8000 | |
8369ae33 RM |
38 | #define BCMA_RESET_CTL 0x0800 |
39 | #define BCMA_RESET_CTL_RESET 0x0001 | |
1640f28f | 40 | #define BCMA_RESET_ST 0x0804 |
8369ae33 RM |
41 | |
42 | /* BCMA PCI config space registers. */ | |
43 | #define BCMA_PCI_PMCSR 0x44 | |
44 | #define BCMA_PCI_PE 0x100 | |
45 | #define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */ | |
46 | #define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */ | |
47 | #define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */ | |
48 | #define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */ | |
49 | #define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */ | |
50 | #define BCMA_PCI_IRQS 0x90 /* PCI interrupts */ | |
51 | #define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */ | |
52 | #define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */ | |
53 | #define BCMA_PCI_BAR0_WIN2 0xAC | |
54 | #define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */ | |
55 | #define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */ | |
56 | #define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */ | |
57 | #define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ | |
58 | #define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ | |
59 | #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ | |
60 | #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ | |
61 | ||
49dc9577 HM |
62 | /* SiliconBackplane Address Map. |
63 | * All regions may not exist on all chips. | |
64 | */ | |
65 | #define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */ | |
66 | #define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ | |
67 | #define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024) | |
68 | #define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ | |
69 | #define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ | |
70 | #define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */ | |
71 | ||
72 | ||
73 | #define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ | |
74 | #define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */ | |
75 | #define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ | |
76 | #define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 | |
77 | * (2 ZettaBytes), low 32 bits | |
78 | */ | |
79 | #define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 | |
80 | * (2 ZettaBytes), high 32 bits | |
81 | */ | |
82 | ||
83 | #define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */ | |
84 | #define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */ | |
85 | #define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2 | |
86 | * (2 ZettaBytes), high 32 bits | |
87 | */ | |
88 | ||
cc787081 HM |
89 | #define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ |
90 | #define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ | |
91 | #define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ | |
92 | #define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ | |
d57ef3a6 | 93 | |
8369ae33 | 94 | #endif /* LINUX_BCMA_REGS_H_ */ |