projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 755ccb9d FF |
1 | #ifndef _LINUX_BRCMPHY_H |
| 2 | #define _LINUX_BRCMPHY_H | |
| 3 | ||
| 4f822c62 FF |
4 | #include <linux/phy.h> |
| 5 | ||
| 8bc84b79 FF |
6 | /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used |
| 7 | * to configure the switch internal registers via MDIO accesses. | |
| 8 | */ | |
| 9 | #define BRCM_PSEUDO_PHY_ADDR 30 | |
| 10 | ||
| 6a443a0f MC |
11 | #define PHY_ID_BCM50610 0x0143bd60 |
| 12 | #define PHY_ID_BCM50610M 0x0143bd70 | |
| 7a938f80 | 13 | #define PHY_ID_BCM5241 0x0143bc30 |
| 6a443a0f | 14 | #define PHY_ID_BCMAC131 0x0143bc70 |
| fcb26ec5 DB |
15 | #define PHY_ID_BCM5481 0x0143bca0 |
| 16 | #define PHY_ID_BCM5482 0x0143bcb0 | |
| 17 | #define PHY_ID_BCM5411 0x00206070 | |
| 18 | #define PHY_ID_BCM5421 0x002060e0 | |
| 19 | #define PHY_ID_BCM5464 0x002060b0 | |
| 20 | #define PHY_ID_BCM5461 0x002060c0 | |
| 3bca4cf6 | 21 | #define PHY_ID_BCM54616S 0x03625d10 |
| 6a443a0f MC |
22 | #define PHY_ID_BCM57780 0x03625d90 |
| 23 | ||
| 430ad68f FF |
24 | #define PHY_ID_BCM7250 0xae025280 |
| 25 | #define PHY_ID_BCM7364 0xae025260 | |
| b560a58c | 26 | #define PHY_ID_BCM7366 0x600d8490 |
| cc4a84c3 | 27 | #define PHY_ID_BCM7425 0x600d86b0 |
| d068b02c | 28 | #define PHY_ID_BCM7429 0x600d8730 |
| 9458ceab | 29 | #define PHY_ID_BCM7435 0x600d8750 |
| b560a58c | 30 | #define PHY_ID_BCM7439 0x600d8480 |
| 59e33c2b | 31 | #define PHY_ID_BCM7439_2 0xae025080 |
| b560a58c | 32 | #define PHY_ID_BCM7445 0x600d8510 |
| b560a58c | 33 | |
| 8e185d69 AP |
34 | #define PHY_ID_BCM_CYGNUS 0xae025200 |
| 35 | ||
| 6a443a0f MC |
36 | #define PHY_BCM_OUI_MASK 0xfffffc00 |
| 37 | #define PHY_BCM_OUI_1 0x00206000 | |
| 38 | #define PHY_BCM_OUI_2 0x0143bc00 | |
| 39 | #define PHY_BCM_OUI_3 0x03625c00 | |
| 97fdaab4 | 40 | #define PHY_BCM_OUI_4 0x600d8400 |
| b560a58c | 41 | #define PHY_BCM_OUI_5 0x03625e00 |
| 11bf2bbd | 42 | #define PHY_BCM_OUI_6 0xae025000 |
| 6a443a0f | 43 | |
| 8649f13d MC |
44 | #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 |
| 45 | #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002 | |
| 46 | #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010 | |
| 47 | #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020 | |
| 48 | #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100 | |
| 49 | #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200 | |
| 32e5a8d6 | 50 | #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400 |
| 8649f13d MC |
51 | #define PHY_BRCM_STD_IBND_DISABLE 0x00000800 |
| 52 | #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000 | |
| 53 | #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 | |
| 63a14ce4 | 54 | #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 |
| 52fae083 | 55 | #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 |
| b560a58c | 56 | /* Broadcom BCM7xxx specific workarounds */ |
| bb7d9349 FF |
57 | #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) |
| 58 | #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) | |
| 8649f13d | 59 | #define PHY_BCM_FLAGS_VALID 0x80000000 |
| 755ccb9d | 60 | |
| 439d39a9 FF |
61 | /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ |
| 62 | #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ | |
| 63 | #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ | |
| 64 | #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ | |
| 65 | ||
| 66 | #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ | |
| 67 | #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ | |
| 68 | ||
| 69 | #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ | |
| 70 | #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ | |
| 71 | #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ | |
| 72 | #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ | |
| 73 | ||
| 74 | #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ | |
| 75 | #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ | |
| 76 | #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ | |
| 77 | #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ | |
| 78 | #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ | |
| 79 | #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ | |
| 80 | #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ | |
| 81 | #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ | |
| 82 | #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ | |
| 83 | #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ | |
| 84 | #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ | |
| 85 | #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ | |
| 86 | #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ | |
| 87 | #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ | |
| 88 | #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ | |
| 89 | #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ | |
| 90 | #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ | |
| 91 | #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ | |
| 92 | ||
| 93 | #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ | |
| 94 | #define MII_BCM54XX_SHD_WRITE 0x8000 | |
| 95 | #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) | |
| 96 | #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) | |
| 97 | ||
| 98 | /* | |
| 99 | * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) | |
| 100 | */ | |
| 101 | #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 | |
| 102 | #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 | |
| 103 | #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 | |
| 104 | ||
| 105 | #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 | |
| 106 | #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 | |
| 107 | #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000 | |
| 108 | #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007 | |
| 109 | ||
| 110 | #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 | |
| 111 | ||
| 3af20efc FF |
112 | /* |
| 113 | * Broadcom LED source encodings. These are used in BCM5461, BCM5481, | |
| 114 | * BCM5482, and possibly some others. | |
| 115 | */ | |
| 116 | #define BCM_LED_SRC_LINKSPD1 0x0 | |
| 117 | #define BCM_LED_SRC_LINKSPD2 0x1 | |
| 118 | #define BCM_LED_SRC_XMITLED 0x2 | |
| 119 | #define BCM_LED_SRC_ACTIVITYLED 0x3 | |
| 120 | #define BCM_LED_SRC_FDXLED 0x4 | |
| 121 | #define BCM_LED_SRC_SLAVE 0x5 | |
| 122 | #define BCM_LED_SRC_INTR 0x6 | |
| 123 | #define BCM_LED_SRC_QUALITY 0x7 | |
| 124 | #define BCM_LED_SRC_RCVLED 0x8 | |
| 125 | #define BCM_LED_SRC_MULTICOLOR1 0xa | |
| 126 | #define BCM_LED_SRC_OPENSHORT 0xb | |
| 127 | #define BCM_LED_SRC_OFF 0xe /* Tied high */ | |
| 128 | #define BCM_LED_SRC_ON 0xf /* Tied low */ | |
| 129 | ||
| 130 | ||
| 131 | /* | |
| 132 | * BCM5482: Shadow registers | |
| 133 | * Shadow values go into bits [14:10] of register 0x1c to select a shadow | |
| 134 | * register to access. | |
| 135 | */ | |
| 136 | /* 00101: Spare Control Register 3 */ | |
| 137 | #define BCM54XX_SHD_SCR3 0x05 | |
| 138 | #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 | |
| 139 | #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 | |
| 140 | #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 | |
| 141 | ||
| 142 | /* 01010: Auto Power-Down */ | |
| 143 | #define BCM54XX_SHD_APD 0x0a | |
| a1cba561 | 144 | #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ |
| 3af20efc | 145 | #define BCM54XX_SHD_APD_EN 0x0020 |
| a1cba561 AP |
146 | #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ |
| 147 | #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ | |
| 3af20efc FF |
148 | |
| 149 | #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ | |
| 150 | /* LED3 / ~LINKSPD[2] selector */ | |
| 151 | #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) | |
| 152 | /* LED1 / ~LINKSPD[1] selector */ | |
| 153 | #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) | |
| 154 | #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ | |
| 155 | #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ | |
| 156 | #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ | |
| 157 | #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ | |
| 158 | #define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */ | |
| 159 | #define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */ | |
| 160 | ||
| 161 | ||
| 162 | /* | |
| 163 | * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) | |
| 164 | */ | |
| 165 | #define MII_BCM54XX_EXP_AADJ1CH0 0x001f | |
| 166 | #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 | |
| 167 | #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 | |
| 168 | #define MII_BCM54XX_EXP_AADJ1CH3 0x601f | |
| 169 | #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 | |
| 170 | #define MII_BCM54XX_EXP_EXP08 0x0F08 | |
| 171 | #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 | |
| 172 | #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 | |
| 173 | #define MII_BCM54XX_EXP_EXP75 0x0f75 | |
| 174 | #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c | |
| 175 | #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 | |
| 176 | #define MII_BCM54XX_EXP_EXP96 0x0f96 | |
| 177 | #define MII_BCM54XX_EXP_EXP96_MYST 0x0010 | |
| 178 | #define MII_BCM54XX_EXP_EXP97 0x0f97 | |
| 179 | #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c | |
| 180 | ||
| 181 | /* | |
| 182 | * BCM5482: Secondary SerDes registers | |
| 183 | */ | |
| 184 | #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ | |
| 185 | #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ | |
| 186 | #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ | |
| 187 | #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ | |
| 188 | #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ | |
| 189 | ||
| 190 | ||
| 191 | /*****************************************************************************/ | |
| 192 | /* Fast Ethernet Transceiver definitions. */ | |
| 193 | /*****************************************************************************/ | |
| 194 | ||
| 195 | #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ | |
| 196 | #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ | |
| 197 | #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ | |
| 198 | #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ | |
| 199 | #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ | |
| 200 | #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ | |
| 201 | ||
| 202 | #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ | |
| 203 | #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ | |
| 204 | ||
| 205 | ||
| 206 | /*** Shadow register definitions ***/ | |
| 207 | ||
| 208 | #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ | |
| 209 | #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ | |
| 210 | ||
| 211 | #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ | |
| 212 | #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 | |
| 213 | #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 | |
| 214 | ||
| 215 | #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ | |
| 216 | #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ | |
| 217 | ||
| b8f9a029 FF |
218 | #define BRCM_CL45VEN_EEE_CONTROL 0x803d |
| 219 | #define LPI_FEATURE_EN 0x8000 | |
| 220 | #define LPI_FEATURE_EN_DIG1000X 0x4000 | |
| 70531479 | 221 | |
| 8e185d69 AP |
222 | /* Core register definitions*/ |
| 223 | #define MII_BRCM_CORE_BASE1E 0x1E | |
| 224 | #define MII_BRCM_CORE_EXPB0 0xB0 | |
| 225 | #define MII_BRCM_CORE_EXPB1 0xB1 | |
| 226 | ||
| 755ccb9d | 227 | #endif /* _LINUX_BRCMPHY_H */ |