[deliverable/linux.git] / include / linux / clk-private.h

/*
 *  linux/include/linux/clk-private.h
 *
 *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
 *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_CLK_PRIVATE_H
#define __LINUX_CLK_PRIVATE_H

#include <linux/clk-provider.h>
#include <linux/kref.h>
#include <linux/list.h>

/*
 * WARNING: Do not include clk-private.h from any file that implements struct
 * clk_ops.  Doing so is a layering violation!
 *
 * This header exists only to allow for statically initialized clock data.  Any
 * static clock data must be defined in a separate file from the logic that
 * implements the clock operations for that same data.
 */

#ifdef CONFIG_COMMON_CLK

struct module;

struct clk {
	const char		*name;
	const struct clk_ops	*ops;
	struct clk_hw		*hw;
	struct module		*owner;
	struct clk		*parent;
	const char		**parent_names;
	struct clk		**parents;
	u8			num_parents;
	u8			new_parent_index;
	unsigned long		rate;
	unsigned long		new_rate;
	struct clk		*new_parent;
	struct clk		*new_child;
	unsigned long		flags;
	unsigned int		enable_count;
	unsigned int		prepare_count;
	unsigned long		accuracy;
	int			phase;
	struct hlist_head	children;
	struct hlist_node	child_node;
	struct hlist_node	debug_node;
	unsigned int		notifier_count;
#ifdef CONFIG_DEBUG_FS
	struct dentry		*dentry;
#endif
	struct kref		ref;
};

/*
 * DOC: Basic clock implementations common to many platforms
 *
 * Each basic clock hardware type is comprised of a structure describing the
 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 * unique flags for that hardware type, a registration function and an
 * alternative macro for static initialization
 */

#define DEFINE_CLK(_name, _ops, _flags, _parent_names,		\
		_parents)					\
	static struct clk _name = {				\
		.name = #_name,					\
		.ops = &_ops,					\
		.hw = &_name##_hw.hw,				\
		.parent_names = _parent_names,			\
		.num_parents = ARRAY_SIZE(_parent_names),	\
		.parents = _parents,				\
		.flags = _flags | CLK_IS_BASIC,			\
	}

#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
				_fixed_rate_flags)		\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {};		\
	static struct clk_fixed_rate _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.fixed_rate = _rate,				\
		.flags = _fixed_rate_flags,			\
	};							\
	DEFINE_CLK(_name, clk_fixed_rate_ops, _flags,		\
			_name##_parent_names, NULL);

#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _bit_idx,		\
				_gate_flags, _lock)		\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_gate _name##_hw = {			\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.bit_idx = _bit_idx,				\
		.flags = _gate_flags,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_gate_ops, _flags,			\
			_name##_parent_names, _name##_parents);

#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _table, _lock)	\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_divider _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.shift = _shift,				\
		.width = _width,				\
		.flags = _divider_flags,			\
		.table = _table,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_divider_ops, _flags,		\
			_name##_parent_names, _name##_parents);

#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _lock)		\
	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, NULL, _lock)

#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name,		\
				_parent_ptr, _flags, _reg,	\
				_shift, _width, _divider_flags,	\
				_table, _lock)			\
	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
				_flags, _reg, _shift, _width,	\
				_divider_flags, _table, _lock)	\

#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
				_reg, _shift, _width,		\
				_mux_flags, _lock)		\
	static struct clk _name;				\
	static struct clk_mux _name##_hw = {			\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.reg = _reg,					\
		.shift = _shift,				\
		.mask = BIT(_width) - 1,			\
		.flags = _mux_flags,				\
		.lock = _lock,					\
	};							\
	DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names,	\
			_parents);

#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,		\
				_parent_ptr, _flags,		\
				_mult, _div)			\
	static struct clk _name;				\
	static const char *_name##_parent_names[] = {		\
		_parent_name,					\
	};							\
	static struct clk *_name##_parents[] = {		\
		_parent_ptr,					\
	};							\
	static struct clk_fixed_factor _name##_hw = {		\
		.hw = {						\
			.clk = &_name,				\
		},						\
		.mult = _mult,					\
		.div = _div,					\
	};							\
	DEFINE_CLK(_name, clk_fixed_factor_ops, _flags,		\
			_name##_parent_names, _name##_parents);

/**
 * __clk_init - initialize the data structures in a struct clk
 * @dev:	device initializing this clk, placeholder for now
 * @clk:	clk being initialized
 *
 * Initializes the lists in struct clk, queries the hardware for the
 * parent and rate and sets them both.
 *
 * Any struct clk passed into __clk_init must have the following members
 * populated:
 * 	.name
 * 	.ops
 * 	.hw
 * 	.parent_names
 * 	.num_parents
 * 	.flags
 *
 * It is not necessary to call clk_register if __clk_init is used directly with
 * statically initialized clock data.
 *
 * Returns 0 on success, otherwise an error code.
 */
int __clk_init(struct device *dev, struct clk *clk);

struct clk *__clk_register(struct device *dev, struct clk_hw *hw);

#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PRIVATE_H */
Commit	Line	Data
b2476490 MT	1	/*
	2	* linux/include/linux/clk-private.h
	3	*
	4	* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
	5	* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef __LINUX_CLK_PRIVATE_H
	12	#define __LINUX_CLK_PRIVATE_H
	13
	14	#include <linux/clk-provider.h>
fcb0ee6a	15	#include <linux/kref.h>
b2476490 MT	16	#include <linux/list.h>
	17
	18	/*
	19	* WARNING: Do not include clk-private.h from any file that implements struct
	20	* clk_ops. Doing so is a layering violation!
	21	*
	22	* This header exists only to allow for statically initialized clock data. Any
	23	* static clock data must be defined in a separate file from the logic that
	24	* implements the clock operations for that same data.
	25	*/
	26
	27	#ifdef CONFIG_COMMON_CLK
	28
ac2df527 SN	29	struct module;
ac2df527 SN	30
b2476490 MT	31	struct clk {
	32	const char *name;
	33	const struct clk_ops *ops;
	34	struct clk_hw *hw;
ac2df527	35	struct module *owner;
b2476490	36	struct clk *parent;
d305fb78	37	const char **parent_names;
b2476490 MT	38	struct clk **parents;
b2476490 MT	39	u8 num_parents;
71472c0c	40	u8 new_parent_index;
b2476490 MT	41	unsigned long rate;
b2476490 MT	42	unsigned long new_rate;
71472c0c JH	43	struct clk *new_parent;
71472c0c JH	44	struct clk *new_child;
b2476490 MT	45	unsigned long flags;
	46	unsigned int enable_count;
	47	unsigned int prepare_count;
5279fc40	48	unsigned long accuracy;
e59c5371	49	int phase;
b2476490 MT	50	struct hlist_head children;
b2476490 MT	51	struct hlist_node child_node;
6314b679	52	struct hlist_node debug_node;
b2476490	53	unsigned int notifier_count;
ea72dc2c	54	#ifdef CONFIG_DEBUG_FS
b2476490 MT	55	struct dentry *dentry;
b2476490 MT	56	#endif
fcb0ee6a	57	struct kref ref;
b2476490 MT	58	};
b2476490 MT	59
9d9f78ed MT	60	/*
	61	* DOC: Basic clock implementations common to many platforms
	62	*
	63	* Each basic clock hardware type is comprised of a structure describing the
	64	* clock hardware, implementations of the relevant callbacks in struct clk_ops,
	65	* unique flags for that hardware type, a registration function and an
	66	* alternative macro for static initialization
	67	*/
	68
182f9e8c VK	69	#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
	70	_parents) \
	71	static struct clk _name = { \
	72	.name = #_name, \
	73	.ops = &_ops, \
	74	.hw = &_name##_hw.hw, \
	75	.parent_names = _parent_names, \
	76	.num_parents = ARRAY_SIZE(_parent_names), \
	77	.parents = _parents, \
f7d8caad	78	.flags = _flags \| CLK_IS_BASIC, \
182f9e8c VK	79	}
182f9e8c VK	80
9d9f78ed MT	81	#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
	82	_fixed_rate_flags) \
	83	static struct clk _name; \
e447c50e	84	static const char *_name##_parent_names[] = {}; \
9d9f78ed MT	85	static struct clk_fixed_rate _name##_hw = { \
	86	.hw = { \
	87	.clk = &_name, \
	88	}, \
	89	.fixed_rate = _rate, \
	90	.flags = _fixed_rate_flags, \
	91	}; \
182f9e8c VK	92	DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
182f9e8c VK	93	_name##_parent_names, NULL);
9d9f78ed	94
9d9f78ed MT	95	#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
	96	_flags, _reg, _bit_idx, \
	97	_gate_flags, _lock) \
	98	static struct clk _name; \
e447c50e	99	static const char *_name##_parent_names[] = { \
9d9f78ed MT	100	_parent_name, \
	101	}; \
	102	static struct clk *_name##_parents[] = { \
	103	_parent_ptr, \
	104	}; \
	105	static struct clk_gate _name##_hw = { \
	106	.hw = { \
	107	.clk = &_name, \
	108	}, \
	109	.reg = _reg, \
	110	.bit_idx = _bit_idx, \
	111	.flags = _gate_flags, \
	112	.lock = _lock, \
	113	}; \
182f9e8c VK	114	DEFINE_CLK(_name, clk_gate_ops, _flags, \
182f9e8c VK	115	_name##_parent_names, _name##_parents);
9d9f78ed	116
357c3f0a	117	#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
9d9f78ed	118	_flags, _reg, _shift, _width, \
357c3f0a	119	_divider_flags, _table, _lock) \
9d9f78ed	120	static struct clk _name; \
e447c50e	121	static const char *_name##_parent_names[] = { \
9d9f78ed MT	122	_parent_name, \
	123	}; \
	124	static struct clk *_name##_parents[] = { \
	125	_parent_ptr, \
	126	}; \
	127	static struct clk_divider _name##_hw = { \
	128	.hw = { \
	129	.clk = &_name, \
	130	}, \
	131	.reg = _reg, \
	132	.shift = _shift, \
	133	.width = _width, \
	134	.flags = _divider_flags, \
357c3f0a	135	.table = _table, \
9d9f78ed MT	136	.lock = _lock, \
9d9f78ed MT	137	}; \
182f9e8c VK	138	DEFINE_CLK(_name, clk_divider_ops, _flags, \
182f9e8c VK	139	_name##_parent_names, _name##_parents);
9d9f78ed	140
357c3f0a RN	141	#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	142	_flags, _reg, _shift, _width, \
	143	_divider_flags, _lock) \
	144	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	145	_flags, _reg, _shift, _width, \
	146	_divider_flags, NULL, _lock)
	147
	148	#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
	149	_parent_ptr, _flags, _reg, \
	150	_shift, _width, _divider_flags, \
	151	_table, _lock) \
	152	_DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
	153	_flags, _reg, _shift, _width, \
	154	_divider_flags, _table, _lock) \
	155
9d9f78ed MT	156	#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
	157	_reg, _shift, _width, \
	158	_mux_flags, _lock) \
	159	static struct clk _name; \
	160	static struct clk_mux _name##_hw = { \
	161	.hw = { \
	162	.clk = &_name, \
	163	}, \
	164	.reg = _reg, \
	165	.shift = _shift, \
ce4f3313	166	.mask = BIT(_width) - 1, \
9d9f78ed MT	167	.flags = _mux_flags, \
	168	.lock = _lock, \
	169	}; \
182f9e8c VK	170	DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
182f9e8c VK	171	_parents);
9d9f78ed	172
f0948f59 SH	173	#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
	174	_parent_ptr, _flags, \
	175	_mult, _div) \
	176	static struct clk _name; \
	177	static const char *_name##_parent_names[] = { \
	178	_parent_name, \
	179	}; \
	180	static struct clk *_name##_parents[] = { \
	181	_parent_ptr, \
	182	}; \
	183	static struct clk_fixed_factor _name##_hw = { \
	184	.hw = { \
	185	.clk = &_name, \
	186	}, \
	187	.mult = _mult, \
	188	.div = _div, \
	189	}; \
	190	DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
	191	_name##_parent_names, _name##_parents);
	192
b2476490 MT	193	/**
	194	* __clk_init - initialize the data structures in a struct clk
	195	* @dev: device initializing this clk, placeholder for now
	196	* @clk: clk being initialized
	197	*
	198	* Initializes the lists in struct clk, queries the hardware for the
	199	* parent and rate and sets them both.
	200	*
	201	* Any struct clk passed into __clk_init must have the following members
	202	* populated:
	203	* .name
	204	* .ops
	205	* .hw
	206	* .parent_names
	207	* .num_parents
	208	* .flags
	209	*
	210	* It is not necessary to call clk_register if __clk_init is used directly with
	211	* statically initialized clock data.
d1302a36 MT	212	*
d1302a36 MT	213	* Returns 0 on success, otherwise an error code.
b2476490	214	*/
d1302a36	215	int __clk_init(struct device dev, struct clk clk);
b2476490	216
0197b3ea SK	217	struct clk __clk_register(struct device dev, struct clk_hw *hw);
0197b3ea SK	218
b2476490 MT	219	#endif /* CONFIG_COMMON_CLK */
b2476490 MT	220	#endif /* CLK_PRIVATE_H */