Commit | Line | Data |
---|---|---|
b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-private.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PRIVATE_H | |
12 | #define __LINUX_CLK_PRIVATE_H | |
13 | ||
14 | #include <linux/clk-provider.h> | |
15 | #include <linux/list.h> | |
16 | ||
17 | /* | |
18 | * WARNING: Do not include clk-private.h from any file that implements struct | |
19 | * clk_ops. Doing so is a layering violation! | |
20 | * | |
21 | * This header exists only to allow for statically initialized clock data. Any | |
22 | * static clock data must be defined in a separate file from the logic that | |
23 | * implements the clock operations for that same data. | |
24 | */ | |
25 | ||
26 | #ifdef CONFIG_COMMON_CLK | |
27 | ||
28 | struct clk { | |
29 | const char *name; | |
30 | const struct clk_ops *ops; | |
31 | struct clk_hw *hw; | |
32 | struct clk *parent; | |
d305fb78 | 33 | const char **parent_names; |
b2476490 MT |
34 | struct clk **parents; |
35 | u8 num_parents; | |
71472c0c | 36 | u8 new_parent_index; |
b2476490 MT |
37 | unsigned long rate; |
38 | unsigned long new_rate; | |
71472c0c JH |
39 | struct clk *new_parent; |
40 | struct clk *new_child; | |
b2476490 MT |
41 | unsigned long flags; |
42 | unsigned int enable_count; | |
43 | unsigned int prepare_count; | |
44 | struct hlist_head children; | |
45 | struct hlist_node child_node; | |
46 | unsigned int notifier_count; | |
47 | #ifdef CONFIG_COMMON_CLK_DEBUG | |
48 | struct dentry *dentry; | |
49 | #endif | |
50 | }; | |
51 | ||
9d9f78ed MT |
52 | /* |
53 | * DOC: Basic clock implementations common to many platforms | |
54 | * | |
55 | * Each basic clock hardware type is comprised of a structure describing the | |
56 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
57 | * unique flags for that hardware type, a registration function and an | |
58 | * alternative macro for static initialization | |
59 | */ | |
60 | ||
182f9e8c VK |
61 | #define DEFINE_CLK(_name, _ops, _flags, _parent_names, \ |
62 | _parents) \ | |
63 | static struct clk _name = { \ | |
64 | .name = #_name, \ | |
65 | .ops = &_ops, \ | |
66 | .hw = &_name##_hw.hw, \ | |
67 | .parent_names = _parent_names, \ | |
68 | .num_parents = ARRAY_SIZE(_parent_names), \ | |
69 | .parents = _parents, \ | |
f7d8caad | 70 | .flags = _flags | CLK_IS_BASIC, \ |
182f9e8c VK |
71 | } |
72 | ||
9d9f78ed MT |
73 | #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ |
74 | _fixed_rate_flags) \ | |
75 | static struct clk _name; \ | |
e447c50e | 76 | static const char *_name##_parent_names[] = {}; \ |
9d9f78ed MT |
77 | static struct clk_fixed_rate _name##_hw = { \ |
78 | .hw = { \ | |
79 | .clk = &_name, \ | |
80 | }, \ | |
81 | .fixed_rate = _rate, \ | |
82 | .flags = _fixed_rate_flags, \ | |
83 | }; \ | |
182f9e8c VK |
84 | DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \ |
85 | _name##_parent_names, NULL); | |
9d9f78ed | 86 | |
9d9f78ed MT |
87 | #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ |
88 | _flags, _reg, _bit_idx, \ | |
89 | _gate_flags, _lock) \ | |
90 | static struct clk _name; \ | |
e447c50e | 91 | static const char *_name##_parent_names[] = { \ |
9d9f78ed MT |
92 | _parent_name, \ |
93 | }; \ | |
94 | static struct clk *_name##_parents[] = { \ | |
95 | _parent_ptr, \ | |
96 | }; \ | |
97 | static struct clk_gate _name##_hw = { \ | |
98 | .hw = { \ | |
99 | .clk = &_name, \ | |
100 | }, \ | |
101 | .reg = _reg, \ | |
102 | .bit_idx = _bit_idx, \ | |
103 | .flags = _gate_flags, \ | |
104 | .lock = _lock, \ | |
105 | }; \ | |
182f9e8c VK |
106 | DEFINE_CLK(_name, clk_gate_ops, _flags, \ |
107 | _name##_parent_names, _name##_parents); | |
9d9f78ed | 108 | |
357c3f0a | 109 | #define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ |
9d9f78ed | 110 | _flags, _reg, _shift, _width, \ |
357c3f0a | 111 | _divider_flags, _table, _lock) \ |
9d9f78ed | 112 | static struct clk _name; \ |
e447c50e | 113 | static const char *_name##_parent_names[] = { \ |
9d9f78ed MT |
114 | _parent_name, \ |
115 | }; \ | |
116 | static struct clk *_name##_parents[] = { \ | |
117 | _parent_ptr, \ | |
118 | }; \ | |
119 | static struct clk_divider _name##_hw = { \ | |
120 | .hw = { \ | |
121 | .clk = &_name, \ | |
122 | }, \ | |
123 | .reg = _reg, \ | |
124 | .shift = _shift, \ | |
125 | .width = _width, \ | |
126 | .flags = _divider_flags, \ | |
357c3f0a | 127 | .table = _table, \ |
9d9f78ed MT |
128 | .lock = _lock, \ |
129 | }; \ | |
182f9e8c VK |
130 | DEFINE_CLK(_name, clk_divider_ops, _flags, \ |
131 | _name##_parent_names, _name##_parents); | |
9d9f78ed | 132 | |
357c3f0a RN |
133 | #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ |
134 | _flags, _reg, _shift, _width, \ | |
135 | _divider_flags, _lock) \ | |
136 | _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ | |
137 | _flags, _reg, _shift, _width, \ | |
138 | _divider_flags, NULL, _lock) | |
139 | ||
140 | #define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \ | |
141 | _parent_ptr, _flags, _reg, \ | |
142 | _shift, _width, _divider_flags, \ | |
143 | _table, _lock) \ | |
144 | _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ | |
145 | _flags, _reg, _shift, _width, \ | |
146 | _divider_flags, _table, _lock) \ | |
147 | ||
9d9f78ed MT |
148 | #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ |
149 | _reg, _shift, _width, \ | |
150 | _mux_flags, _lock) \ | |
151 | static struct clk _name; \ | |
152 | static struct clk_mux _name##_hw = { \ | |
153 | .hw = { \ | |
154 | .clk = &_name, \ | |
155 | }, \ | |
156 | .reg = _reg, \ | |
157 | .shift = _shift, \ | |
ce4f3313 | 158 | .mask = BIT(_width) - 1, \ |
9d9f78ed MT |
159 | .flags = _mux_flags, \ |
160 | .lock = _lock, \ | |
161 | }; \ | |
182f9e8c VK |
162 | DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \ |
163 | _parents); | |
9d9f78ed | 164 | |
f0948f59 SH |
165 | #define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \ |
166 | _parent_ptr, _flags, \ | |
167 | _mult, _div) \ | |
168 | static struct clk _name; \ | |
169 | static const char *_name##_parent_names[] = { \ | |
170 | _parent_name, \ | |
171 | }; \ | |
172 | static struct clk *_name##_parents[] = { \ | |
173 | _parent_ptr, \ | |
174 | }; \ | |
175 | static struct clk_fixed_factor _name##_hw = { \ | |
176 | .hw = { \ | |
177 | .clk = &_name, \ | |
178 | }, \ | |
179 | .mult = _mult, \ | |
180 | .div = _div, \ | |
181 | }; \ | |
182 | DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \ | |
183 | _name##_parent_names, _name##_parents); | |
184 | ||
b2476490 MT |
185 | /** |
186 | * __clk_init - initialize the data structures in a struct clk | |
187 | * @dev: device initializing this clk, placeholder for now | |
188 | * @clk: clk being initialized | |
189 | * | |
190 | * Initializes the lists in struct clk, queries the hardware for the | |
191 | * parent and rate and sets them both. | |
192 | * | |
193 | * Any struct clk passed into __clk_init must have the following members | |
194 | * populated: | |
195 | * .name | |
196 | * .ops | |
197 | * .hw | |
198 | * .parent_names | |
199 | * .num_parents | |
200 | * .flags | |
201 | * | |
202 | * It is not necessary to call clk_register if __clk_init is used directly with | |
203 | * statically initialized clock data. | |
d1302a36 MT |
204 | * |
205 | * Returns 0 on success, otherwise an error code. | |
b2476490 | 206 | */ |
d1302a36 | 207 | int __clk_init(struct device *dev, struct clk *clk); |
b2476490 | 208 | |
0197b3ea SK |
209 | struct clk *__clk_register(struct device *dev, struct clk_hw *hw); |
210 | ||
b2476490 MT |
211 | #endif /* CONFIG_COMMON_CLK */ |
212 | #endif /* CLK_PRIVATE_H */ |