Commit | Line | Data |
---|---|---|
b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
aa514ce3 | 14 | #include <linux/io.h> |
355bb165 | 15 | #include <linux/of.h> |
b2476490 MT |
16 | |
17 | #ifdef CONFIG_COMMON_CLK | |
18 | ||
b2476490 MT |
19 | /* |
20 | * flags used across common struct clk. these flags should only affect the | |
21 | * top-level framework. custom flags for dealing with hardware specifics | |
22 | * belong in struct clk_foo | |
23 | */ | |
24 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
25 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
26 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
27 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
28 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ | |
f7d8caad | 29 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 30 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 31 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 32 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 33 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
b2476490 | 34 | |
61ae7656 | 35 | struct clk; |
0197b3ea | 36 | struct clk_hw; |
035a61c3 | 37 | struct clk_core; |
c646cbf1 | 38 | struct dentry; |
0197b3ea | 39 | |
0817b62c BB |
40 | /** |
41 | * struct clk_rate_request - Structure encoding the clk constraints that | |
42 | * a clock user might require. | |
43 | * | |
44 | * @rate: Requested clock rate. This field will be adjusted by | |
45 | * clock drivers according to hardware capabilities. | |
46 | * @min_rate: Minimum rate imposed by clk users. | |
47 | * @max_rate: Maximum rate a imposed by clk users. | |
48 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the | |
49 | * requested constraints. | |
50 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
51 | * requested constraints. | |
52 | * | |
53 | */ | |
54 | struct clk_rate_request { | |
55 | unsigned long rate; | |
56 | unsigned long min_rate; | |
57 | unsigned long max_rate; | |
58 | unsigned long best_parent_rate; | |
59 | struct clk_hw *best_parent_hw; | |
60 | }; | |
61 | ||
b2476490 MT |
62 | /** |
63 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
64 | * be provided by the clock implementation, and will be called by drivers | |
65 | * through the clk_* api. | |
66 | * | |
67 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
68 | * the clock is fully prepared, and it's safe to call clk_enable. |
69 | * This callback is intended to allow clock implementations to | |
70 | * do any initialisation that may sleep. Called with | |
71 | * prepare_lock held. | |
b2476490 MT |
72 | * |
73 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
74 | * undo any work done in the @prepare callback. Called with |
75 | * prepare_lock held. | |
b2476490 | 76 | * |
3d6ee287 UH |
77 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
78 | * This function is allowed to sleep. Optional, if this op is not | |
79 | * set then the prepare count will be used. | |
80 | * | |
3cc8247f UH |
81 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
82 | * clk_disable_unused for prepare clocks with special needs. | |
83 | * Called with prepare mutex held. This function may sleep. | |
84 | * | |
b2476490 | 85 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
86 | * clock is generating a valid clock signal, usable by consumer |
87 | * devices. Called with enable_lock held. This function must not | |
88 | * sleep. | |
b2476490 MT |
89 | * |
90 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 91 | * This function must not sleep. |
b2476490 | 92 | * |
119c7127 | 93 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
94 | * This function must not sleep. Optional, if this op is not |
95 | * set then the enable count will be used. | |
119c7127 | 96 | * |
7c045a55 MT |
97 | * @disable_unused: Disable the clock atomically. Only called from |
98 | * clk_disable_unused for gate clocks with special needs. | |
99 | * Called with enable_lock held. This function must not | |
100 | * sleep. | |
101 | * | |
7ce3e8cc | 102 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
103 | * parent rate is an input parameter. It is up to the caller to |
104 | * ensure that the prepare_mutex is held across this call. | |
105 | * Returns the calculated rate. Optional, but recommended - if | |
106 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
107 | * |
108 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
109 | * supported by the clock. The parent rate is an input/output |
110 | * parameter. | |
b2476490 | 111 | * |
71472c0c JH |
112 | * @determine_rate: Given a target rate as input, returns the closest rate |
113 | * actually supported by the clock, and optionally the parent clock | |
114 | * that should be used to provide the clock rate. | |
115 | * | |
b2476490 | 116 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
117 | * possible parents specify a new parent by passing in the index |
118 | * as a u8 corresponding to the parent in either the .parent_names | |
119 | * or .parents arrays. This function in affect translates an | |
120 | * array index into the value programmed into the hardware. | |
121 | * Returns 0 on success, -EERROR otherwise. | |
122 | * | |
b2476490 | 123 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
124 | * return value is a u8 which specifies the index corresponding to |
125 | * the parent clock. This index can be applied to either the | |
126 | * .parent_names or .parents arrays. In short, this function | |
127 | * translates the parent value read from hardware into an array | |
128 | * index. Currently only called when the clock is initialized by | |
129 | * __clk_init. This callback is mandatory for clocks with | |
130 | * multiple parents. It is optional (and unnecessary) for clocks | |
131 | * with 0 or 1 parents. | |
b2476490 | 132 | * |
1c0035d7 SG |
133 | * @set_rate: Change the rate of this clock. The requested rate is specified |
134 | * by the second argument, which should typically be the return | |
135 | * of .round_rate call. The third argument gives the parent rate | |
136 | * which is likely helpful for most .set_rate implementation. | |
137 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 138 | * |
3fa2252b SB |
139 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
140 | * requested rate is specified by the second argument, which | |
141 | * should typically be the return of .round_rate call. The | |
142 | * third argument gives the parent rate which is likely helpful | |
143 | * for most .set_rate_and_parent implementation. The fourth | |
144 | * argument gives the parent index. This callback is optional (and | |
145 | * unnecessary) for clocks with 0 or 1 parents as well as | |
146 | * for clocks that can tolerate switching the rate and the parent | |
147 | * separately via calls to .set_parent and .set_rate. | |
148 | * Returns 0 on success, -EERROR otherwise. | |
149 | * | |
54e73016 GU |
150 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
151 | * is expressed in ppb (parts per billion). The parent accuracy is | |
152 | * an input parameter. | |
153 | * Returns the calculated accuracy. Optional - if this op is not | |
154 | * set then clock accuracy will be initialized to parent accuracy | |
155 | * or 0 (perfect clock) if clock has no parent. | |
156 | * | |
9824cf73 MR |
157 | * @get_phase: Queries the hardware to get the current phase of a clock. |
158 | * Returned values are 0-359 degrees on success, negative | |
159 | * error codes on failure. | |
160 | * | |
e59c5371 MT |
161 | * @set_phase: Shift the phase this clock signal in degrees specified |
162 | * by the second argument. Valid values for degrees are | |
163 | * 0-359. Return 0 on success, otherwise -EERROR. | |
164 | * | |
54e73016 GU |
165 | * @init: Perform platform-specific initialization magic. |
166 | * This is not not used by any of the basic clock types. | |
167 | * Please consider other ways of solving initialization problems | |
168 | * before using this callback, as its use is discouraged. | |
169 | * | |
c646cbf1 AE |
170 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
171 | * is called once, after the debugfs directory entry for this | |
172 | * clock has been created. The dentry pointer representing that | |
173 | * directory is provided as an argument. Called with | |
174 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
175 | * | |
3fa2252b | 176 | * |
b2476490 MT |
177 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
178 | * implementations to split any work between atomic (enable) and sleepable | |
179 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
180 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 181 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
182 | * |
183 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
184 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
185 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
186 | * called before clk_enable. | |
187 | */ | |
188 | struct clk_ops { | |
189 | int (*prepare)(struct clk_hw *hw); | |
190 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 191 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 192 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
193 | int (*enable)(struct clk_hw *hw); |
194 | void (*disable)(struct clk_hw *hw); | |
195 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 196 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
197 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
198 | unsigned long parent_rate); | |
54e73016 GU |
199 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
200 | unsigned long *parent_rate); | |
0817b62c BB |
201 | int (*determine_rate)(struct clk_hw *hw, |
202 | struct clk_rate_request *req); | |
b2476490 MT |
203 | int (*set_parent)(struct clk_hw *hw, u8 index); |
204 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
205 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
206 | unsigned long parent_rate); | |
3fa2252b SB |
207 | int (*set_rate_and_parent)(struct clk_hw *hw, |
208 | unsigned long rate, | |
209 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
210 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
211 | unsigned long parent_accuracy); | |
9824cf73 | 212 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 213 | int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490 | 214 | void (*init)(struct clk_hw *hw); |
c646cbf1 | 215 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
216 | }; |
217 | ||
0197b3ea SK |
218 | /** |
219 | * struct clk_init_data - holds init data that's common to all clocks and is | |
220 | * shared between the clock provider and the common clock framework. | |
221 | * | |
222 | * @name: clock name | |
223 | * @ops: operations this clock supports | |
224 | * @parent_names: array of string names for all possible parents | |
225 | * @num_parents: number of possible parents | |
226 | * @flags: framework-level hints and quirks | |
227 | */ | |
228 | struct clk_init_data { | |
229 | const char *name; | |
230 | const struct clk_ops *ops; | |
2893c379 | 231 | const char * const *parent_names; |
0197b3ea SK |
232 | u8 num_parents; |
233 | unsigned long flags; | |
234 | }; | |
235 | ||
236 | /** | |
237 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
238 | * hardware-specific structure. struct clk_hw should be declared within struct | |
239 | * clk_foo and then referenced by the struct clk instance that uses struct | |
240 | * clk_foo's clk_ops | |
241 | * | |
035a61c3 TV |
242 | * @core: pointer to the struct clk_core instance that points back to this |
243 | * struct clk_hw instance | |
244 | * | |
245 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
246 | * into the clk API | |
0197b3ea SK |
247 | * |
248 | * @init: pointer to struct clk_init_data that contains the init data shared | |
249 | * with the common clock framework. | |
250 | */ | |
251 | struct clk_hw { | |
035a61c3 | 252 | struct clk_core *core; |
0197b3ea | 253 | struct clk *clk; |
dc4cd941 | 254 | const struct clk_init_data *init; |
0197b3ea SK |
255 | }; |
256 | ||
9d9f78ed MT |
257 | /* |
258 | * DOC: Basic clock implementations common to many platforms | |
259 | * | |
260 | * Each basic clock hardware type is comprised of a structure describing the | |
261 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
262 | * unique flags for that hardware type, a registration function and an | |
263 | * alternative macro for static initialization | |
264 | */ | |
265 | ||
266 | /** | |
267 | * struct clk_fixed_rate - fixed-rate clock | |
268 | * @hw: handle between common and hardware-specific interfaces | |
269 | * @fixed_rate: constant frequency of clock | |
270 | */ | |
271 | struct clk_fixed_rate { | |
272 | struct clk_hw hw; | |
273 | unsigned long fixed_rate; | |
0903ea60 | 274 | unsigned long fixed_accuracy; |
9d9f78ed MT |
275 | u8 flags; |
276 | }; | |
277 | ||
bffad66e | 278 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
279 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
280 | const char *parent_name, unsigned long flags, | |
281 | unsigned long fixed_rate); | |
0903ea60 BB |
282 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
283 | const char *name, const char *parent_name, unsigned long flags, | |
284 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
9d9f78ed | 285 | |
015ba402 GL |
286 | void of_fixed_clk_setup(struct device_node *np); |
287 | ||
9d9f78ed MT |
288 | /** |
289 | * struct clk_gate - gating clock | |
290 | * | |
291 | * @hw: handle between common and hardware-specific interfaces | |
292 | * @reg: register controlling gate | |
293 | * @bit_idx: single bit controlling gate | |
294 | * @flags: hardware-specific flags | |
295 | * @lock: register lock | |
296 | * | |
297 | * Clock which can gate its output. Implements .enable & .disable | |
298 | * | |
299 | * Flags: | |
1f73f31a | 300 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
301 | * enable the clock. Setting this flag does the opposite: setting the bit |
302 | * disable the clock and clearing it enables the clock | |
04577994 | 303 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
304 | * of this register, and mask of gate bits are in higher 16-bit of this |
305 | * register. While setting the gate bits, higher 16-bit should also be | |
306 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
307 | */ |
308 | struct clk_gate { | |
309 | struct clk_hw hw; | |
310 | void __iomem *reg; | |
311 | u8 bit_idx; | |
312 | u8 flags; | |
313 | spinlock_t *lock; | |
9d9f78ed MT |
314 | }; |
315 | ||
316 | #define CLK_GATE_SET_TO_DISABLE BIT(0) | |
04577994 | 317 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 318 | |
bffad66e | 319 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
320 | struct clk *clk_register_gate(struct device *dev, const char *name, |
321 | const char *parent_name, unsigned long flags, | |
322 | void __iomem *reg, u8 bit_idx, | |
323 | u8 clk_gate_flags, spinlock_t *lock); | |
4e3c021f | 324 | void clk_unregister_gate(struct clk *clk); |
9d9f78ed | 325 | |
357c3f0a RN |
326 | struct clk_div_table { |
327 | unsigned int val; | |
328 | unsigned int div; | |
329 | }; | |
330 | ||
9d9f78ed MT |
331 | /** |
332 | * struct clk_divider - adjustable divider clock | |
333 | * | |
334 | * @hw: handle between common and hardware-specific interfaces | |
335 | * @reg: register containing the divider | |
336 | * @shift: shift to the divider bit field | |
337 | * @width: width of the divider bit field | |
357c3f0a | 338 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
339 | * @lock: register lock |
340 | * | |
341 | * Clock with an adjustable divider affecting its output frequency. Implements | |
342 | * .recalc_rate, .set_rate and .round_rate | |
343 | * | |
344 | * Flags: | |
345 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
346 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
347 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 348 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 349 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 350 | * the hardware register |
056b2053 SB |
351 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
352 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
353 | * Some hardware implementations gracefully handle this case and allow a | |
354 | * zero divisor by not modifying their input clock | |
355 | * (divide by one / bypass). | |
d57dfe75 | 356 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
357 | * of this register, and mask of divider bits are in higher 16-bit of this |
358 | * register. While setting the divider bits, higher 16-bit should also be | |
359 | * updated to indicate changing divider bits. | |
774b5143 MC |
360 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
361 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
362 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
363 | * not be changed by the clock framework. | |
afe76c8f JQ |
364 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
365 | * except when the value read from the register is zero, the divisor is | |
366 | * 2^width of the field. | |
9d9f78ed MT |
367 | */ |
368 | struct clk_divider { | |
369 | struct clk_hw hw; | |
370 | void __iomem *reg; | |
371 | u8 shift; | |
372 | u8 width; | |
373 | u8 flags; | |
357c3f0a | 374 | const struct clk_div_table *table; |
9d9f78ed | 375 | spinlock_t *lock; |
9d9f78ed MT |
376 | }; |
377 | ||
378 | #define CLK_DIVIDER_ONE_BASED BIT(0) | |
379 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 380 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 381 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 382 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 383 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 384 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
9d9f78ed | 385 | |
bffad66e | 386 | extern const struct clk_ops clk_divider_ops; |
bca9690b SB |
387 | |
388 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
389 | unsigned int val, const struct clk_div_table *table, | |
390 | unsigned long flags); | |
391 | long divider_round_rate(struct clk_hw *hw, unsigned long rate, | |
392 | unsigned long *prate, const struct clk_div_table *table, | |
393 | u8 width, unsigned long flags); | |
394 | int divider_get_val(unsigned long rate, unsigned long parent_rate, | |
395 | const struct clk_div_table *table, u8 width, | |
396 | unsigned long flags); | |
397 | ||
9d9f78ed MT |
398 | struct clk *clk_register_divider(struct device *dev, const char *name, |
399 | const char *parent_name, unsigned long flags, | |
400 | void __iomem *reg, u8 shift, u8 width, | |
401 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
402 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
403 | const char *parent_name, unsigned long flags, | |
404 | void __iomem *reg, u8 shift, u8 width, | |
405 | u8 clk_divider_flags, const struct clk_div_table *table, | |
406 | spinlock_t *lock); | |
4e3c021f | 407 | void clk_unregister_divider(struct clk *clk); |
9d9f78ed MT |
408 | |
409 | /** | |
410 | * struct clk_mux - multiplexer clock | |
411 | * | |
412 | * @hw: handle between common and hardware-specific interfaces | |
413 | * @reg: register controlling multiplexer | |
414 | * @shift: shift to multiplexer bit field | |
415 | * @width: width of mutliplexer bit field | |
3566d40c | 416 | * @flags: hardware-specific flags |
9d9f78ed MT |
417 | * @lock: register lock |
418 | * | |
419 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
420 | * and .recalc_rate | |
421 | * | |
422 | * Flags: | |
423 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 424 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 425 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
426 | * register, and mask of mux bits are in higher 16-bit of this register. |
427 | * While setting the mux bits, higher 16-bit should also be updated to | |
428 | * indicate changing mux bits. | |
15a02c1f SB |
429 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
430 | * frequency. | |
9d9f78ed MT |
431 | */ |
432 | struct clk_mux { | |
433 | struct clk_hw hw; | |
434 | void __iomem *reg; | |
ce4f3313 PDS |
435 | u32 *table; |
436 | u32 mask; | |
9d9f78ed | 437 | u8 shift; |
9d9f78ed MT |
438 | u8 flags; |
439 | spinlock_t *lock; | |
440 | }; | |
441 | ||
442 | #define CLK_MUX_INDEX_ONE BIT(0) | |
443 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 444 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
445 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
446 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
9d9f78ed | 447 | |
bffad66e | 448 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 449 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 450 | |
9d9f78ed | 451 | struct clk *clk_register_mux(struct device *dev, const char *name, |
2893c379 SH |
452 | const char * const *parent_names, u8 num_parents, |
453 | unsigned long flags, | |
9d9f78ed MT |
454 | void __iomem *reg, u8 shift, u8 width, |
455 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 456 | |
ce4f3313 | 457 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
458 | const char * const *parent_names, u8 num_parents, |
459 | unsigned long flags, | |
ce4f3313 PDS |
460 | void __iomem *reg, u8 shift, u32 mask, |
461 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
462 | ||
4e3c021f KK |
463 | void clk_unregister_mux(struct clk *clk); |
464 | ||
79b16641 GC |
465 | void of_fixed_factor_clk_setup(struct device_node *node); |
466 | ||
f0948f59 SH |
467 | /** |
468 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
469 | * | |
470 | * @hw: handle between common and hardware-specific interfaces | |
471 | * @mult: multiplier | |
472 | * @div: divider | |
473 | * | |
474 | * Clock with a fixed multiplier and divider. The output frequency is the | |
475 | * parent clock rate divided by div and multiplied by mult. | |
476 | * Implements .recalc_rate, .set_rate and .round_rate | |
477 | */ | |
478 | ||
479 | struct clk_fixed_factor { | |
480 | struct clk_hw hw; | |
481 | unsigned int mult; | |
482 | unsigned int div; | |
483 | }; | |
484 | ||
3037e9ea | 485 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
486 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
487 | const char *parent_name, unsigned long flags, | |
488 | unsigned int mult, unsigned int div); | |
489 | ||
e2d0e90f HK |
490 | /** |
491 | * struct clk_fractional_divider - adjustable fractional divider clock | |
492 | * | |
493 | * @hw: handle between common and hardware-specific interfaces | |
494 | * @reg: register containing the divider | |
495 | * @mshift: shift to the numerator bit field | |
496 | * @mwidth: width of the numerator bit field | |
497 | * @nshift: shift to the denominator bit field | |
498 | * @nwidth: width of the denominator bit field | |
499 | * @lock: register lock | |
500 | * | |
501 | * Clock with adjustable fractional divider affecting its output frequency. | |
502 | */ | |
e2d0e90f HK |
503 | struct clk_fractional_divider { |
504 | struct clk_hw hw; | |
505 | void __iomem *reg; | |
506 | u8 mshift; | |
934e2536 | 507 | u8 mwidth; |
e2d0e90f HK |
508 | u32 mmask; |
509 | u8 nshift; | |
934e2536 | 510 | u8 nwidth; |
e2d0e90f HK |
511 | u32 nmask; |
512 | u8 flags; | |
513 | spinlock_t *lock; | |
514 | }; | |
515 | ||
516 | extern const struct clk_ops clk_fractional_divider_ops; | |
517 | struct clk *clk_register_fractional_divider(struct device *dev, | |
518 | const char *name, const char *parent_name, unsigned long flags, | |
519 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
520 | u8 clk_divider_flags, spinlock_t *lock); | |
521 | ||
f2e0a532 MR |
522 | /** |
523 | * struct clk_multiplier - adjustable multiplier clock | |
524 | * | |
525 | * @hw: handle between common and hardware-specific interfaces | |
526 | * @reg: register containing the multiplier | |
527 | * @shift: shift to the multiplier bit field | |
528 | * @width: width of the multiplier bit field | |
529 | * @lock: register lock | |
530 | * | |
531 | * Clock with an adjustable multiplier affecting its output frequency. | |
532 | * Implements .recalc_rate, .set_rate and .round_rate | |
533 | * | |
534 | * Flags: | |
535 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
536 | * from the register, with 0 being a valid value effectively | |
537 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
538 | * set, then a null multiplier will be considered as a bypass, | |
539 | * leaving the parent rate unmodified. | |
540 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
541 | * rounded to the closest integer instead of the down one. | |
542 | */ | |
543 | struct clk_multiplier { | |
544 | struct clk_hw hw; | |
545 | void __iomem *reg; | |
546 | u8 shift; | |
547 | u8 width; | |
548 | u8 flags; | |
549 | spinlock_t *lock; | |
550 | }; | |
551 | ||
552 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) | |
553 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
554 | ||
555 | extern const struct clk_ops clk_multiplier_ops; | |
556 | ||
ece70094 PG |
557 | /*** |
558 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
559 | * | |
560 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
561 | * @mux_hw: handle between composite and hardware-specific mux clock |
562 | * @rate_hw: handle between composite and hardware-specific rate clock | |
563 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 564 | * @mux_ops: clock ops for mux |
d3a1c7be | 565 | * @rate_ops: clock ops for rate |
ece70094 PG |
566 | * @gate_ops: clock ops for gate |
567 | */ | |
568 | struct clk_composite { | |
569 | struct clk_hw hw; | |
570 | struct clk_ops ops; | |
571 | ||
572 | struct clk_hw *mux_hw; | |
d3a1c7be | 573 | struct clk_hw *rate_hw; |
ece70094 PG |
574 | struct clk_hw *gate_hw; |
575 | ||
576 | const struct clk_ops *mux_ops; | |
d3a1c7be | 577 | const struct clk_ops *rate_ops; |
ece70094 PG |
578 | const struct clk_ops *gate_ops; |
579 | }; | |
580 | ||
581 | struct clk *clk_register_composite(struct device *dev, const char *name, | |
2893c379 | 582 | const char * const *parent_names, int num_parents, |
ece70094 | 583 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 584 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
585 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
586 | unsigned long flags); | |
587 | ||
c873d14d JS |
588 | /*** |
589 | * struct clk_gpio_gate - gpio gated clock | |
590 | * | |
591 | * @hw: handle between common and hardware-specific interfaces | |
592 | * @gpiod: gpio descriptor | |
593 | * | |
594 | * Clock with a gpio control for enabling and disabling the parent clock. | |
595 | * Implements .enable, .disable and .is_enabled | |
596 | */ | |
597 | ||
598 | struct clk_gpio { | |
599 | struct clk_hw hw; | |
600 | struct gpio_desc *gpiod; | |
601 | }; | |
602 | ||
603 | extern const struct clk_ops clk_gpio_gate_ops; | |
604 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
820ad975 | 605 | const char *parent_name, unsigned gpio, bool active_low, |
c873d14d JS |
606 | unsigned long flags); |
607 | ||
608 | void of_gpio_clk_gate_setup(struct device_node *node); | |
609 | ||
80eeb1f0 SS |
610 | /** |
611 | * struct clk_gpio_mux - gpio controlled clock multiplexer | |
612 | * | |
613 | * @hw: see struct clk_gpio | |
614 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer | |
615 | * | |
616 | * Clock with a gpio control for selecting the parent clock. | |
617 | * Implements .get_parent, .set_parent and .determine_rate | |
618 | */ | |
619 | ||
620 | extern const struct clk_ops clk_gpio_mux_ops; | |
621 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
37bff2c1 | 622 | const char * const *parent_names, u8 num_parents, unsigned gpio, |
80eeb1f0 SS |
623 | bool active_low, unsigned long flags); |
624 | ||
625 | void of_gpio_mux_clk_setup(struct device_node *node); | |
626 | ||
b2476490 MT |
627 | /** |
628 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
629 | * @dev: device that is registering this clock | |
b2476490 | 630 | * @hw: link to hardware-specific clock data |
b2476490 MT |
631 | * |
632 | * clk_register is the primary interface for populating the clock tree with new | |
633 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
634 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
635 | * rest of the clock API. In the event of an error clk_register will return an |
636 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 637 | */ |
0197b3ea | 638 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 639 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 640 | |
1df5c939 | 641 | void clk_unregister(struct clk *clk); |
46c8773a | 642 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 643 | |
b2476490 | 644 | /* helper functions */ |
b76281cb | 645 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 646 | const char *clk_hw_get_name(const struct clk_hw *hw); |
b2476490 | 647 | struct clk_hw *__clk_get_hw(struct clk *clk); |
e7df6f6e SB |
648 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
649 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
650 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 651 | unsigned int index); |
93874681 | 652 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 653 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 654 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e SB |
655 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
656 | bool clk_hw_is_prepared(const struct clk_hw *hw); | |
be68bf88 | 657 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 658 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 659 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
660 | int __clk_mux_determine_rate(struct clk_hw *hw, |
661 | struct clk_rate_request *req); | |
662 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
663 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
664 | struct clk_rate_request *req); | |
42c86547 | 665 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
666 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
667 | unsigned long max_rate); | |
b2476490 | 668 | |
2e65d8bf JMC |
669 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
670 | { | |
671 | dst->clk = src->clk; | |
672 | dst->core = src->core; | |
673 | } | |
674 | ||
b2476490 MT |
675 | /* |
676 | * FIXME clock api without lock protection | |
677 | */ | |
1a9c069c | 678 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 679 | |
766e6a4e GL |
680 | struct of_device_id; |
681 | ||
682 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
683 | ||
0b151deb SH |
684 | struct clk_onecell_data { |
685 | struct clk **clks; | |
686 | unsigned int clk_num; | |
687 | }; | |
688 | ||
819b4861 TK |
689 | extern struct of_device_id __clk_of_table; |
690 | ||
54196ccb | 691 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb SH |
692 | |
693 | #ifdef CONFIG_OF | |
766e6a4e GL |
694 | int of_clk_add_provider(struct device_node *np, |
695 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
696 | void *data), | |
697 | void *data); | |
698 | void of_clk_del_provider(struct device_node *np); | |
699 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |
700 | void *data); | |
494bfec9 | 701 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
f6102742 | 702 | int of_clk_get_parent_count(struct device_node *np); |
2e61dfb3 DN |
703 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
704 | unsigned int size); | |
766e6a4e | 705 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
f2f6c255 | 706 | |
766e6a4e GL |
707 | void of_clk_init(const struct of_device_id *matches); |
708 | ||
0b151deb | 709 | #else /* !CONFIG_OF */ |
f2f6c255 | 710 | |
0b151deb SH |
711 | static inline int of_clk_add_provider(struct device_node *np, |
712 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
713 | void *data), | |
714 | void *data) | |
715 | { | |
716 | return 0; | |
717 | } | |
718 | #define of_clk_del_provider(np) \ | |
719 | { while (0); } | |
720 | static inline struct clk *of_clk_src_simple_get( | |
721 | struct of_phandle_args *clkspec, void *data) | |
722 | { | |
723 | return ERR_PTR(-ENOENT); | |
724 | } | |
725 | static inline struct clk *of_clk_src_onecell_get( | |
726 | struct of_phandle_args *clkspec, void *data) | |
727 | { | |
728 | return ERR_PTR(-ENOENT); | |
729 | } | |
679c51cf SB |
730 | static inline int of_clk_get_parent_count(struct device_node *np) |
731 | { | |
732 | return 0; | |
733 | } | |
734 | static inline int of_clk_parent_fill(struct device_node *np, | |
735 | const char **parents, unsigned int size) | |
736 | { | |
737 | return 0; | |
738 | } | |
0b151deb SH |
739 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
740 | int index) | |
741 | { | |
742 | return NULL; | |
743 | } | |
744 | #define of_clk_init(matches) \ | |
745 | { while (0); } | |
746 | #endif /* CONFIG_OF */ | |
aa514ce3 GS |
747 | |
748 | /* | |
749 | * wrap access to peripherals in accessor routines | |
750 | * for improved portability across platforms | |
751 | */ | |
752 | ||
6d8cdb68 GS |
753 | #if IS_ENABLED(CONFIG_PPC) |
754 | ||
755 | static inline u32 clk_readl(u32 __iomem *reg) | |
756 | { | |
757 | return ioread32be(reg); | |
758 | } | |
759 | ||
760 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
761 | { | |
762 | iowrite32be(val, reg); | |
763 | } | |
764 | ||
765 | #else /* platform dependent I/O accessors */ | |
766 | ||
aa514ce3 GS |
767 | static inline u32 clk_readl(u32 __iomem *reg) |
768 | { | |
769 | return readl(reg); | |
770 | } | |
771 | ||
772 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
773 | { | |
774 | writel(val, reg); | |
775 | } | |
776 | ||
6d8cdb68 GS |
777 | #endif /* platform dependent I/O accessors */ |
778 | ||
fb2b3c9f | 779 | #ifdef CONFIG_DEBUG_FS |
61c7cddf | 780 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
fb2b3c9f PDS |
781 | void *data, const struct file_operations *fops); |
782 | #endif | |
783 | ||
b2476490 MT |
784 | #endif /* CONFIG_COMMON_CLK */ |
785 | #endif /* CLK_PROVIDER_H */ |