Commit | Line | Data |
---|---|---|
b2476490 MT |
1 | /* |
2 | * linux/include/linux/clk-provider.h | |
3 | * | |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __LINUX_CLK_PROVIDER_H | |
12 | #define __LINUX_CLK_PROVIDER_H | |
13 | ||
aa514ce3 | 14 | #include <linux/io.h> |
355bb165 | 15 | #include <linux/of.h> |
b2476490 MT |
16 | |
17 | #ifdef CONFIG_COMMON_CLK | |
18 | ||
b2476490 MT |
19 | /* |
20 | * flags used across common struct clk. these flags should only affect the | |
21 | * top-level framework. custom flags for dealing with hardware specifics | |
22 | * belong in struct clk_foo | |
23 | */ | |
24 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | |
25 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | |
26 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | |
27 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | |
b9610e74 | 28 | /* unused */ |
f7d8caad | 29 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2 | 30 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de3 | 31 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc40 | 32 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
d8d91987 | 33 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
2eb8c710 | 34 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
32b9b109 | 35 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
b2476490 | 36 | |
61ae7656 | 37 | struct clk; |
0197b3ea | 38 | struct clk_hw; |
035a61c3 | 39 | struct clk_core; |
c646cbf1 | 40 | struct dentry; |
0197b3ea | 41 | |
0817b62c BB |
42 | /** |
43 | * struct clk_rate_request - Structure encoding the clk constraints that | |
44 | * a clock user might require. | |
45 | * | |
46 | * @rate: Requested clock rate. This field will be adjusted by | |
47 | * clock drivers according to hardware capabilities. | |
48 | * @min_rate: Minimum rate imposed by clk users. | |
1971dfb7 | 49 | * @max_rate: Maximum rate imposed by clk users. |
0817b62c BB |
50 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
51 | * requested constraints. | |
52 | * @best_parent_hw: The most appropriate parent clock that fulfills the | |
53 | * requested constraints. | |
54 | * | |
55 | */ | |
56 | struct clk_rate_request { | |
57 | unsigned long rate; | |
58 | unsigned long min_rate; | |
59 | unsigned long max_rate; | |
60 | unsigned long best_parent_rate; | |
61 | struct clk_hw *best_parent_hw; | |
62 | }; | |
63 | ||
b2476490 MT |
64 | /** |
65 | * struct clk_ops - Callback operations for hardware clocks; these are to | |
66 | * be provided by the clock implementation, and will be called by drivers | |
67 | * through the clk_* api. | |
68 | * | |
69 | * @prepare: Prepare the clock for enabling. This must not return until | |
725b418b GU |
70 | * the clock is fully prepared, and it's safe to call clk_enable. |
71 | * This callback is intended to allow clock implementations to | |
72 | * do any initialisation that may sleep. Called with | |
73 | * prepare_lock held. | |
b2476490 MT |
74 | * |
75 | * @unprepare: Release the clock from its prepared state. This will typically | |
725b418b GU |
76 | * undo any work done in the @prepare callback. Called with |
77 | * prepare_lock held. | |
b2476490 | 78 | * |
3d6ee287 UH |
79 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
80 | * This function is allowed to sleep. Optional, if this op is not | |
81 | * set then the prepare count will be used. | |
82 | * | |
3cc8247f UH |
83 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
84 | * clk_disable_unused for prepare clocks with special needs. | |
85 | * Called with prepare mutex held. This function may sleep. | |
86 | * | |
b2476490 | 87 | * @enable: Enable the clock atomically. This must not return until the |
725b418b GU |
88 | * clock is generating a valid clock signal, usable by consumer |
89 | * devices. Called with enable_lock held. This function must not | |
90 | * sleep. | |
b2476490 MT |
91 | * |
92 | * @disable: Disable the clock atomically. Called with enable_lock held. | |
725b418b | 93 | * This function must not sleep. |
b2476490 | 94 | * |
119c7127 | 95 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b GU |
96 | * This function must not sleep. Optional, if this op is not |
97 | * set then the enable count will be used. | |
119c7127 | 98 | * |
7c045a55 MT |
99 | * @disable_unused: Disable the clock atomically. Only called from |
100 | * clk_disable_unused for gate clocks with special needs. | |
101 | * Called with enable_lock held. This function must not | |
102 | * sleep. | |
103 | * | |
7ce3e8cc | 104 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b GU |
105 | * parent rate is an input parameter. It is up to the caller to |
106 | * ensure that the prepare_mutex is held across this call. | |
107 | * Returns the calculated rate. Optional, but recommended - if | |
108 | * this op is not set then clock rate will be initialized to 0. | |
b2476490 MT |
109 | * |
110 | * @round_rate: Given a target rate as input, returns the closest rate actually | |
54e73016 GU |
111 | * supported by the clock. The parent rate is an input/output |
112 | * parameter. | |
b2476490 | 113 | * |
71472c0c JH |
114 | * @determine_rate: Given a target rate as input, returns the closest rate |
115 | * actually supported by the clock, and optionally the parent clock | |
116 | * that should be used to provide the clock rate. | |
117 | * | |
b2476490 | 118 | * @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016 GU |
119 | * possible parents specify a new parent by passing in the index |
120 | * as a u8 corresponding to the parent in either the .parent_names | |
121 | * or .parents arrays. This function in affect translates an | |
122 | * array index into the value programmed into the hardware. | |
123 | * Returns 0 on success, -EERROR otherwise. | |
124 | * | |
b2476490 | 125 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b GU |
126 | * return value is a u8 which specifies the index corresponding to |
127 | * the parent clock. This index can be applied to either the | |
128 | * .parent_names or .parents arrays. In short, this function | |
129 | * translates the parent value read from hardware into an array | |
130 | * index. Currently only called when the clock is initialized by | |
131 | * __clk_init. This callback is mandatory for clocks with | |
132 | * multiple parents. It is optional (and unnecessary) for clocks | |
133 | * with 0 or 1 parents. | |
b2476490 | 134 | * |
1c0035d7 SG |
135 | * @set_rate: Change the rate of this clock. The requested rate is specified |
136 | * by the second argument, which should typically be the return | |
137 | * of .round_rate call. The third argument gives the parent rate | |
138 | * which is likely helpful for most .set_rate implementation. | |
139 | * Returns 0 on success, -EERROR otherwise. | |
b2476490 | 140 | * |
3fa2252b SB |
141 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
142 | * requested rate is specified by the second argument, which | |
143 | * should typically be the return of .round_rate call. The | |
144 | * third argument gives the parent rate which is likely helpful | |
145 | * for most .set_rate_and_parent implementation. The fourth | |
146 | * argument gives the parent index. This callback is optional (and | |
147 | * unnecessary) for clocks with 0 or 1 parents as well as | |
148 | * for clocks that can tolerate switching the rate and the parent | |
149 | * separately via calls to .set_parent and .set_rate. | |
150 | * Returns 0 on success, -EERROR otherwise. | |
151 | * | |
54e73016 GU |
152 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
153 | * is expressed in ppb (parts per billion). The parent accuracy is | |
154 | * an input parameter. | |
155 | * Returns the calculated accuracy. Optional - if this op is not | |
156 | * set then clock accuracy will be initialized to parent accuracy | |
157 | * or 0 (perfect clock) if clock has no parent. | |
158 | * | |
9824cf73 MR |
159 | * @get_phase: Queries the hardware to get the current phase of a clock. |
160 | * Returned values are 0-359 degrees on success, negative | |
161 | * error codes on failure. | |
162 | * | |
e59c5371 MT |
163 | * @set_phase: Shift the phase this clock signal in degrees specified |
164 | * by the second argument. Valid values for degrees are | |
165 | * 0-359. Return 0 on success, otherwise -EERROR. | |
166 | * | |
54e73016 GU |
167 | * @init: Perform platform-specific initialization magic. |
168 | * This is not not used by any of the basic clock types. | |
169 | * Please consider other ways of solving initialization problems | |
170 | * before using this callback, as its use is discouraged. | |
171 | * | |
c646cbf1 AE |
172 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
173 | * is called once, after the debugfs directory entry for this | |
174 | * clock has been created. The dentry pointer representing that | |
175 | * directory is provided as an argument. Called with | |
176 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. | |
177 | * | |
3fa2252b | 178 | * |
b2476490 MT |
179 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
180 | * implementations to split any work between atomic (enable) and sleepable | |
181 | * (prepare) contexts. If enabling a clock requires code that might sleep, | |
182 | * this must be done in clk_prepare. Clock enable code that will never be | |
7ce3e8cc | 183 | * called in a sleepable context may be implemented in clk_enable. |
b2476490 MT |
184 | * |
185 | * Typically, drivers will call clk_prepare when a clock may be needed later | |
186 | * (eg. when a device is opened), and clk_enable when the clock is actually | |
187 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | |
188 | * called before clk_enable. | |
189 | */ | |
190 | struct clk_ops { | |
191 | int (*prepare)(struct clk_hw *hw); | |
192 | void (*unprepare)(struct clk_hw *hw); | |
3d6ee287 | 193 | int (*is_prepared)(struct clk_hw *hw); |
3cc8247f | 194 | void (*unprepare_unused)(struct clk_hw *hw); |
b2476490 MT |
195 | int (*enable)(struct clk_hw *hw); |
196 | void (*disable)(struct clk_hw *hw); | |
197 | int (*is_enabled)(struct clk_hw *hw); | |
7c045a55 | 198 | void (*disable_unused)(struct clk_hw *hw); |
b2476490 MT |
199 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
200 | unsigned long parent_rate); | |
54e73016 GU |
201 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
202 | unsigned long *parent_rate); | |
0817b62c BB |
203 | int (*determine_rate)(struct clk_hw *hw, |
204 | struct clk_rate_request *req); | |
b2476490 MT |
205 | int (*set_parent)(struct clk_hw *hw, u8 index); |
206 | u8 (*get_parent)(struct clk_hw *hw); | |
54e73016 GU |
207 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
208 | unsigned long parent_rate); | |
3fa2252b SB |
209 | int (*set_rate_and_parent)(struct clk_hw *hw, |
210 | unsigned long rate, | |
211 | unsigned long parent_rate, u8 index); | |
5279fc40 BB |
212 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
213 | unsigned long parent_accuracy); | |
9824cf73 | 214 | int (*get_phase)(struct clk_hw *hw); |
e59c5371 | 215 | int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490 | 216 | void (*init)(struct clk_hw *hw); |
c646cbf1 | 217 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490 MT |
218 | }; |
219 | ||
0197b3ea SK |
220 | /** |
221 | * struct clk_init_data - holds init data that's common to all clocks and is | |
222 | * shared between the clock provider and the common clock framework. | |
223 | * | |
224 | * @name: clock name | |
225 | * @ops: operations this clock supports | |
226 | * @parent_names: array of string names for all possible parents | |
227 | * @num_parents: number of possible parents | |
228 | * @flags: framework-level hints and quirks | |
229 | */ | |
230 | struct clk_init_data { | |
231 | const char *name; | |
232 | const struct clk_ops *ops; | |
2893c379 | 233 | const char * const *parent_names; |
0197b3ea SK |
234 | u8 num_parents; |
235 | unsigned long flags; | |
236 | }; | |
237 | ||
238 | /** | |
239 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | |
240 | * hardware-specific structure. struct clk_hw should be declared within struct | |
241 | * clk_foo and then referenced by the struct clk instance that uses struct | |
242 | * clk_foo's clk_ops | |
243 | * | |
035a61c3 TV |
244 | * @core: pointer to the struct clk_core instance that points back to this |
245 | * struct clk_hw instance | |
246 | * | |
247 | * @clk: pointer to the per-user struct clk instance that can be used to call | |
248 | * into the clk API | |
0197b3ea SK |
249 | * |
250 | * @init: pointer to struct clk_init_data that contains the init data shared | |
251 | * with the common clock framework. | |
252 | */ | |
253 | struct clk_hw { | |
035a61c3 | 254 | struct clk_core *core; |
0197b3ea | 255 | struct clk *clk; |
dc4cd941 | 256 | const struct clk_init_data *init; |
0197b3ea SK |
257 | }; |
258 | ||
9d9f78ed MT |
259 | /* |
260 | * DOC: Basic clock implementations common to many platforms | |
261 | * | |
262 | * Each basic clock hardware type is comprised of a structure describing the | |
263 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | |
264 | * unique flags for that hardware type, a registration function and an | |
265 | * alternative macro for static initialization | |
266 | */ | |
267 | ||
268 | /** | |
269 | * struct clk_fixed_rate - fixed-rate clock | |
270 | * @hw: handle between common and hardware-specific interfaces | |
271 | * @fixed_rate: constant frequency of clock | |
272 | */ | |
273 | struct clk_fixed_rate { | |
274 | struct clk_hw hw; | |
275 | unsigned long fixed_rate; | |
0903ea60 | 276 | unsigned long fixed_accuracy; |
9d9f78ed MT |
277 | u8 flags; |
278 | }; | |
279 | ||
5fd9c05c GT |
280 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
281 | ||
bffad66e | 282 | extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed MT |
283 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
284 | const char *parent_name, unsigned long flags, | |
285 | unsigned long fixed_rate); | |
26ef56be SB |
286 | struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, |
287 | const char *parent_name, unsigned long flags, | |
288 | unsigned long fixed_rate); | |
0903ea60 BB |
289 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
290 | const char *name, const char *parent_name, unsigned long flags, | |
291 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
0b225e41 | 292 | void clk_unregister_fixed_rate(struct clk *clk); |
26ef56be SB |
293 | struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, |
294 | const char *name, const char *parent_name, unsigned long flags, | |
295 | unsigned long fixed_rate, unsigned long fixed_accuracy); | |
296 | ||
015ba402 GL |
297 | void of_fixed_clk_setup(struct device_node *np); |
298 | ||
9d9f78ed MT |
299 | /** |
300 | * struct clk_gate - gating clock | |
301 | * | |
302 | * @hw: handle between common and hardware-specific interfaces | |
303 | * @reg: register controlling gate | |
304 | * @bit_idx: single bit controlling gate | |
305 | * @flags: hardware-specific flags | |
306 | * @lock: register lock | |
307 | * | |
308 | * Clock which can gate its output. Implements .enable & .disable | |
309 | * | |
310 | * Flags: | |
1f73f31a | 311 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b GU |
312 | * enable the clock. Setting this flag does the opposite: setting the bit |
313 | * disable the clock and clearing it enables the clock | |
04577994 | 314 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b GU |
315 | * of this register, and mask of gate bits are in higher 16-bit of this |
316 | * register. While setting the gate bits, higher 16-bit should also be | |
317 | * updated to indicate changing gate bits. | |
9d9f78ed MT |
318 | */ |
319 | struct clk_gate { | |
320 | struct clk_hw hw; | |
321 | void __iomem *reg; | |
322 | u8 bit_idx; | |
323 | u8 flags; | |
324 | spinlock_t *lock; | |
9d9f78ed MT |
325 | }; |
326 | ||
5fd9c05c GT |
327 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
328 | ||
9d9f78ed | 329 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
04577994 | 330 | #define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed | 331 | |
bffad66e | 332 | extern const struct clk_ops clk_gate_ops; |
9d9f78ed MT |
333 | struct clk *clk_register_gate(struct device *dev, const char *name, |
334 | const char *parent_name, unsigned long flags, | |
335 | void __iomem *reg, u8 bit_idx, | |
336 | u8 clk_gate_flags, spinlock_t *lock); | |
e270d8cb SB |
337 | struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, |
338 | const char *parent_name, unsigned long flags, | |
339 | void __iomem *reg, u8 bit_idx, | |
340 | u8 clk_gate_flags, spinlock_t *lock); | |
4e3c021f | 341 | void clk_unregister_gate(struct clk *clk); |
e270d8cb | 342 | void clk_hw_unregister_gate(struct clk_hw *hw); |
9d9f78ed | 343 | |
357c3f0a RN |
344 | struct clk_div_table { |
345 | unsigned int val; | |
346 | unsigned int div; | |
347 | }; | |
348 | ||
9d9f78ed MT |
349 | /** |
350 | * struct clk_divider - adjustable divider clock | |
351 | * | |
352 | * @hw: handle between common and hardware-specific interfaces | |
353 | * @reg: register containing the divider | |
354 | * @shift: shift to the divider bit field | |
355 | * @width: width of the divider bit field | |
357c3f0a | 356 | * @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed MT |
357 | * @lock: register lock |
358 | * | |
359 | * Clock with an adjustable divider affecting its output frequency. Implements | |
360 | * .recalc_rate, .set_rate and .round_rate | |
361 | * | |
362 | * Flags: | |
363 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | |
725b418b GU |
364 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
365 | * the raw value read from the register, with the value of zero considered | |
056b2053 | 366 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed | 367 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b | 368 | * the hardware register |
056b2053 SB |
369 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
370 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | |
371 | * Some hardware implementations gracefully handle this case and allow a | |
372 | * zero divisor by not modifying their input clock | |
373 | * (divide by one / bypass). | |
d57dfe75 | 374 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b GU |
375 | * of this register, and mask of divider bits are in higher 16-bit of this |
376 | * register. While setting the divider bits, higher 16-bit should also be | |
377 | * updated to indicate changing divider bits. | |
774b5143 MC |
378 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
379 | * to the closest integer instead of the up one. | |
79c6ab50 HS |
380 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
381 | * not be changed by the clock framework. | |
afe76c8f JQ |
382 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
383 | * except when the value read from the register is zero, the divisor is | |
384 | * 2^width of the field. | |
9d9f78ed MT |
385 | */ |
386 | struct clk_divider { | |
387 | struct clk_hw hw; | |
388 | void __iomem *reg; | |
389 | u8 shift; | |
390 | u8 width; | |
391 | u8 flags; | |
357c3f0a | 392 | const struct clk_div_table *table; |
9d9f78ed | 393 | spinlock_t *lock; |
9d9f78ed MT |
394 | }; |
395 | ||
5fd9c05c GT |
396 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
397 | ||
9d9f78ed MT |
398 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
399 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | |
056b2053 | 400 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe75 | 401 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b5143 | 402 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab50 | 403 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
afe76c8f | 404 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
9d9f78ed | 405 | |
bffad66e | 406 | extern const struct clk_ops clk_divider_ops; |
50359819 | 407 | extern const struct clk_ops clk_divider_ro_ops; |
bca9690b SB |
408 | |
409 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, | |
410 | unsigned int val, const struct clk_div_table *table, | |
411 | unsigned long flags); | |
412 | long divider_round_rate(struct clk_hw *hw, unsigned long rate, | |
413 | unsigned long *prate, const struct clk_div_table *table, | |
414 | u8 width, unsigned long flags); | |
415 | int divider_get_val(unsigned long rate, unsigned long parent_rate, | |
416 | const struct clk_div_table *table, u8 width, | |
417 | unsigned long flags); | |
418 | ||
9d9f78ed MT |
419 | struct clk *clk_register_divider(struct device *dev, const char *name, |
420 | const char *parent_name, unsigned long flags, | |
421 | void __iomem *reg, u8 shift, u8 width, | |
422 | u8 clk_divider_flags, spinlock_t *lock); | |
eb7d264f SB |
423 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
424 | const char *parent_name, unsigned long flags, | |
425 | void __iomem *reg, u8 shift, u8 width, | |
426 | u8 clk_divider_flags, spinlock_t *lock); | |
357c3f0a RN |
427 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
428 | const char *parent_name, unsigned long flags, | |
429 | void __iomem *reg, u8 shift, u8 width, | |
430 | u8 clk_divider_flags, const struct clk_div_table *table, | |
431 | spinlock_t *lock); | |
eb7d264f SB |
432 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
433 | const char *name, const char *parent_name, unsigned long flags, | |
434 | void __iomem *reg, u8 shift, u8 width, | |
435 | u8 clk_divider_flags, const struct clk_div_table *table, | |
436 | spinlock_t *lock); | |
4e3c021f | 437 | void clk_unregister_divider(struct clk *clk); |
eb7d264f | 438 | void clk_hw_unregister_divider(struct clk_hw *hw); |
9d9f78ed MT |
439 | |
440 | /** | |
441 | * struct clk_mux - multiplexer clock | |
442 | * | |
443 | * @hw: handle between common and hardware-specific interfaces | |
444 | * @reg: register controlling multiplexer | |
445 | * @shift: shift to multiplexer bit field | |
446 | * @width: width of mutliplexer bit field | |
3566d40c | 447 | * @flags: hardware-specific flags |
9d9f78ed MT |
448 | * @lock: register lock |
449 | * | |
450 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | |
451 | * and .recalc_rate | |
452 | * | |
453 | * Flags: | |
454 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | |
1f73f31a | 455 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e90 | 456 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b GU |
457 | * register, and mask of mux bits are in higher 16-bit of this register. |
458 | * While setting the mux bits, higher 16-bit should also be updated to | |
459 | * indicate changing mux bits. | |
15a02c1f SB |
460 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
461 | * frequency. | |
9d9f78ed MT |
462 | */ |
463 | struct clk_mux { | |
464 | struct clk_hw hw; | |
465 | void __iomem *reg; | |
ce4f3313 PDS |
466 | u32 *table; |
467 | u32 mask; | |
9d9f78ed | 468 | u8 shift; |
9d9f78ed MT |
469 | u8 flags; |
470 | spinlock_t *lock; | |
471 | }; | |
472 | ||
5fd9c05c GT |
473 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
474 | ||
9d9f78ed MT |
475 | #define CLK_MUX_INDEX_ONE BIT(0) |
476 | #define CLK_MUX_INDEX_BIT BIT(1) | |
ba492e90 | 477 | #define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f SB |
478 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
479 | #define CLK_MUX_ROUND_CLOSEST BIT(4) | |
9d9f78ed | 480 | |
bffad66e | 481 | extern const struct clk_ops clk_mux_ops; |
c57acd14 | 482 | extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313 | 483 | |
9d9f78ed | 484 | struct clk *clk_register_mux(struct device *dev, const char *name, |
2893c379 SH |
485 | const char * const *parent_names, u8 num_parents, |
486 | unsigned long flags, | |
9d9f78ed MT |
487 | void __iomem *reg, u8 shift, u8 width, |
488 | u8 clk_mux_flags, spinlock_t *lock); | |
264b3171 SB |
489 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
490 | const char * const *parent_names, u8 num_parents, | |
491 | unsigned long flags, | |
492 | void __iomem *reg, u8 shift, u8 width, | |
493 | u8 clk_mux_flags, spinlock_t *lock); | |
b2476490 | 494 | |
ce4f3313 | 495 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
2893c379 SH |
496 | const char * const *parent_names, u8 num_parents, |
497 | unsigned long flags, | |
ce4f3313 PDS |
498 | void __iomem *reg, u8 shift, u32 mask, |
499 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
264b3171 SB |
500 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
501 | const char * const *parent_names, u8 num_parents, | |
502 | unsigned long flags, | |
503 | void __iomem *reg, u8 shift, u32 mask, | |
504 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | |
ce4f3313 | 505 | |
4e3c021f | 506 | void clk_unregister_mux(struct clk *clk); |
264b3171 | 507 | void clk_hw_unregister_mux(struct clk_hw *hw); |
4e3c021f | 508 | |
79b16641 GC |
509 | void of_fixed_factor_clk_setup(struct device_node *node); |
510 | ||
f0948f59 SH |
511 | /** |
512 | * struct clk_fixed_factor - fixed multiplier and divider clock | |
513 | * | |
514 | * @hw: handle between common and hardware-specific interfaces | |
515 | * @mult: multiplier | |
516 | * @div: divider | |
517 | * | |
518 | * Clock with a fixed multiplier and divider. The output frequency is the | |
519 | * parent clock rate divided by div and multiplied by mult. | |
520 | * Implements .recalc_rate, .set_rate and .round_rate | |
521 | */ | |
522 | ||
523 | struct clk_fixed_factor { | |
524 | struct clk_hw hw; | |
525 | unsigned int mult; | |
526 | unsigned int div; | |
527 | }; | |
528 | ||
5fd9c05c GT |
529 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
530 | ||
3037e9ea | 531 | extern const struct clk_ops clk_fixed_factor_ops; |
f0948f59 SH |
532 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
533 | const char *parent_name, unsigned long flags, | |
534 | unsigned int mult, unsigned int div); | |
cbf9591f | 535 | void clk_unregister_fixed_factor(struct clk *clk); |
0759ac8a SB |
536 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
537 | const char *name, const char *parent_name, unsigned long flags, | |
538 | unsigned int mult, unsigned int div); | |
539 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); | |
f0948f59 | 540 | |
e2d0e90f HK |
541 | /** |
542 | * struct clk_fractional_divider - adjustable fractional divider clock | |
543 | * | |
544 | * @hw: handle between common and hardware-specific interfaces | |
545 | * @reg: register containing the divider | |
546 | * @mshift: shift to the numerator bit field | |
547 | * @mwidth: width of the numerator bit field | |
548 | * @nshift: shift to the denominator bit field | |
549 | * @nwidth: width of the denominator bit field | |
550 | * @lock: register lock | |
551 | * | |
552 | * Clock with adjustable fractional divider affecting its output frequency. | |
553 | */ | |
e2d0e90f HK |
554 | struct clk_fractional_divider { |
555 | struct clk_hw hw; | |
556 | void __iomem *reg; | |
557 | u8 mshift; | |
934e2536 | 558 | u8 mwidth; |
e2d0e90f HK |
559 | u32 mmask; |
560 | u8 nshift; | |
934e2536 | 561 | u8 nwidth; |
e2d0e90f HK |
562 | u32 nmask; |
563 | u8 flags; | |
564 | spinlock_t *lock; | |
565 | }; | |
566 | ||
5fd9c05c GT |
567 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
568 | ||
e2d0e90f HK |
569 | extern const struct clk_ops clk_fractional_divider_ops; |
570 | struct clk *clk_register_fractional_divider(struct device *dev, | |
571 | const char *name, const char *parent_name, unsigned long flags, | |
572 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
573 | u8 clk_divider_flags, spinlock_t *lock); | |
39b44cff SB |
574 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
575 | const char *name, const char *parent_name, unsigned long flags, | |
576 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, | |
577 | u8 clk_divider_flags, spinlock_t *lock); | |
578 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); | |
e2d0e90f | 579 | |
f2e0a532 MR |
580 | /** |
581 | * struct clk_multiplier - adjustable multiplier clock | |
582 | * | |
583 | * @hw: handle between common and hardware-specific interfaces | |
584 | * @reg: register containing the multiplier | |
585 | * @shift: shift to the multiplier bit field | |
586 | * @width: width of the multiplier bit field | |
587 | * @lock: register lock | |
588 | * | |
589 | * Clock with an adjustable multiplier affecting its output frequency. | |
590 | * Implements .recalc_rate, .set_rate and .round_rate | |
591 | * | |
592 | * Flags: | |
593 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read | |
594 | * from the register, with 0 being a valid value effectively | |
595 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is | |
596 | * set, then a null multiplier will be considered as a bypass, | |
597 | * leaving the parent rate unmodified. | |
598 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be | |
599 | * rounded to the closest integer instead of the down one. | |
600 | */ | |
601 | struct clk_multiplier { | |
602 | struct clk_hw hw; | |
603 | void __iomem *reg; | |
604 | u8 shift; | |
605 | u8 width; | |
606 | u8 flags; | |
607 | spinlock_t *lock; | |
608 | }; | |
609 | ||
5fd9c05c GT |
610 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
611 | ||
f2e0a532 MR |
612 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
613 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) | |
614 | ||
615 | extern const struct clk_ops clk_multiplier_ops; | |
616 | ||
ece70094 PG |
617 | /*** |
618 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | |
619 | * | |
620 | * @hw: handle between common and hardware-specific interfaces | |
d3a1c7be MT |
621 | * @mux_hw: handle between composite and hardware-specific mux clock |
622 | * @rate_hw: handle between composite and hardware-specific rate clock | |
623 | * @gate_hw: handle between composite and hardware-specific gate clock | |
ece70094 | 624 | * @mux_ops: clock ops for mux |
d3a1c7be | 625 | * @rate_ops: clock ops for rate |
ece70094 PG |
626 | * @gate_ops: clock ops for gate |
627 | */ | |
628 | struct clk_composite { | |
629 | struct clk_hw hw; | |
630 | struct clk_ops ops; | |
631 | ||
632 | struct clk_hw *mux_hw; | |
d3a1c7be | 633 | struct clk_hw *rate_hw; |
ece70094 PG |
634 | struct clk_hw *gate_hw; |
635 | ||
636 | const struct clk_ops *mux_ops; | |
d3a1c7be | 637 | const struct clk_ops *rate_ops; |
ece70094 PG |
638 | const struct clk_ops *gate_ops; |
639 | }; | |
640 | ||
5fd9c05c GT |
641 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
642 | ||
ece70094 | 643 | struct clk *clk_register_composite(struct device *dev, const char *name, |
2893c379 | 644 | const char * const *parent_names, int num_parents, |
ece70094 | 645 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be | 646 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094 PG |
647 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
648 | unsigned long flags); | |
92a39d90 | 649 | void clk_unregister_composite(struct clk *clk); |
49cb392d SB |
650 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
651 | const char * const *parent_names, int num_parents, | |
652 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | |
653 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, | |
654 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | |
655 | unsigned long flags); | |
656 | void clk_hw_unregister_composite(struct clk_hw *hw); | |
ece70094 | 657 | |
c873d14d JS |
658 | /*** |
659 | * struct clk_gpio_gate - gpio gated clock | |
660 | * | |
661 | * @hw: handle between common and hardware-specific interfaces | |
662 | * @gpiod: gpio descriptor | |
663 | * | |
664 | * Clock with a gpio control for enabling and disabling the parent clock. | |
665 | * Implements .enable, .disable and .is_enabled | |
666 | */ | |
667 | ||
668 | struct clk_gpio { | |
669 | struct clk_hw hw; | |
670 | struct gpio_desc *gpiod; | |
671 | }; | |
672 | ||
5fd9c05c GT |
673 | #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) |
674 | ||
c873d14d JS |
675 | extern const struct clk_ops clk_gpio_gate_ops; |
676 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, | |
820ad975 | 677 | const char *parent_name, unsigned gpio, bool active_low, |
c873d14d | 678 | unsigned long flags); |
b120743a SB |
679 | struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, |
680 | const char *parent_name, unsigned gpio, bool active_low, | |
681 | unsigned long flags); | |
682 | void clk_hw_unregister_gpio_gate(struct clk_hw *hw); | |
c873d14d | 683 | |
80eeb1f0 SS |
684 | /** |
685 | * struct clk_gpio_mux - gpio controlled clock multiplexer | |
686 | * | |
687 | * @hw: see struct clk_gpio | |
688 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer | |
689 | * | |
690 | * Clock with a gpio control for selecting the parent clock. | |
691 | * Implements .get_parent, .set_parent and .determine_rate | |
692 | */ | |
693 | ||
694 | extern const struct clk_ops clk_gpio_mux_ops; | |
695 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, | |
37bff2c1 | 696 | const char * const *parent_names, u8 num_parents, unsigned gpio, |
80eeb1f0 | 697 | bool active_low, unsigned long flags); |
b120743a SB |
698 | struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, |
699 | const char * const *parent_names, u8 num_parents, unsigned gpio, | |
700 | bool active_low, unsigned long flags); | |
701 | void clk_hw_unregister_gpio_mux(struct clk_hw *hw); | |
80eeb1f0 | 702 | |
b2476490 MT |
703 | /** |
704 | * clk_register - allocate a new clock, register it and return an opaque cookie | |
705 | * @dev: device that is registering this clock | |
b2476490 | 706 | * @hw: link to hardware-specific clock data |
b2476490 MT |
707 | * |
708 | * clk_register is the primary interface for populating the clock tree with new | |
709 | * clock nodes. It returns a pointer to the newly allocated struct clk which | |
710 | * cannot be dereferenced by driver code but may be used in conjuction with the | |
d1302a36 MT |
711 | * rest of the clock API. In the event of an error clk_register will return an |
712 | * error code; drivers must test for an error code after calling clk_register. | |
b2476490 | 713 | */ |
0197b3ea | 714 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a | 715 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490 | 716 | |
4143804c SB |
717 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
718 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); | |
719 | ||
1df5c939 | 720 | void clk_unregister(struct clk *clk); |
46c8773a | 721 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939 | 722 | |
4143804c SB |
723 | void clk_hw_unregister(struct clk_hw *hw); |
724 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); | |
725 | ||
b2476490 | 726 | /* helper functions */ |
b76281cb | 727 | const char *__clk_get_name(const struct clk *clk); |
e7df6f6e | 728 | const char *clk_hw_get_name(const struct clk_hw *hw); |
b2476490 | 729 | struct clk_hw *__clk_get_hw(struct clk *clk); |
e7df6f6e SB |
730 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
731 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); | |
732 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, | |
1a9c069c | 733 | unsigned int index); |
93874681 | 734 | unsigned int __clk_get_enable_count(struct clk *clk); |
e7df6f6e | 735 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
b2476490 | 736 | unsigned long __clk_get_flags(struct clk *clk); |
e7df6f6e SB |
737 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
738 | bool clk_hw_is_prepared(const struct clk_hw *hw); | |
be68bf88 | 739 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
2ac6b1f5 | 740 | bool __clk_is_enabled(struct clk *clk); |
b2476490 | 741 | struct clk *__clk_lookup(const char *name); |
0817b62c BB |
742 | int __clk_mux_determine_rate(struct clk_hw *hw, |
743 | struct clk_rate_request *req); | |
744 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); | |
745 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, | |
746 | struct clk_rate_request *req); | |
42c86547 | 747 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
9783c0d9 SB |
748 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
749 | unsigned long max_rate); | |
b2476490 | 750 | |
2e65d8bf JMC |
751 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
752 | { | |
753 | dst->clk = src->clk; | |
754 | dst->core = src->core; | |
755 | } | |
756 | ||
b2476490 MT |
757 | /* |
758 | * FIXME clock api without lock protection | |
759 | */ | |
1a9c069c | 760 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
b2476490 | 761 | |
766e6a4e GL |
762 | struct of_device_id; |
763 | ||
764 | typedef void (*of_clk_init_cb_t)(struct device_node *); | |
765 | ||
0b151deb SH |
766 | struct clk_onecell_data { |
767 | struct clk **clks; | |
768 | unsigned int clk_num; | |
769 | }; | |
770 | ||
0861e5b8 SB |
771 | struct clk_hw_onecell_data { |
772 | size_t num; | |
773 | struct clk_hw *hws[]; | |
774 | }; | |
775 | ||
819b4861 TK |
776 | extern struct of_device_id __clk_of_table; |
777 | ||
54196ccb | 778 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151deb SH |
779 | |
780 | #ifdef CONFIG_OF | |
766e6a4e GL |
781 | int of_clk_add_provider(struct device_node *np, |
782 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
783 | void *data), | |
784 | void *data); | |
0861e5b8 SB |
785 | int of_clk_add_hw_provider(struct device_node *np, |
786 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
787 | void *data), | |
788 | void *data); | |
766e6a4e GL |
789 | void of_clk_del_provider(struct device_node *np); |
790 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | |
791 | void *data); | |
0861e5b8 SB |
792 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
793 | void *data); | |
494bfec9 | 794 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
0861e5b8 SB |
795 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
796 | void *data); | |
929e7f3b | 797 | unsigned int of_clk_get_parent_count(struct device_node *np); |
2e61dfb3 DN |
798 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
799 | unsigned int size); | |
766e6a4e | 800 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
d56f8994 LJ |
801 | int of_clk_detect_critical(struct device_node *np, int index, |
802 | unsigned long *flags); | |
766e6a4e GL |
803 | void of_clk_init(const struct of_device_id *matches); |
804 | ||
0b151deb | 805 | #else /* !CONFIG_OF */ |
f2f6c255 | 806 | |
0b151deb SH |
807 | static inline int of_clk_add_provider(struct device_node *np, |
808 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | |
809 | void *data), | |
810 | void *data) | |
811 | { | |
812 | return 0; | |
813 | } | |
0861e5b8 SB |
814 | static inline int of_clk_add_hw_provider(struct device_node *np, |
815 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, | |
816 | void *data), | |
817 | void *data) | |
818 | { | |
819 | return 0; | |
820 | } | |
20dd882a | 821 | static inline void of_clk_del_provider(struct device_node *np) {} |
0b151deb SH |
822 | static inline struct clk *of_clk_src_simple_get( |
823 | struct of_phandle_args *clkspec, void *data) | |
824 | { | |
825 | return ERR_PTR(-ENOENT); | |
826 | } | |
0861e5b8 SB |
827 | static inline struct clk_hw * |
828 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) | |
829 | { | |
830 | return ERR_PTR(-ENOENT); | |
831 | } | |
0b151deb SH |
832 | static inline struct clk *of_clk_src_onecell_get( |
833 | struct of_phandle_args *clkspec, void *data) | |
834 | { | |
835 | return ERR_PTR(-ENOENT); | |
836 | } | |
0861e5b8 SB |
837 | static inline struct clk_hw * |
838 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) | |
839 | { | |
840 | return ERR_PTR(-ENOENT); | |
841 | } | |
679c51cf SB |
842 | static inline int of_clk_get_parent_count(struct device_node *np) |
843 | { | |
844 | return 0; | |
845 | } | |
846 | static inline int of_clk_parent_fill(struct device_node *np, | |
847 | const char **parents, unsigned int size) | |
848 | { | |
849 | return 0; | |
850 | } | |
0b151deb SH |
851 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
852 | int index) | |
853 | { | |
854 | return NULL; | |
855 | } | |
d56f8994 LJ |
856 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
857 | unsigned long *flags) | |
858 | { | |
859 | return 0; | |
860 | } | |
20dd882a | 861 | static inline void of_clk_init(const struct of_device_id *matches) {} |
0b151deb | 862 | #endif /* CONFIG_OF */ |
aa514ce3 GS |
863 | |
864 | /* | |
865 | * wrap access to peripherals in accessor routines | |
866 | * for improved portability across platforms | |
867 | */ | |
868 | ||
6d8cdb68 GS |
869 | #if IS_ENABLED(CONFIG_PPC) |
870 | ||
871 | static inline u32 clk_readl(u32 __iomem *reg) | |
872 | { | |
873 | return ioread32be(reg); | |
874 | } | |
875 | ||
876 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
877 | { | |
878 | iowrite32be(val, reg); | |
879 | } | |
880 | ||
881 | #else /* platform dependent I/O accessors */ | |
882 | ||
aa514ce3 GS |
883 | static inline u32 clk_readl(u32 __iomem *reg) |
884 | { | |
885 | return readl(reg); | |
886 | } | |
887 | ||
888 | static inline void clk_writel(u32 val, u32 __iomem *reg) | |
889 | { | |
890 | writel(val, reg); | |
891 | } | |
892 | ||
6d8cdb68 GS |
893 | #endif /* platform dependent I/O accessors */ |
894 | ||
fb2b3c9f | 895 | #ifdef CONFIG_DEBUG_FS |
61c7cddf | 896 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
fb2b3c9f PDS |
897 | void *data, const struct file_operations *fops); |
898 | #endif | |
899 | ||
b2476490 MT |
900 | #endif /* CONFIG_COMMON_CLK */ |
901 | #endif /* CLK_PROVIDER_H */ |