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1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #ifndef _LINUX_CORESIGHT_H | |
14 | #define _LINUX_CORESIGHT_H | |
15 | ||
16 | #include <linux/device.h> | |
ff63ec13 | 17 | #include <linux/sched.h> |
a06ae860 PP |
18 | |
19 | /* Peripheral id registers (0xFD0-0xFEC) */ | |
20 | #define CORESIGHT_PERIPHIDR4 0xfd0 | |
21 | #define CORESIGHT_PERIPHIDR5 0xfd4 | |
22 | #define CORESIGHT_PERIPHIDR6 0xfd8 | |
23 | #define CORESIGHT_PERIPHIDR7 0xfdC | |
24 | #define CORESIGHT_PERIPHIDR0 0xfe0 | |
25 | #define CORESIGHT_PERIPHIDR1 0xfe4 | |
26 | #define CORESIGHT_PERIPHIDR2 0xfe8 | |
27 | #define CORESIGHT_PERIPHIDR3 0xfeC | |
28 | /* Component id registers (0xFF0-0xFFC) */ | |
29 | #define CORESIGHT_COMPIDR0 0xff0 | |
30 | #define CORESIGHT_COMPIDR1 0xff4 | |
31 | #define CORESIGHT_COMPIDR2 0xff8 | |
32 | #define CORESIGHT_COMPIDR3 0xffC | |
33 | ||
34 | #define ETM_ARCH_V3_3 0x23 | |
35 | #define ETM_ARCH_V3_5 0x25 | |
36 | #define PFT_ARCH_V1_0 0x30 | |
37 | #define PFT_ARCH_V1_1 0x31 | |
38 | ||
39 | #define CORESIGHT_UNLOCK 0xc5acce55 | |
40 | ||
41 | extern struct bus_type coresight_bustype; | |
42 | ||
43 | enum coresight_dev_type { | |
44 | CORESIGHT_DEV_TYPE_NONE, | |
45 | CORESIGHT_DEV_TYPE_SINK, | |
46 | CORESIGHT_DEV_TYPE_LINK, | |
47 | CORESIGHT_DEV_TYPE_LINKSINK, | |
48 | CORESIGHT_DEV_TYPE_SOURCE, | |
49 | }; | |
50 | ||
51 | enum coresight_dev_subtype_sink { | |
52 | CORESIGHT_DEV_SUBTYPE_SINK_NONE, | |
53 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, | |
54 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, | |
55 | }; | |
56 | ||
57 | enum coresight_dev_subtype_link { | |
58 | CORESIGHT_DEV_SUBTYPE_LINK_NONE, | |
59 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, | |
60 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, | |
61 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, | |
62 | }; | |
63 | ||
64 | enum coresight_dev_subtype_source { | |
65 | CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, | |
66 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, | |
67 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, | |
68 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, | |
69 | }; | |
70 | ||
71 | /** | |
72 | * struct coresight_dev_subtype - further characterisation of a type | |
73 | * @sink_subtype: type of sink this component is, as defined | |
74 | by @coresight_dev_subtype_sink. | |
75 | * @link_subtype: type of link this component is, as defined | |
76 | by @coresight_dev_subtype_link. | |
77 | * @source_subtype: type of source this component is, as defined | |
78 | by @coresight_dev_subtype_source. | |
79 | */ | |
80 | struct coresight_dev_subtype { | |
81 | enum coresight_dev_subtype_sink sink_subtype; | |
82 | enum coresight_dev_subtype_link link_subtype; | |
83 | enum coresight_dev_subtype_source source_subtype; | |
84 | }; | |
85 | ||
86 | /** | |
87 | * struct coresight_platform_data - data harvested from the DT specification | |
88 | * @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs. | |
89 | * @name: name of the component as shown under sysfs. | |
90 | * @nr_inport: number of input ports for this component. | |
8ee885a9 | 91 | * @outports: list of remote endpoint port number. |
a06ae860 PP |
92 | * @child_names:name of all child components connected to this device. |
93 | * @child_ports:child component port number the current component is | |
94 | connected to. | |
95 | * @nr_outport: number of output ports for this component. | |
96 | * @clk: The clock this component is associated to. | |
97 | */ | |
98 | struct coresight_platform_data { | |
99 | int cpu; | |
100 | const char *name; | |
101 | int nr_inport; | |
102 | int *outports; | |
103 | const char **child_names; | |
104 | int *child_ports; | |
105 | int nr_outport; | |
106 | struct clk *clk; | |
107 | }; | |
108 | ||
109 | /** | |
110 | * struct coresight_desc - description of a component required from drivers | |
111 | * @type: as defined by @coresight_dev_type. | |
112 | * @subtype: as defined by @coresight_dev_subtype. | |
113 | * @ops: generic operations for this component, as defined | |
114 | by @coresight_ops. | |
115 | * @pdata: platform data collected from DT. | |
116 | * @dev: The device entity associated to this component. | |
8ee885a9 | 117 | * @groups: operations specific to this component. These will end up |
a06ae860 PP |
118 | in the component's sysfs sub-directory. |
119 | */ | |
120 | struct coresight_desc { | |
121 | enum coresight_dev_type type; | |
122 | struct coresight_dev_subtype subtype; | |
123 | const struct coresight_ops *ops; | |
124 | struct coresight_platform_data *pdata; | |
125 | struct device *dev; | |
126 | const struct attribute_group **groups; | |
127 | }; | |
128 | ||
129 | /** | |
130 | * struct coresight_connection - representation of a single connection | |
a06ae860 PP |
131 | * @outport: a connection's output port number. |
132 | * @chid_name: remote component's name. | |
133 | * @child_port: remote component's port number @output is connected to. | |
134 | * @child_dev: a @coresight_device representation of the component | |
135 | connected to @outport. | |
136 | */ | |
137 | struct coresight_connection { | |
138 | int outport; | |
139 | const char *child_name; | |
140 | int child_port; | |
141 | struct coresight_device *child_dev; | |
142 | }; | |
143 | ||
144 | /** | |
145 | * struct coresight_device - representation of a device as used by the framework | |
8ee885a9 | 146 | * @conns: array of coresight_connections associated to this component. |
a06ae860 PP |
147 | * @nr_inport: number of input port associated to this component. |
148 | * @nr_outport: number of output port associated to this component. | |
149 | * @type: as defined by @coresight_dev_type. | |
150 | * @subtype: as defined by @coresight_dev_subtype. | |
151 | * @ops: generic operations for this component, as defined | |
152 | by @coresight_ops. | |
153 | * @dev: The device entity associated to this component. | |
154 | * @refcnt: keep track of what is in use. | |
155 | * @path_link: link of current component into the path being enabled. | |
156 | * @orphan: true if the component has connections that haven't been linked. | |
157 | * @enable: 'true' if component is currently part of an active path. | |
158 | * @activated: 'true' only if a _sink_ has been activated. A sink can be | |
159 | activated but not yet enabled. Enabling for a _sink_ | |
160 | happens when a source has been selected for that it. | |
161 | */ | |
162 | struct coresight_device { | |
163 | struct coresight_connection *conns; | |
164 | int nr_inport; | |
165 | int nr_outport; | |
166 | enum coresight_dev_type type; | |
167 | struct coresight_dev_subtype subtype; | |
168 | const struct coresight_ops *ops; | |
169 | struct device dev; | |
170 | atomic_t *refcnt; | |
171 | struct list_head path_link; | |
172 | bool orphan; | |
173 | bool enable; /* true only if configured as part of a path */ | |
174 | bool activated; /* true only if a sink is part of a path */ | |
175 | }; | |
176 | ||
177 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) | |
178 | ||
179 | #define source_ops(csdev) csdev->ops->source_ops | |
180 | #define sink_ops(csdev) csdev->ops->sink_ops | |
181 | #define link_ops(csdev) csdev->ops->link_ops | |
182 | ||
a06ae860 PP |
183 | /** |
184 | * struct coresight_ops_sink - basic operations for a sink | |
185 | * Operations available for sinks | |
186 | * @enable: enables the sink. | |
187 | * @disable: disables the sink. | |
188 | */ | |
189 | struct coresight_ops_sink { | |
190 | int (*enable)(struct coresight_device *csdev); | |
191 | void (*disable)(struct coresight_device *csdev); | |
192 | }; | |
193 | ||
194 | /** | |
195 | * struct coresight_ops_link - basic operations for a link | |
196 | * Operations available for links. | |
197 | * @enable: enables flow between iport and oport. | |
198 | * @disable: disables flow between iport and oport. | |
199 | */ | |
200 | struct coresight_ops_link { | |
201 | int (*enable)(struct coresight_device *csdev, int iport, int oport); | |
202 | void (*disable)(struct coresight_device *csdev, int iport, int oport); | |
203 | }; | |
204 | ||
205 | /** | |
206 | * struct coresight_ops_source - basic operations for a source | |
207 | * Operations available for sources. | |
208 | * @trace_id: returns the value of the component's trace ID as known | |
209 | to the HW. | |
1d27ff5a | 210 | * @enable: enables tracing for a source. |
a06ae860 PP |
211 | * @disable: disables tracing for a source. |
212 | */ | |
213 | struct coresight_ops_source { | |
214 | int (*trace_id)(struct coresight_device *csdev); | |
215 | int (*enable)(struct coresight_device *csdev); | |
216 | void (*disable)(struct coresight_device *csdev); | |
217 | }; | |
218 | ||
219 | struct coresight_ops { | |
220 | const struct coresight_ops_sink *sink_ops; | |
221 | const struct coresight_ops_link *link_ops; | |
222 | const struct coresight_ops_source *source_ops; | |
223 | }; | |
224 | ||
225 | #ifdef CONFIG_CORESIGHT | |
226 | extern struct coresight_device * | |
227 | coresight_register(struct coresight_desc *desc); | |
228 | extern void coresight_unregister(struct coresight_device *csdev); | |
229 | extern int coresight_enable(struct coresight_device *csdev); | |
230 | extern void coresight_disable(struct coresight_device *csdev); | |
a06ae860 PP |
231 | extern int coresight_timeout(void __iomem *addr, u32 offset, |
232 | int position, int value); | |
a06ae860 PP |
233 | #else |
234 | static inline struct coresight_device * | |
235 | coresight_register(struct coresight_desc *desc) { return NULL; } | |
236 | static inline void coresight_unregister(struct coresight_device *csdev) {} | |
237 | static inline int | |
238 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } | |
239 | static inline void coresight_disable(struct coresight_device *csdev) {} | |
a06ae860 PP |
240 | static inline int coresight_timeout(void __iomem *addr, u32 offset, |
241 | int position, int value) { return 1; } | |
c61c4b5d MP |
242 | #endif |
243 | ||
a06ae860 | 244 | #ifdef CONFIG_OF |
c61c4b5d MP |
245 | extern struct coresight_platform_data *of_get_coresight_platform_data( |
246 | struct device *dev, struct device_node *node); | |
247 | #else | |
a06ae860 PP |
248 | static inline struct coresight_platform_data *of_get_coresight_platform_data( |
249 | struct device *dev, struct device_node *node) { return NULL; } | |
250 | #endif | |
a06ae860 | 251 | |
72210227 CZ |
252 | #ifdef CONFIG_PID_NS |
253 | static inline unsigned long | |
254 | coresight_vpid_to_pid(unsigned long vpid) | |
255 | { | |
256 | struct task_struct *task = NULL; | |
257 | unsigned long pid = 0; | |
258 | ||
259 | rcu_read_lock(); | |
260 | task = find_task_by_vpid(vpid); | |
261 | if (task) | |
262 | pid = task_pid_nr(task); | |
263 | rcu_read_unlock(); | |
264 | ||
265 | return pid; | |
266 | } | |
267 | #else | |
268 | static inline unsigned long | |
269 | coresight_vpid_to_pid(unsigned long vpid) { return vpid; } | |
270 | #endif | |
271 | ||
a06ae860 | 272 | #endif |