[deliverable/linux.git] / include / linux / coresight.h

/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _LINUX_CORESIGHT_H
#define _LINUX_CORESIGHT_H

#include <linux/device.h>
#include <linux/perf_event.h>
#include <linux/sched.h>

/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4	0xfd0
#define CORESIGHT_PERIPHIDR5	0xfd4
#define CORESIGHT_PERIPHIDR6	0xfd8
#define CORESIGHT_PERIPHIDR7	0xfdC
#define CORESIGHT_PERIPHIDR0	0xfe0
#define CORESIGHT_PERIPHIDR1	0xfe4
#define CORESIGHT_PERIPHIDR2	0xfe8
#define CORESIGHT_PERIPHIDR3	0xfeC
/* Component id registers (0xFF0-0xFFC) */
#define CORESIGHT_COMPIDR0	0xff0
#define CORESIGHT_COMPIDR1	0xff4
#define CORESIGHT_COMPIDR2	0xff8
#define CORESIGHT_COMPIDR3	0xffC

#define ETM_ARCH_V3_3		0x23
#define ETM_ARCH_V3_5		0x25
#define PFT_ARCH_V1_0		0x30
#define PFT_ARCH_V1_1		0x31

#define CORESIGHT_UNLOCK	0xc5acce55

extern struct bus_type coresight_bustype;

enum coresight_dev_type {
	CORESIGHT_DEV_TYPE_NONE,
	CORESIGHT_DEV_TYPE_SINK,
	CORESIGHT_DEV_TYPE_LINK,
	CORESIGHT_DEV_TYPE_LINKSINK,
	CORESIGHT_DEV_TYPE_SOURCE,
};

enum coresight_dev_subtype_sink {
	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
};

enum coresight_dev_subtype_link {
	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
};

enum coresight_dev_subtype_source {
	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
};

/**
 * struct coresight_dev_subtype - further characterisation of a type
 * @sink_subtype:	type of sink this component is, as defined
			by @coresight_dev_subtype_sink.
 * @link_subtype:	type of link this component is, as defined
			by @coresight_dev_subtype_link.
 * @source_subtype:	type of source this component is, as defined
			by @coresight_dev_subtype_source.
 */
struct coresight_dev_subtype {
	enum coresight_dev_subtype_sink sink_subtype;
	enum coresight_dev_subtype_link link_subtype;
	enum coresight_dev_subtype_source source_subtype;
};

/**
 * struct coresight_platform_data - data harvested from the DT specification
 * @cpu:	the CPU a source belongs to. Only applicable for ETM/PTMs.
 * @name:	name of the component as shown under sysfs.
 * @nr_inport:	number of input ports for this component.
 * @outports:	list of remote endpoint port number.
 * @child_names:name of all child components connected to this device.
 * @child_ports:child component port number the current component is
		connected  to.
 * @nr_outport:	number of output ports for this component.
 * @clk:	The clock this component is associated to.
 */
struct coresight_platform_data {
	int cpu;
	const char *name;
	int nr_inport;
	int *outports;
	const char **child_names;
	int *child_ports;
	int nr_outport;
	struct clk *clk;
};

/**
 * struct coresight_desc - description of a component required from drivers
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @pdata:	platform data collected from DT.
 * @dev:	The device entity associated to this component.
 * @groups:	operations specific to this component. These will end up
		in the component's sysfs sub-directory.
 */
struct coresight_desc {
	enum coresight_dev_type type;
	struct coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct coresight_platform_data *pdata;
	struct device *dev;
	const struct attribute_group **groups;
};

/**
 * struct coresight_connection - representation of a single connection
 * @outport:	a connection's output port number.
 * @chid_name:	remote component's name.
 * @child_port:	remote component's port number @output is connected to.
 * @child_dev:	a @coresight_device representation of the component
		connected to @outport.
 */
struct coresight_connection {
	int outport;
	const char *child_name;
	int child_port;
	struct coresight_device *child_dev;
};

/**
 * struct coresight_device - representation of a device as used by the framework
 * @conns:	array of coresight_connections associated to this component.
 * @nr_inport:	number of input port associated to this component.
 * @nr_outport:	number of output port associated to this component.
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @dev:	The device entity associated to this component.
 * @refcnt:	keep track of what is in use.
 * @orphan:	true if the component has connections that haven't been linked.
 * @enable:	'true' if component is currently part of an active path.
 * @activated:	'true' only if a _sink_ has been activated.  A sink can be
		activated but not yet enabled.  Enabling for a _sink_
		happens when a source has been selected for that it.
 */
struct coresight_device {
	struct coresight_connection *conns;
	int nr_inport;
	int nr_outport;
	enum coresight_dev_type type;
	struct coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct device dev;
	atomic_t *refcnt;
	bool orphan;
	bool enable;	/* true only if configured as part of a path */
	bool activated;	/* true only if a sink is part of a path */
};

#define to_coresight_device(d) container_of(d, struct coresight_device, dev)

#define source_ops(csdev)	csdev->ops->source_ops
#define sink_ops(csdev)		csdev->ops->sink_ops
#define link_ops(csdev)		csdev->ops->link_ops

/**
 * struct coresight_ops_sink - basic operations for a sink
 * Operations available for sinks
 * @enable:	enables the sink.
 * @disable:	disables the sink.
 */
struct coresight_ops_sink {
	int (*enable)(struct coresight_device *csdev);
	void (*disable)(struct coresight_device *csdev);
};

/**
 * struct coresight_ops_link - basic operations for a link
 * Operations available for links.
 * @enable:	enables flow between iport and oport.
 * @disable:	disables flow between iport and oport.
 */
struct coresight_ops_link {
	int (*enable)(struct coresight_device *csdev, int iport, int oport);
	void (*disable)(struct coresight_device *csdev, int iport, int oport);
};

/**
 * struct coresight_ops_source - basic operations for a source
 * Operations available for sources.
 * @cpu_id:	returns the value of the CPU number this component
 *		is associated to.
 * @trace_id:	returns the value of the component's trace ID as known
 *		to the HW.
 * @enable:	enables tracing for a source.
 * @disable:	disables tracing for a source.
 */
struct coresight_ops_source {
	int (*cpu_id)(struct coresight_device *csdev);
	int (*trace_id)(struct coresight_device *csdev);
	int (*enable)(struct coresight_device *csdev,
		      struct perf_event_attr *attr,  u32 mode);
	void (*disable)(struct coresight_device *csdev);
};

struct coresight_ops {
	const struct coresight_ops_sink *sink_ops;
	const struct coresight_ops_link *link_ops;
	const struct coresight_ops_source *source_ops;
};

#ifdef CONFIG_CORESIGHT
extern struct coresight_device *
coresight_register(struct coresight_desc *desc);
extern void coresight_unregister(struct coresight_device *csdev);
extern int coresight_enable(struct coresight_device *csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
			     int position, int value);
#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
static inline void coresight_unregister(struct coresight_device *csdev) {}
static inline int
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
static inline void coresight_disable(struct coresight_device *csdev) {}
static inline int coresight_timeout(void __iomem *addr, u32 offset,
				     int position, int value) { return 1; }
#endif

#ifdef CONFIG_OF
extern struct coresight_platform_data *of_get_coresight_platform_data(
				struct device *dev, struct device_node *node);
#else
static inline struct coresight_platform_data *of_get_coresight_platform_data(
	struct device *dev, struct device_node *node) { return NULL; }
#endif

#ifdef CONFIG_PID_NS
static inline unsigned long
coresight_vpid_to_pid(unsigned long vpid)
{
	struct task_struct *task = NULL;
	unsigned long pid = 0;

	rcu_read_lock();
	task = find_task_by_vpid(vpid);
	if (task)
		pid = task_pid_nr(task);
	rcu_read_unlock();

	return pid;
}
#else
static inline unsigned long
coresight_vpid_to_pid(unsigned long vpid) { return vpid; }
#endif

#endif
Commit	Line	Data
a06ae860 PP	1	/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*/
	12
	13	#ifndef _LINUX_CORESIGHT_H
	14	#define _LINUX_CORESIGHT_H
	15
	16	#include <linux/device.h>
882d5e11	17	#include <linux/perf_event.h>
ff63ec13	18	#include <linux/sched.h>
a06ae860 PP	19
	20	/* Peripheral id registers (0xFD0-0xFEC) */
	21	#define CORESIGHT_PERIPHIDR4 0xfd0
	22	#define CORESIGHT_PERIPHIDR5 0xfd4
	23	#define CORESIGHT_PERIPHIDR6 0xfd8
	24	#define CORESIGHT_PERIPHIDR7 0xfdC
	25	#define CORESIGHT_PERIPHIDR0 0xfe0
	26	#define CORESIGHT_PERIPHIDR1 0xfe4
	27	#define CORESIGHT_PERIPHIDR2 0xfe8
	28	#define CORESIGHT_PERIPHIDR3 0xfeC
	29	/* Component id registers (0xFF0-0xFFC) */
	30	#define CORESIGHT_COMPIDR0 0xff0
	31	#define CORESIGHT_COMPIDR1 0xff4
	32	#define CORESIGHT_COMPIDR2 0xff8
	33	#define CORESIGHT_COMPIDR3 0xffC
	34
	35	#define ETM_ARCH_V3_3 0x23
	36	#define ETM_ARCH_V3_5 0x25
	37	#define PFT_ARCH_V1_0 0x30
	38	#define PFT_ARCH_V1_1 0x31
	39
	40	#define CORESIGHT_UNLOCK 0xc5acce55
	41
	42	extern struct bus_type coresight_bustype;
	43
	44	enum coresight_dev_type {
	45	CORESIGHT_DEV_TYPE_NONE,
	46	CORESIGHT_DEV_TYPE_SINK,
	47	CORESIGHT_DEV_TYPE_LINK,
	48	CORESIGHT_DEV_TYPE_LINKSINK,
	49	CORESIGHT_DEV_TYPE_SOURCE,
	50	};
	51
	52	enum coresight_dev_subtype_sink {
	53	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	54	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	55	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
	56	};
	57
	58	enum coresight_dev_subtype_link {
	59	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	60	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	61	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	62	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
	63	};
	64
	65	enum coresight_dev_subtype_source {
	66	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	67	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	68	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	69	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
	70	};
	71
	72	/**
	73	* struct coresight_dev_subtype - further characterisation of a type
	74	* @sink_subtype: type of sink this component is, as defined
	75	by @coresight_dev_subtype_sink.
	76	* @link_subtype: type of link this component is, as defined
	77	by @coresight_dev_subtype_link.
	78	* @source_subtype: type of source this component is, as defined
	79	by @coresight_dev_subtype_source.
	80	*/
	81	struct coresight_dev_subtype {
	82	enum coresight_dev_subtype_sink sink_subtype;
83	enum coresight_dev_subtype_link link_subtype;
84	enum coresight_dev_subtype_source source_subtype;
85	};
86
87	/**
88	* struct coresight_platform_data - data harvested from the DT specification
89	* @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs.
90	* @name: name of the component as shown under sysfs.
91	* @nr_inport: number of input ports for this component.
8ee885a9	92	* @outports: list of remote endpoint port number.
a06ae860 PP	93	* @child_names:name of all child components connected to this device.
	94	* @child_ports:child component port number the current component is
	95	connected to.
	96	* @nr_outport: number of output ports for this component.
	97	* @clk: The clock this component is associated to.
	98	*/
	99	struct coresight_platform_data {
	100	int cpu;
	101	const char *name;
	102	int nr_inport;
	103	int *outports;
	104	const char **child_names;
	105	int *child_ports;
	106	int nr_outport;
	107	struct clk *clk;
	108	};
	109
	110	/**
	111	* struct coresight_desc - description of a component required from drivers
	112	* @type: as defined by @coresight_dev_type.
	113	* @subtype: as defined by @coresight_dev_subtype.
	114	* @ops: generic operations for this component, as defined
	115	by @coresight_ops.
	116	* @pdata: platform data collected from DT.
	117	* @dev: The device entity associated to this component.
8ee885a9	118	* @groups: operations specific to this component. These will end up
a06ae860 PP	119	in the component's sysfs sub-directory.
	120	*/
	121	struct coresight_desc {
	122	enum coresight_dev_type type;
	123	struct coresight_dev_subtype subtype;
	124	const struct coresight_ops *ops;
	125	struct coresight_platform_data *pdata;
	126	struct device *dev;
	127	const struct attribute_group **groups;
	128	};
	129
	130	/**
	131	* struct coresight_connection - representation of a single connection
a06ae860 PP	132	* @outport: a connection's output port number.
	133	* @chid_name: remote component's name.
	134	* @child_port: remote component's port number @output is connected to.
	135	* @child_dev: a @coresight_device representation of the component
	136	connected to @outport.
	137	*/
	138	struct coresight_connection {
	139	int outport;
	140	const char *child_name;
	141	int child_port;
	142	struct coresight_device *child_dev;
	143	};
	144
	145	/**
	146	* struct coresight_device - representation of a device as used by the framework
8ee885a9	147	* @conns: array of coresight_connections associated to this component.
a06ae860 PP	148	* @nr_inport: number of input port associated to this component.
	149	* @nr_outport: number of output port associated to this component.
	150	* @type: as defined by @coresight_dev_type.
	151	* @subtype: as defined by @coresight_dev_subtype.
	152	* @ops: generic operations for this component, as defined
	153	by @coresight_ops.
	154	* @dev: The device entity associated to this component.
	155	* @refcnt: keep track of what is in use.
a06ae860 PP	156	* @orphan: true if the component has connections that haven't been linked.
	157	* @enable: 'true' if component is currently part of an active path.
	158	* @activated: 'true' only if a _sink_ has been activated. A sink can be
	159	activated but not yet enabled. Enabling for a _sink_
	160	happens when a source has been selected for that it.
	161	*/
	162	struct coresight_device {
	163	struct coresight_connection *conns;
	164	int nr_inport;
	165	int nr_outport;
	166	enum coresight_dev_type type;
	167	struct coresight_dev_subtype subtype;
	168	const struct coresight_ops *ops;
	169	struct device dev;
	170	atomic_t *refcnt;
a06ae860 PP	171	bool orphan;
	172	bool enable; /* true only if configured as part of a path */
	173	bool activated; /* true only if a sink is part of a path */
	174	};
	175
	176	#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
	177
	178	#define source_ops(csdev) csdev->ops->source_ops
	179	#define sink_ops(csdev) csdev->ops->sink_ops
	180	#define link_ops(csdev) csdev->ops->link_ops
	181
a06ae860 PP	182	/**
	183	* struct coresight_ops_sink - basic operations for a sink
	184	* Operations available for sinks
	185	* @enable: enables the sink.
	186	* @disable: disables the sink.
	187	*/
	188	struct coresight_ops_sink {
	189	int (enable)(struct coresight_device csdev);
	190	void (disable)(struct coresight_device csdev);
	191	};
	192
	193	/**
	194	* struct coresight_ops_link - basic operations for a link
	195	* Operations available for links.
	196	* @enable: enables flow between iport and oport.
	197	* @disable: disables flow between iport and oport.
	198	*/
	199	struct coresight_ops_link {
	200	int (enable)(struct coresight_device csdev, int iport, int oport);
	201	void (disable)(struct coresight_device csdev, int iport, int oport);
	202	};
	203
	204	/**
	205	* struct coresight_ops_source - basic operations for a source
	206	* Operations available for sources.
52210c87 MP	207	* @cpu_id: returns the value of the CPU number this component
52210c87 MP	208	* is associated to.
a06ae860	209	* @trace_id: returns the value of the component's trace ID as known
882d5e11	210	* to the HW.
1d27ff5a	211	* @enable: enables tracing for a source.
a06ae860 PP	212	* @disable: disables tracing for a source.
	213	*/
	214	struct coresight_ops_source {
52210c87	215	int (cpu_id)(struct coresight_device csdev);
a06ae860	216	int (trace_id)(struct coresight_device csdev);
882d5e11 MP	217	int (enable)(struct coresight_device csdev,
882d5e11 MP	218	struct perf_event_attr *attr, u32 mode);
a06ae860 PP	219	void (disable)(struct coresight_device csdev);
	220	};
	221
	222	struct coresight_ops {
	223	const struct coresight_ops_sink *sink_ops;
	224	const struct coresight_ops_link *link_ops;
	225	const struct coresight_ops_source *source_ops;
	226	};
	227
	228	#ifdef CONFIG_CORESIGHT
	229	extern struct coresight_device *
	230	coresight_register(struct coresight_desc *desc);
	231	extern void coresight_unregister(struct coresight_device *csdev);
	232	extern int coresight_enable(struct coresight_device *csdev);
	233	extern void coresight_disable(struct coresight_device *csdev);
a06ae860 PP	234	extern int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	235	int position, int value);
a06ae860 PP	236	#else
	237	static inline struct coresight_device *
	238	coresight_register(struct coresight_desc *desc) { return NULL; }
	239	static inline void coresight_unregister(struct coresight_device *csdev) {}
	240	static inline int
	241	coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
	242	static inline void coresight_disable(struct coresight_device *csdev) {}
a06ae860 PP	243	static inline int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	244	int position, int value) { return 1; }
c61c4b5d MP	245	#endif
c61c4b5d MP	246
a06ae860	247	#ifdef CONFIG_OF
c61c4b5d MP	248	extern struct coresight_platform_data *of_get_coresight_platform_data(
	249	struct device dev, struct device_node node);
	250	#else
a06ae860 PP	251	static inline struct coresight_platform_data *of_get_coresight_platform_data(
	252	struct device dev, struct device_node node) { return NULL; }
	253	#endif
a06ae860	254
72210227 CZ	255	#ifdef CONFIG_PID_NS
	256	static inline unsigned long
	257	coresight_vpid_to_pid(unsigned long vpid)
	258	{
	259	struct task_struct *task = NULL;
	260	unsigned long pid = 0;
	261
	262	rcu_read_lock();
	263	task = find_task_by_vpid(vpid);
	264	if (task)
	265	pid = task_pid_nr(task);
	266	rcu_read_unlock();
	267
	268	return pid;
	269	}
	270	#else
	271	static inline unsigned long
	272	coresight_vpid_to_pid(unsigned long vpid) { return vpid; }
	273	#endif
	274
a06ae860	275	#endif