Commit | Line | Data |
---|---|---|
96532bab RD |
1 | #ifndef _LINUX_DMA_MAPPING_H |
2 | #define _LINUX_DMA_MAPPING_H | |
1da177e4 | 3 | |
842fa69f | 4 | #include <linux/string.h> |
1da177e4 LT |
5 | #include <linux/device.h> |
6 | #include <linux/err.h> | |
f0402a26 | 7 | #include <linux/dma-attrs.h> |
b7f080cf | 8 | #include <linux/dma-direction.h> |
f0402a26 | 9 | #include <linux/scatterlist.h> |
1da177e4 | 10 | |
f0402a26 FT |
11 | struct dma_map_ops { |
12 | void* (*alloc_coherent)(struct device *dev, size_t size, | |
13 | dma_addr_t *dma_handle, gfp_t gfp); | |
14 | void (*free_coherent)(struct device *dev, size_t size, | |
15 | void *vaddr, dma_addr_t dma_handle); | |
16 | dma_addr_t (*map_page)(struct device *dev, struct page *page, | |
17 | unsigned long offset, size_t size, | |
18 | enum dma_data_direction dir, | |
19 | struct dma_attrs *attrs); | |
20 | void (*unmap_page)(struct device *dev, dma_addr_t dma_handle, | |
21 | size_t size, enum dma_data_direction dir, | |
22 | struct dma_attrs *attrs); | |
23 | int (*map_sg)(struct device *dev, struct scatterlist *sg, | |
24 | int nents, enum dma_data_direction dir, | |
25 | struct dma_attrs *attrs); | |
26 | void (*unmap_sg)(struct device *dev, | |
27 | struct scatterlist *sg, int nents, | |
28 | enum dma_data_direction dir, | |
29 | struct dma_attrs *attrs); | |
30 | void (*sync_single_for_cpu)(struct device *dev, | |
31 | dma_addr_t dma_handle, size_t size, | |
32 | enum dma_data_direction dir); | |
33 | void (*sync_single_for_device)(struct device *dev, | |
34 | dma_addr_t dma_handle, size_t size, | |
35 | enum dma_data_direction dir); | |
f0402a26 FT |
36 | void (*sync_sg_for_cpu)(struct device *dev, |
37 | struct scatterlist *sg, int nents, | |
38 | enum dma_data_direction dir); | |
39 | void (*sync_sg_for_device)(struct device *dev, | |
40 | struct scatterlist *sg, int nents, | |
41 | enum dma_data_direction dir); | |
42 | int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); | |
43 | int (*dma_supported)(struct device *dev, u64 mask); | |
f726f30e | 44 | int (*set_dma_mask)(struct device *dev, u64 mask); |
f0402a26 FT |
45 | int is_phys; |
46 | }; | |
47 | ||
8f286c33 | 48 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
34c65384 | 49 | |
32e8f702 JB |
50 | #define DMA_MASK_NONE 0x0ULL |
51 | ||
d6bd3a39 REB |
52 | static inline int valid_dma_direction(int dma_direction) |
53 | { | |
54 | return ((dma_direction == DMA_BIDIRECTIONAL) || | |
55 | (dma_direction == DMA_TO_DEVICE) || | |
56 | (dma_direction == DMA_FROM_DEVICE)); | |
57 | } | |
58 | ||
32e8f702 JB |
59 | static inline int is_device_dma_capable(struct device *dev) |
60 | { | |
61 | return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE; | |
62 | } | |
63 | ||
1b0fac45 | 64 | #ifdef CONFIG_HAS_DMA |
1da177e4 | 65 | #include <asm/dma-mapping.h> |
1b0fac45 DW |
66 | #else |
67 | #include <asm-generic/dma-mapping-broken.h> | |
68 | #endif | |
1da177e4 | 69 | |
589fc9a6 FT |
70 | static inline u64 dma_get_mask(struct device *dev) |
71 | { | |
07a2c01a | 72 | if (dev && dev->dma_mask && *dev->dma_mask) |
589fc9a6 | 73 | return *dev->dma_mask; |
284901a9 | 74 | return DMA_BIT_MASK(32); |
589fc9a6 FT |
75 | } |
76 | ||
710224fa FT |
77 | #ifdef ARCH_HAS_DMA_SET_COHERENT_MASK |
78 | int dma_set_coherent_mask(struct device *dev, u64 mask); | |
79 | #else | |
6a1961f4 FT |
80 | static inline int dma_set_coherent_mask(struct device *dev, u64 mask) |
81 | { | |
82 | if (!dma_supported(dev, mask)) | |
83 | return -EIO; | |
84 | dev->coherent_dma_mask = mask; | |
85 | return 0; | |
86 | } | |
710224fa | 87 | #endif |
6a1961f4 | 88 | |
1da177e4 LT |
89 | extern u64 dma_get_required_mask(struct device *dev); |
90 | ||
6b7b6510 FT |
91 | static inline unsigned int dma_get_max_seg_size(struct device *dev) |
92 | { | |
93 | return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536; | |
94 | } | |
95 | ||
96 | static inline unsigned int dma_set_max_seg_size(struct device *dev, | |
97 | unsigned int size) | |
98 | { | |
99 | if (dev->dma_parms) { | |
100 | dev->dma_parms->max_segment_size = size; | |
101 | return 0; | |
102 | } else | |
103 | return -EIO; | |
104 | } | |
105 | ||
d22a6966 FT |
106 | static inline unsigned long dma_get_seg_boundary(struct device *dev) |
107 | { | |
108 | return dev->dma_parms ? | |
109 | dev->dma_parms->segment_boundary_mask : 0xffffffff; | |
110 | } | |
111 | ||
112 | static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) | |
113 | { | |
114 | if (dev->dma_parms) { | |
115 | dev->dma_parms->segment_boundary_mask = mask; | |
116 | return 0; | |
117 | } else | |
118 | return -EIO; | |
119 | } | |
120 | ||
842fa69f AM |
121 | static inline void *dma_zalloc_coherent(struct device *dev, size_t size, |
122 | dma_addr_t *dma_handle, gfp_t flag) | |
123 | { | |
124 | void *ret = dma_alloc_coherent(dev, size, dma_handle, flag); | |
125 | if (ret) | |
126 | memset(ret, 0, size); | |
127 | return ret; | |
128 | } | |
129 | ||
e259f191 | 130 | #ifdef CONFIG_HAS_DMA |
4565f017 FT |
131 | static inline int dma_get_cache_alignment(void) |
132 | { | |
133 | #ifdef ARCH_DMA_MINALIGN | |
134 | return ARCH_DMA_MINALIGN; | |
135 | #endif | |
136 | return 1; | |
137 | } | |
e259f191 | 138 | #endif |
4565f017 | 139 | |
1da177e4 LT |
140 | /* flags for the coherent memory api */ |
141 | #define DMA_MEMORY_MAP 0x01 | |
142 | #define DMA_MEMORY_IO 0x02 | |
143 | #define DMA_MEMORY_INCLUDES_CHILDREN 0x04 | |
144 | #define DMA_MEMORY_EXCLUSIVE 0x08 | |
145 | ||
146 | #ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY | |
147 | static inline int | |
148 | dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, | |
149 | dma_addr_t device_addr, size_t size, int flags) | |
150 | { | |
151 | return 0; | |
152 | } | |
153 | ||
154 | static inline void | |
155 | dma_release_declared_memory(struct device *dev) | |
156 | { | |
157 | } | |
158 | ||
159 | static inline void * | |
160 | dma_mark_declared_memory_occupied(struct device *dev, | |
161 | dma_addr_t device_addr, size_t size) | |
162 | { | |
163 | return ERR_PTR(-EBUSY); | |
164 | } | |
165 | #endif | |
166 | ||
9ac7849e TH |
167 | /* |
168 | * Managed DMA API | |
169 | */ | |
170 | extern void *dmam_alloc_coherent(struct device *dev, size_t size, | |
171 | dma_addr_t *dma_handle, gfp_t gfp); | |
172 | extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, | |
173 | dma_addr_t dma_handle); | |
174 | extern void *dmam_alloc_noncoherent(struct device *dev, size_t size, | |
175 | dma_addr_t *dma_handle, gfp_t gfp); | |
176 | extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr, | |
177 | dma_addr_t dma_handle); | |
178 | #ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY | |
179 | extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, | |
180 | dma_addr_t device_addr, size_t size, | |
181 | int flags); | |
182 | extern void dmam_release_declared_memory(struct device *dev); | |
183 | #else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */ | |
184 | static inline int dmam_declare_coherent_memory(struct device *dev, | |
185 | dma_addr_t bus_addr, dma_addr_t device_addr, | |
186 | size_t size, gfp_t gfp) | |
187 | { | |
188 | return 0; | |
189 | } | |
1da177e4 | 190 | |
9ac7849e TH |
191 | static inline void dmam_release_declared_memory(struct device *dev) |
192 | { | |
193 | } | |
194 | #endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */ | |
1da177e4 | 195 | |
74bc7cee AK |
196 | #ifndef CONFIG_HAVE_DMA_ATTRS |
197 | struct dma_attrs; | |
198 | ||
199 | #define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \ | |
200 | dma_map_single(dev, cpu_addr, size, dir) | |
201 | ||
202 | #define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \ | |
203 | dma_unmap_single(dev, dma_addr, size, dir) | |
204 | ||
205 | #define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \ | |
206 | dma_map_sg(dev, sgl, nents, dir) | |
207 | ||
208 | #define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \ | |
209 | dma_unmap_sg(dev, sgl, nents, dir) | |
210 | ||
211 | #endif /* CONFIG_HAVE_DMA_ATTRS */ | |
212 | ||
0acedc12 FT |
213 | #ifdef CONFIG_NEED_DMA_MAP_STATE |
214 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME | |
215 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME | |
216 | #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) | |
217 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) | |
218 | #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) | |
219 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) | |
220 | #else | |
221 | #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) | |
222 | #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) | |
223 | #define dma_unmap_addr(PTR, ADDR_NAME) (0) | |
224 | #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
225 | #define dma_unmap_len(PTR, LEN_NAME) (0) | |
226 | #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
227 | #endif | |
228 | ||
9ac7849e | 229 | #endif |