Commit | Line | Data |
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e61d98d8 SS |
1 | #ifndef _DMA_REMAPPING_H |
2 | #define _DMA_REMAPPING_H | |
3 | ||
4 | /* | |
5b6985ce | 5 | * VT-d hardware uses 4KiB page size regardless of host page size. |
e61d98d8 | 6 | */ |
5b6985ce FY |
7 | #define VTD_PAGE_SHIFT (12) |
8 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) | |
9 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) | |
10 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) | |
e61d98d8 | 11 | |
6dd9a7c7 YS |
12 | #define VTD_STRIDE_SHIFT (9) |
13 | #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) | |
14 | ||
e61d98d8 SS |
15 | #define DMA_PTE_READ (1) |
16 | #define DMA_PTE_WRITE (2) | |
6dd9a7c7 | 17 | #define DMA_PTE_LARGE_PAGE (1 << 7) |
9cf06697 | 18 | #define DMA_PTE_SNP (1 << 11) |
e61d98d8 | 19 | |
4ed0d3e6 | 20 | #define CONTEXT_TT_MULTI_LEVEL 0 |
93a23a72 | 21 | #define CONTEXT_TT_DEV_IOTLB 1 |
4ed0d3e6 | 22 | #define CONTEXT_TT_PASS_THROUGH 2 |
2f26e0a9 DW |
23 | /* Extended context entry types */ |
24 | #define CONTEXT_TT_PT_PASID 4 | |
25 | #define CONTEXT_TT_PT_PASID_DEV_IOTLB 5 | |
26 | #define CONTEXT_TT_MASK (7ULL << 2) | |
27 | ||
907fea34 | 28 | #define CONTEXT_DINVE (1ULL << 8) |
2f26e0a9 DW |
29 | #define CONTEXT_PRS (1ULL << 9) |
30 | #define CONTEXT_PASIDE (1ULL << 11) | |
4ed0d3e6 | 31 | |
e61d98d8 | 32 | struct intel_iommu; |
99126f7c MM |
33 | struct dmar_domain; |
34 | struct root_entry; | |
e61d98d8 | 35 | |
c66b9906 | 36 | |
d3f13810 | 37 | #ifdef CONFIG_INTEL_IOMMU |
1b573683 | 38 | extern int iommu_calculate_agaw(struct intel_iommu *iommu); |
4ed0d3e6 | 39 | extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu); |
f5d1b97b | 40 | extern int dmar_disabled; |
8bc1f85c | 41 | extern int intel_iommu_enabled; |
c66b9906 IM |
42 | #else |
43 | static inline int iommu_calculate_agaw(struct intel_iommu *iommu) | |
44 | { | |
45 | return 0; | |
46 | } | |
4ed0d3e6 FY |
47 | static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
48 | { | |
49 | return 0; | |
50 | } | |
f5d1b97b | 51 | #define dmar_disabled (1) |
8bc1f85c | 52 | #define intel_iommu_enabled (0) |
c66b9906 | 53 | #endif |
e61d98d8 | 54 | |
2ae21010 | 55 | |
e61d98d8 | 56 | #endif |