Commit | Line | Data |
---|---|---|
c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
d2ebfb33 RKAL |
21 | #ifndef LINUX_DMAENGINE_H |
22 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 | 24 | #include <linux/device.h> |
0ad7c000 | 25 | #include <linux/err.h> |
c13c8260 | 26 | #include <linux/uio.h> |
187f1882 | 27 | #include <linux/bug.h> |
90b44f8f | 28 | #include <linux/scatterlist.h> |
a8efa9d6 | 29 | #include <linux/bitmap.h> |
dcc043dc | 30 | #include <linux/types.h> |
a8efa9d6 | 31 | #include <asm/page.h> |
b7f080cf | 32 | |
c13c8260 | 33 | /** |
fe4ada2d | 34 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
35 | * |
36 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
37 | */ | |
38 | typedef s32 dma_cookie_t; | |
76bd061f SM |
39 | #define DMA_MIN_COOKIE 1 |
40 | #define DMA_MAX_COOKIE INT_MAX | |
c13c8260 | 41 | |
71ea1483 DC |
42 | static inline int dma_submit_error(dma_cookie_t cookie) |
43 | { | |
44 | return cookie < 0 ? cookie : 0; | |
45 | } | |
c13c8260 CL |
46 | |
47 | /** | |
48 | * enum dma_status - DMA transaction status | |
adfedd9a | 49 | * @DMA_COMPLETE: transaction completed |
c13c8260 | 50 | * @DMA_IN_PROGRESS: transaction not yet processed |
07934481 | 51 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
52 | * @DMA_ERROR: transaction failed |
53 | */ | |
54 | enum dma_status { | |
7db5f727 | 55 | DMA_COMPLETE, |
c13c8260 | 56 | DMA_IN_PROGRESS, |
07934481 | 57 | DMA_PAUSED, |
c13c8260 CL |
58 | DMA_ERROR, |
59 | }; | |
60 | ||
7405f74b DW |
61 | /** |
62 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
63 | * |
64 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
65 | * automatically set as dma devices are registered. | |
7405f74b DW |
66 | */ |
67 | enum dma_transaction_type { | |
68 | DMA_MEMCPY, | |
69 | DMA_XOR, | |
b2f46fd8 | 70 | DMA_PQ, |
099f53cb DW |
71 | DMA_XOR_VAL, |
72 | DMA_PQ_VAL, | |
7405f74b | 73 | DMA_INTERRUPT, |
a86ee03c | 74 | DMA_SG, |
59b5ec21 | 75 | DMA_PRIVATE, |
138f4c35 | 76 | DMA_ASYNC_TX, |
dc0ee643 | 77 | DMA_SLAVE, |
782bc950 | 78 | DMA_CYCLIC, |
b14dab79 | 79 | DMA_INTERLEAVE, |
7405f74b | 80 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
81 | DMA_TX_TYPE_END, |
82 | }; | |
dc0ee643 | 83 | |
49920bc6 VK |
84 | /** |
85 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
86 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
87 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
88 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
89 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
90 | */ | |
91 | enum dma_transfer_direction { | |
92 | DMA_MEM_TO_MEM, | |
93 | DMA_MEM_TO_DEV, | |
94 | DMA_DEV_TO_MEM, | |
95 | DMA_DEV_TO_DEV, | |
62268ce9 | 96 | DMA_TRANS_NONE, |
49920bc6 | 97 | }; |
7405f74b | 98 | |
b14dab79 JB |
99 | /** |
100 | * Interleaved Transfer Request | |
101 | * ---------------------------- | |
102 | * A chunk is collection of contiguous bytes to be transfered. | |
103 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
104 | * ICGs may or maynot change between chunks. | |
105 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
106 | * that when repeated an integral number of times, specifies the transfer. | |
107 | * A transfer template is specification of a Frame, the number of times | |
108 | * it is to be repeated and other per-transfer attributes. | |
109 | * | |
110 | * Practically, a client driver would have ready a template for each | |
111 | * type of transfer it is going to need during its lifetime and | |
112 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
113 | * | |
114 | * | |
115 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
116 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
117 | * | |
118 | * == Chunk size | |
119 | * ... ICG | |
120 | */ | |
121 | ||
122 | /** | |
123 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
124 | * @size: Number of bytes to read from source. | |
125 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
126 | * @icg: Number of bytes to jump after last src/dst address of this | |
127 | * chunk and before first src/dst address for next chunk. | |
128 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
129 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
130 | */ | |
131 | struct data_chunk { | |
132 | size_t size; | |
133 | size_t icg; | |
134 | }; | |
135 | ||
136 | /** | |
137 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
138 | * and attributes. | |
139 | * @src_start: Bus address of source for the first chunk. | |
140 | * @dst_start: Bus address of destination for the first chunk. | |
141 | * @dir: Specifies the type of Source and Destination. | |
142 | * @src_inc: If the source address increments after reading from it. | |
143 | * @dst_inc: If the destination address increments after writing to it. | |
144 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
145 | * Otherwise, source is read contiguously (icg ignored). | |
146 | * Ignored if src_inc is false. | |
147 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
148 | * Otherwise, destination is filled contiguously (icg ignored). | |
149 | * Ignored if dst_inc is false. | |
150 | * @numf: Number of frames in this template. | |
151 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
152 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
153 | */ | |
154 | struct dma_interleaved_template { | |
155 | dma_addr_t src_start; | |
156 | dma_addr_t dst_start; | |
157 | enum dma_transfer_direction dir; | |
158 | bool src_inc; | |
159 | bool dst_inc; | |
160 | bool src_sgl; | |
161 | bool dst_sgl; | |
162 | size_t numf; | |
163 | size_t frame_size; | |
164 | struct data_chunk sgl[0]; | |
165 | }; | |
166 | ||
d4c56f97 | 167 | /** |
636bdeaa | 168 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 169 | * control completion, and communicate status. |
d4c56f97 | 170 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 171 | * this transaction |
a88f6667 | 172 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
173 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
174 | * chains | |
b2f46fd8 DW |
175 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
176 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
177 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
178 | * sources that were the result of a previous operation, in the case of a PQ | |
179 | * operation it continues the calculation with new sources | |
0403e382 DW |
180 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
181 | * on the result of this operation | |
d4c56f97 | 182 | */ |
636bdeaa | 183 | enum dma_ctrl_flags { |
d4c56f97 | 184 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 185 | DMA_CTRL_ACK = (1 << 1), |
0776ae7b BZ |
186 | DMA_PREP_PQ_DISABLE_P = (1 << 2), |
187 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
188 | DMA_PREP_CONTINUE = (1 << 4), | |
189 | DMA_PREP_FENCE = (1 << 5), | |
d4c56f97 DW |
190 | }; |
191 | ||
c3635c78 LW |
192 | /** |
193 | * enum dma_ctrl_cmd - DMA operations that can optionally be exercised | |
194 | * on a running channel. | |
195 | * @DMA_TERMINATE_ALL: terminate all ongoing transfers | |
196 | * @DMA_PAUSE: pause ongoing transfers | |
197 | * @DMA_RESUME: resume paused transfer | |
c156d0a5 LW |
198 | * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers |
199 | * that need to runtime reconfigure the slave channels (as opposed to passing | |
200 | * configuration data in statically from the platform). An additional | |
201 | * argument of struct dma_slave_config must be passed in with this | |
202 | * command. | |
968f19ae IS |
203 | * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller |
204 | * into external start mode. | |
c3635c78 LW |
205 | */ |
206 | enum dma_ctrl_cmd { | |
207 | DMA_TERMINATE_ALL, | |
208 | DMA_PAUSE, | |
209 | DMA_RESUME, | |
c156d0a5 | 210 | DMA_SLAVE_CONFIG, |
968f19ae | 211 | FSLDMA_EXTERNAL_START, |
c3635c78 LW |
212 | }; |
213 | ||
ad283ea4 DW |
214 | /** |
215 | * enum sum_check_bits - bit position of pq_check_flags | |
216 | */ | |
217 | enum sum_check_bits { | |
218 | SUM_CHECK_P = 0, | |
219 | SUM_CHECK_Q = 1, | |
220 | }; | |
221 | ||
222 | /** | |
223 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
224 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
225 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
226 | */ | |
227 | enum sum_check_flags { | |
228 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
229 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
230 | }; | |
231 | ||
232 | ||
7405f74b DW |
233 | /** |
234 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
235 | * See linux/cpumask.h | |
236 | */ | |
237 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
238 | ||
c13c8260 CL |
239 | /** |
240 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
241 | * @memcpy_count: transaction counter |
242 | * @bytes_transferred: byte counter | |
243 | */ | |
244 | ||
245 | struct dma_chan_percpu { | |
c13c8260 CL |
246 | /* stats */ |
247 | unsigned long memcpy_count; | |
248 | unsigned long bytes_transferred; | |
249 | }; | |
250 | ||
251 | /** | |
252 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 253 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 254 | * @cookie: last cookie value returned to client |
4d4e58de | 255 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 256 | * @chan_id: channel ID for sysfs |
41d5e59c | 257 | * @dev: class device for sysfs |
c13c8260 CL |
258 | * @device_node: used to add this to the device chan list |
259 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
868d2ee2 | 260 | * @client_count: how many clients are using this channel |
bec08513 | 261 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 262 | * @private: private data for certain client-channel associations |
c13c8260 CL |
263 | */ |
264 | struct dma_chan { | |
c13c8260 CL |
265 | struct dma_device *device; |
266 | dma_cookie_t cookie; | |
4d4e58de | 267 | dma_cookie_t completed_cookie; |
c13c8260 CL |
268 | |
269 | /* sysfs */ | |
270 | int chan_id; | |
41d5e59c | 271 | struct dma_chan_dev *dev; |
c13c8260 | 272 | |
c13c8260 | 273 | struct list_head device_node; |
a29d8b8e | 274 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 275 | int client_count; |
bec08513 | 276 | int table_count; |
287d8592 | 277 | void *private; |
c13c8260 CL |
278 | }; |
279 | ||
41d5e59c DW |
280 | /** |
281 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
868d2ee2 VK |
282 | * @chan: driver channel device |
283 | * @device: sysfs device | |
284 | * @dev_id: parent dma_device dev_id | |
285 | * @idr_ref: reference count to gate release of dma_device dev_id | |
41d5e59c DW |
286 | */ |
287 | struct dma_chan_dev { | |
288 | struct dma_chan *chan; | |
289 | struct device device; | |
864498aa DW |
290 | int dev_id; |
291 | atomic_t *idr_ref; | |
41d5e59c DW |
292 | }; |
293 | ||
c156d0a5 | 294 | /** |
ba730340 | 295 | * enum dma_slave_buswidth - defines bus width of the DMA slave |
c156d0a5 LW |
296 | * device, source or target buses |
297 | */ | |
298 | enum dma_slave_buswidth { | |
299 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
300 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
301 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
302 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, | |
303 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
304 | }; | |
305 | ||
306 | /** | |
307 | * struct dma_slave_config - dma slave channel runtime config | |
308 | * @direction: whether the data shall go in or out on this slave | |
397321f4 AP |
309 | * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are |
310 | * legal values. | |
c156d0a5 LW |
311 | * @src_addr: this is the physical address where DMA slave data |
312 | * should be read (RX), if the source is memory this argument is | |
313 | * ignored. | |
314 | * @dst_addr: this is the physical address where DMA slave data | |
315 | * should be written (TX), if the source is memory this argument | |
316 | * is ignored. | |
317 | * @src_addr_width: this is the width in bytes of the source (RX) | |
318 | * register where DMA data shall be read. If the source | |
319 | * is memory this may be ignored depending on architecture. | |
320 | * Legal values: 1, 2, 4, 8. | |
321 | * @dst_addr_width: same as src_addr_width but for destination | |
322 | * target (TX) mutatis mutandis. | |
323 | * @src_maxburst: the maximum number of words (note: words, as in | |
324 | * units of the src_addr_width member, not bytes) that can be sent | |
325 | * in one burst to the device. Typically something like half the | |
326 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
327 | * may or may not be applicable on memory sources. | |
328 | * @dst_maxburst: same as src_maxburst but for destination target | |
329 | * mutatis mutandis. | |
dcc043dc VK |
330 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
331 | * with 'true' if peripheral should be flow controller. Direction will be | |
332 | * selected at Runtime. | |
4fd1e324 LD |
333 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
334 | * slave peripheral will have unique id as dma requester which need to be | |
335 | * pass as slave config. | |
c156d0a5 LW |
336 | * |
337 | * This struct is passed in as configuration data to a DMA engine | |
338 | * in order to set up a certain channel for DMA transport at runtime. | |
339 | * The DMA device/engine has to provide support for an additional | |
340 | * command in the channel config interface, DMA_SLAVE_CONFIG | |
341 | * and this struct will then be passed in as an argument to the | |
342 | * DMA engine device_control() function. | |
343 | * | |
7cbccb55 LPC |
344 | * The rationale for adding configuration information to this struct is as |
345 | * follows: if it is likely that more than one DMA slave controllers in | |
346 | * the world will support the configuration option, then make it generic. | |
347 | * If not: if it is fixed so that it be sent in static from the platform | |
348 | * data, then prefer to do that. | |
c156d0a5 LW |
349 | */ |
350 | struct dma_slave_config { | |
49920bc6 | 351 | enum dma_transfer_direction direction; |
c156d0a5 LW |
352 | dma_addr_t src_addr; |
353 | dma_addr_t dst_addr; | |
354 | enum dma_slave_buswidth src_addr_width; | |
355 | enum dma_slave_buswidth dst_addr_width; | |
356 | u32 src_maxburst; | |
357 | u32 dst_maxburst; | |
dcc043dc | 358 | bool device_fc; |
4fd1e324 | 359 | unsigned int slave_id; |
c156d0a5 LW |
360 | }; |
361 | ||
50720563 LPC |
362 | /** |
363 | * enum dma_residue_granularity - Granularity of the reported transfer residue | |
364 | * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The | |
365 | * DMA channel is only able to tell whether a descriptor has been completed or | |
366 | * not, which means residue reporting is not supported by this channel. The | |
367 | * residue field of the dma_tx_state field will always be 0. | |
368 | * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully | |
369 | * completed segment of the transfer (For cyclic transfers this is after each | |
370 | * period). This is typically implemented by having the hardware generate an | |
371 | * interrupt after each transferred segment and then the drivers updates the | |
372 | * outstanding residue by the size of the segment. Another possibility is if | |
373 | * the hardware supports scatter-gather and the segment descriptor has a field | |
374 | * which gets set after the segment has been completed. The driver then counts | |
375 | * the number of segments without the flag set to compute the residue. | |
376 | * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred | |
377 | * burst. This is typically only supported if the hardware has a progress | |
378 | * register of some sort (E.g. a register with the current read/write address | |
379 | * or a register with the amount of bursts/beats/bytes that have been | |
380 | * transferred or still need to be transferred). | |
381 | */ | |
382 | enum dma_residue_granularity { | |
383 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
384 | DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
385 | DMA_RESIDUE_GRANULARITY_BURST = 2, | |
386 | }; | |
387 | ||
221a27c7 VK |
388 | /* struct dma_slave_caps - expose capabilities of a slave channel only |
389 | * | |
390 | * @src_addr_widths: bit mask of src addr widths the channel supports | |
391 | * @dstn_addr_widths: bit mask of dstn addr widths the channel supports | |
392 | * @directions: bit mask of slave direction the channel supported | |
393 | * since the enum dma_transfer_direction is not defined as bits for each | |
394 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | |
395 | * should be checked by controller as well | |
396 | * @cmd_pause: true, if pause and thereby resume is supported | |
397 | * @cmd_terminate: true, if terminate cmd is supported | |
50720563 | 398 | * @residue_granularity: granularity of the reported transfer residue |
221a27c7 VK |
399 | */ |
400 | struct dma_slave_caps { | |
401 | u32 src_addr_widths; | |
402 | u32 dstn_addr_widths; | |
403 | u32 directions; | |
404 | bool cmd_pause; | |
405 | bool cmd_terminate; | |
50720563 | 406 | enum dma_residue_granularity residue_granularity; |
221a27c7 VK |
407 | }; |
408 | ||
41d5e59c DW |
409 | static inline const char *dma_chan_name(struct dma_chan *chan) |
410 | { | |
411 | return dev_name(&chan->dev->device); | |
412 | } | |
d379b01e | 413 | |
c13c8260 CL |
414 | void dma_chan_cleanup(struct kref *kref); |
415 | ||
59b5ec21 DW |
416 | /** |
417 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
418 | * @chan: channel to be reviewed | |
419 | * @filter_param: opaque parameter passed through dma_request_channel | |
420 | * | |
421 | * When this optional parameter is specified in a call to dma_request_channel a | |
422 | * suitable channel is passed to this routine for further dispositioning before | |
423 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
424 | * satisfies the given capability mask. It returns 'true' to indicate that the |
425 | * channel is suitable. | |
59b5ec21 | 426 | */ |
7dd60251 | 427 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 428 | |
7405f74b | 429 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
d38a8c62 DW |
430 | |
431 | struct dmaengine_unmap_data { | |
c1f43dd9 | 432 | u8 map_cnt; |
d38a8c62 DW |
433 | u8 to_cnt; |
434 | u8 from_cnt; | |
435 | u8 bidi_cnt; | |
436 | struct device *dev; | |
437 | struct kref kref; | |
438 | size_t len; | |
439 | dma_addr_t addr[0]; | |
440 | }; | |
441 | ||
7405f74b DW |
442 | /** |
443 | * struct dma_async_tx_descriptor - async transaction descriptor | |
444 | * ---dma generic offload fields--- | |
445 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
446 | * this tx is sitting on a dependency list | |
636bdeaa DW |
447 | * @flags: flags to augment operation preparation, control completion, and |
448 | * communicate status | |
7405f74b | 449 | * @phys: physical address of the descriptor |
7405f74b DW |
450 | * @chan: target channel for this operation |
451 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
452 | * @callback: routine to call after this operation is complete |
453 | * @callback_param: general parameter to pass to the callback routine | |
454 | * ---async_tx api specific fields--- | |
19242d72 | 455 | * @next: at completion submit this descriptor |
7405f74b | 456 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 457 | * @lock: protect the parent and next pointers |
7405f74b DW |
458 | */ |
459 | struct dma_async_tx_descriptor { | |
460 | dma_cookie_t cookie; | |
636bdeaa | 461 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 462 | dma_addr_t phys; |
7405f74b DW |
463 | struct dma_chan *chan; |
464 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
465 | dma_async_tx_callback callback; |
466 | void *callback_param; | |
d38a8c62 | 467 | struct dmaengine_unmap_data *unmap; |
5fc6d897 | 468 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 469 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
470 | struct dma_async_tx_descriptor *parent; |
471 | spinlock_t lock; | |
caa20d97 | 472 | #endif |
7405f74b DW |
473 | }; |
474 | ||
89716462 | 475 | #ifdef CONFIG_DMA_ENGINE |
d38a8c62 DW |
476 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, |
477 | struct dmaengine_unmap_data *unmap) | |
478 | { | |
479 | kref_get(&unmap->kref); | |
480 | tx->unmap = unmap; | |
481 | } | |
482 | ||
89716462 DW |
483 | struct dmaengine_unmap_data * |
484 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
45c463ae | 485 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); |
89716462 DW |
486 | #else |
487 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
488 | struct dmaengine_unmap_data *unmap) | |
489 | { | |
490 | } | |
491 | static inline struct dmaengine_unmap_data * | |
492 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
493 | { | |
494 | return NULL; | |
495 | } | |
496 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
497 | { | |
498 | } | |
499 | #endif | |
45c463ae | 500 | |
d38a8c62 DW |
501 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) |
502 | { | |
503 | if (tx->unmap) { | |
45c463ae | 504 | dmaengine_unmap_put(tx->unmap); |
d38a8c62 DW |
505 | tx->unmap = NULL; |
506 | } | |
507 | } | |
508 | ||
5fc6d897 | 509 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
510 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
511 | { | |
512 | } | |
513 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
514 | { | |
515 | } | |
516 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
517 | { | |
518 | BUG(); | |
519 | } | |
520 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
521 | { | |
522 | } | |
523 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
524 | { | |
525 | } | |
526 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
527 | { | |
528 | return NULL; | |
529 | } | |
530 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
531 | { | |
532 | return NULL; | |
533 | } | |
534 | ||
535 | #else | |
536 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
537 | { | |
538 | spin_lock_bh(&txd->lock); | |
539 | } | |
540 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
541 | { | |
542 | spin_unlock_bh(&txd->lock); | |
543 | } | |
544 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
545 | { | |
546 | txd->next = next; | |
547 | next->parent = txd; | |
548 | } | |
549 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
550 | { | |
551 | txd->parent = NULL; | |
552 | } | |
553 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
554 | { | |
555 | txd->next = NULL; | |
556 | } | |
557 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
558 | { | |
559 | return txd->parent; | |
560 | } | |
561 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
562 | { | |
563 | return txd->next; | |
564 | } | |
565 | #endif | |
566 | ||
07934481 LW |
567 | /** |
568 | * struct dma_tx_state - filled in to report the status of | |
569 | * a transfer. | |
570 | * @last: last completed DMA cookie | |
571 | * @used: last issued DMA cookie (i.e. the one in progress) | |
572 | * @residue: the remaining number of bytes left to transmit | |
573 | * on the selected transfer for states DMA_IN_PROGRESS and | |
574 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
575 | */ | |
576 | struct dma_tx_state { | |
577 | dma_cookie_t last; | |
578 | dma_cookie_t used; | |
579 | u32 residue; | |
580 | }; | |
581 | ||
c13c8260 CL |
582 | /** |
583 | * struct dma_device - info on the entity supplying DMA services | |
584 | * @chancnt: how many DMA channels are supported | |
0f571515 | 585 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
586 | * @channels: the list of struct dma_chan |
587 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
588 | * @cap_mask: one or more dma_capability flags |
589 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 590 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
591 | * @copy_align: alignment shift for memcpy operations |
592 | * @xor_align: alignment shift for xor operations | |
593 | * @pq_align: alignment shift for pq operations | |
594 | * @fill_align: alignment shift for memset operations | |
fe4ada2d | 595 | * @dev_id: unique device ID |
7405f74b | 596 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
597 | * @device_alloc_chan_resources: allocate resources and return the |
598 | * number of allocated descriptors | |
599 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
600 | * @device_prep_dma_memcpy: prepares a memcpy operation |
601 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 602 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
603 | * @device_prep_dma_pq: prepares a pq operation |
604 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b | 605 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 606 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
607 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
608 | * The function takes a buffer of size buf_len. The callback function will | |
609 | * be called after period_len bytes have been transferred. | |
b14dab79 | 610 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
c3635c78 LW |
611 | * @device_control: manipulate all pending operations on a channel, returns |
612 | * zero or error code | |
07934481 LW |
613 | * @device_tx_status: poll for transaction completion, the optional |
614 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 615 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 616 | * will just return a simple status code |
7405f74b | 617 | * @device_issue_pending: push pending transactions to hardware |
221a27c7 | 618 | * @device_slave_caps: return the slave channel capabilities |
c13c8260 CL |
619 | */ |
620 | struct dma_device { | |
621 | ||
622 | unsigned int chancnt; | |
0f571515 | 623 | unsigned int privatecnt; |
c13c8260 CL |
624 | struct list_head channels; |
625 | struct list_head global_node; | |
7405f74b | 626 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
627 | unsigned short max_xor; |
628 | unsigned short max_pq; | |
83544ae9 DW |
629 | u8 copy_align; |
630 | u8 xor_align; | |
631 | u8 pq_align; | |
632 | u8 fill_align; | |
b2f46fd8 | 633 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 634 | |
c13c8260 | 635 | int dev_id; |
7405f74b | 636 | struct device *dev; |
c13c8260 | 637 | |
aa1e6f1a | 638 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 639 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
640 | |
641 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 642 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 643 | size_t len, unsigned long flags); |
7405f74b | 644 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 645 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 646 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 647 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 648 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 649 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
650 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
651 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
652 | unsigned int src_cnt, const unsigned char *scf, | |
653 | size_t len, unsigned long flags); | |
654 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
655 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
656 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
657 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 658 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 659 | struct dma_chan *chan, unsigned long flags); |
a86ee03c IS |
660 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
661 | struct dma_chan *chan, | |
662 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
663 | struct scatterlist *src_sg, unsigned int src_nents, | |
664 | unsigned long flags); | |
7405f74b | 665 | |
dc0ee643 HS |
666 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
667 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 668 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 669 | unsigned long flags, void *context); |
782bc950 SH |
670 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
671 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 672 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 673 | unsigned long flags, void *context); |
b14dab79 JB |
674 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
675 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
676 | unsigned long flags); | |
05827630 LW |
677 | int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
678 | unsigned long arg); | |
dc0ee643 | 679 | |
07934481 LW |
680 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
681 | dma_cookie_t cookie, | |
682 | struct dma_tx_state *txstate); | |
7405f74b | 683 | void (*device_issue_pending)(struct dma_chan *chan); |
221a27c7 | 684 | int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); |
c13c8260 CL |
685 | }; |
686 | ||
6e3ecaf0 SH |
687 | static inline int dmaengine_device_control(struct dma_chan *chan, |
688 | enum dma_ctrl_cmd cmd, | |
689 | unsigned long arg) | |
690 | { | |
944ea4dd JM |
691 | if (chan->device->device_control) |
692 | return chan->device->device_control(chan, cmd, arg); | |
978c4172 AS |
693 | |
694 | return -ENOSYS; | |
6e3ecaf0 SH |
695 | } |
696 | ||
697 | static inline int dmaengine_slave_config(struct dma_chan *chan, | |
698 | struct dma_slave_config *config) | |
699 | { | |
700 | return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, | |
701 | (unsigned long)config); | |
702 | } | |
703 | ||
61cc13a5 AS |
704 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
705 | { | |
706 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
707 | } | |
708 | ||
90b44f8f | 709 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 710 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 711 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
712 | { |
713 | struct scatterlist sg; | |
922ee08b KM |
714 | sg_init_table(&sg, 1); |
715 | sg_dma_address(&sg) = buf; | |
716 | sg_dma_len(&sg) = len; | |
90b44f8f | 717 | |
185ecb5f AB |
718 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
719 | dir, flags, NULL); | |
90b44f8f VK |
720 | } |
721 | ||
16052827 AB |
722 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
723 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
724 | enum dma_transfer_direction dir, unsigned long flags) | |
725 | { | |
726 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
185ecb5f | 727 | dir, flags, NULL); |
16052827 AB |
728 | } |
729 | ||
e42d98eb AB |
730 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
731 | struct rio_dma_ext; | |
732 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
733 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
734 | enum dma_transfer_direction dir, unsigned long flags, | |
735 | struct rio_dma_ext *rio_ext) | |
736 | { | |
737 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
738 | dir, flags, rio_ext); | |
739 | } | |
740 | #endif | |
741 | ||
16052827 AB |
742 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
743 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
744 | size_t period_len, enum dma_transfer_direction dir, |
745 | unsigned long flags) | |
16052827 AB |
746 | { |
747 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
ec8b5e48 | 748 | period_len, dir, flags, NULL); |
a14acb4a BS |
749 | } |
750 | ||
751 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
752 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
753 | unsigned long flags) | |
754 | { | |
755 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
90b44f8f VK |
756 | } |
757 | ||
221a27c7 VK |
758 | static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) |
759 | { | |
760 | if (!chan || !caps) | |
761 | return -EINVAL; | |
762 | ||
763 | /* check if the channel supports slave transactions */ | |
764 | if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits)) | |
765 | return -ENXIO; | |
766 | ||
767 | if (chan->device->device_slave_caps) | |
768 | return chan->device->device_slave_caps(chan, caps); | |
769 | ||
770 | return -ENXIO; | |
771 | } | |
772 | ||
6e3ecaf0 SH |
773 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
774 | { | |
775 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); | |
776 | } | |
777 | ||
778 | static inline int dmaengine_pause(struct dma_chan *chan) | |
779 | { | |
780 | return dmaengine_device_control(chan, DMA_PAUSE, 0); | |
781 | } | |
782 | ||
783 | static inline int dmaengine_resume(struct dma_chan *chan) | |
784 | { | |
785 | return dmaengine_device_control(chan, DMA_RESUME, 0); | |
786 | } | |
787 | ||
3052cc2c LPC |
788 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
789 | dma_cookie_t cookie, struct dma_tx_state *state) | |
790 | { | |
791 | return chan->device->device_tx_status(chan, cookie, state); | |
792 | } | |
793 | ||
98d530fe | 794 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
795 | { |
796 | return desc->tx_submit(desc); | |
797 | } | |
798 | ||
83544ae9 DW |
799 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
800 | { | |
801 | size_t mask; | |
802 | ||
803 | if (!align) | |
804 | return true; | |
805 | mask = (1 << align) - 1; | |
806 | if (mask & (off1 | off2 | len)) | |
807 | return false; | |
808 | return true; | |
809 | } | |
810 | ||
811 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
812 | size_t off2, size_t len) | |
813 | { | |
814 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
815 | } | |
816 | ||
817 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
818 | size_t off2, size_t len) | |
819 | { | |
820 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
821 | } | |
822 | ||
823 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
824 | size_t off2, size_t len) | |
825 | { | |
826 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
827 | } | |
828 | ||
829 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
830 | size_t off2, size_t len) | |
831 | { | |
832 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
833 | } | |
834 | ||
b2f46fd8 DW |
835 | static inline void |
836 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
837 | { | |
838 | dma->max_pq = maxpq; | |
839 | if (has_pq_continue) | |
840 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
841 | } | |
842 | ||
843 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
844 | { | |
845 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
846 | } | |
847 | ||
848 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
849 | { | |
850 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
851 | ||
852 | return (flags & mask) == mask; | |
853 | } | |
854 | ||
855 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
856 | { | |
857 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
858 | } | |
859 | ||
d3f3cf85 | 860 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
861 | { |
862 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
863 | } | |
864 | ||
865 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
866 | * @dma - dma device with PQ capability | |
867 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
868 | * | |
869 | * When an engine does not support native continuation we need 3 extra | |
870 | * source slots to reuse P and Q with the following coefficients: | |
871 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
872 | * 2/ {01} * Q : use Q to continue Q' calculation | |
873 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
874 | * | |
875 | * In the case where P is disabled we only need 1 extra source: | |
876 | * 1/ {01} * Q : use Q to continue Q' calculation | |
877 | */ | |
878 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
879 | { | |
880 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
881 | return dma_dev_to_maxpq(dma); | |
882 | else if (dmaf_p_disabled_continue(flags)) | |
883 | return dma_dev_to_maxpq(dma) - 1; | |
884 | else if (dmaf_continue(flags)) | |
885 | return dma_dev_to_maxpq(dma) - 3; | |
886 | BUG(); | |
887 | } | |
888 | ||
c13c8260 CL |
889 | /* --- public DMA engine API --- */ |
890 | ||
649274d9 | 891 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
892 | void dmaengine_get(void); |
893 | void dmaengine_put(void); | |
649274d9 DW |
894 | #else |
895 | static inline void dmaengine_get(void) | |
896 | { | |
897 | } | |
898 | static inline void dmaengine_put(void) | |
899 | { | |
900 | } | |
901 | #endif | |
902 | ||
b4bd07c2 DM |
903 | #ifdef CONFIG_NET_DMA |
904 | #define net_dmaengine_get() dmaengine_get() | |
905 | #define net_dmaengine_put() dmaengine_put() | |
906 | #else | |
907 | static inline void net_dmaengine_get(void) | |
908 | { | |
909 | } | |
910 | static inline void net_dmaengine_put(void) | |
911 | { | |
912 | } | |
913 | #endif | |
914 | ||
729b5d1b DW |
915 | #ifdef CONFIG_ASYNC_TX_DMA |
916 | #define async_dmaengine_get() dmaengine_get() | |
917 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 918 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
919 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
920 | #else | |
729b5d1b | 921 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 922 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
923 | #else |
924 | static inline void async_dmaengine_get(void) | |
925 | { | |
926 | } | |
927 | static inline void async_dmaengine_put(void) | |
928 | { | |
929 | } | |
930 | static inline struct dma_chan * | |
931 | async_dma_find_channel(enum dma_transaction_type type) | |
932 | { | |
933 | return NULL; | |
934 | } | |
138f4c35 | 935 | #endif /* CONFIG_ASYNC_TX_DMA */ |
729b5d1b | 936 | |
7405f74b DW |
937 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
938 | void *dest, void *src, size_t len); | |
939 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
940 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
941 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
942 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
943 | unsigned int src_off, size_t len); | |
944 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
945 | struct dma_chan *chan); | |
c13c8260 | 946 | |
0839875e | 947 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 948 | { |
636bdeaa DW |
949 | tx->flags |= DMA_CTRL_ACK; |
950 | } | |
951 | ||
ef560682 GL |
952 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
953 | { | |
954 | tx->flags &= ~DMA_CTRL_ACK; | |
955 | } | |
956 | ||
0839875e | 957 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 958 | { |
0839875e | 959 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
960 | } |
961 | ||
7405f74b DW |
962 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
963 | static inline void | |
964 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 965 | { |
7405f74b DW |
966 | set_bit(tx_type, dstp->bits); |
967 | } | |
c13c8260 | 968 | |
0f571515 AN |
969 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
970 | static inline void | |
971 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
972 | { | |
973 | clear_bit(tx_type, dstp->bits); | |
974 | } | |
975 | ||
33df8ca0 DW |
976 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
977 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
978 | { | |
979 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
980 | } | |
981 | ||
7405f74b DW |
982 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
983 | static inline int | |
984 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
985 | { | |
986 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
987 | } |
988 | ||
7405f74b | 989 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 990 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 991 | |
c13c8260 | 992 | /** |
7405f74b | 993 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 994 | * @chan: target DMA channel |
c13c8260 CL |
995 | * |
996 | * This allows drivers to push copies to HW in batches, | |
997 | * reducing MMIO writes where possible. | |
998 | */ | |
7405f74b | 999 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 1000 | { |
ec8670f1 | 1001 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
1002 | } |
1003 | ||
1004 | /** | |
7405f74b | 1005 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
1006 | * @chan: DMA channel |
1007 | * @cookie: transaction identifier to check status of | |
1008 | * @last: returns last completed cookie, can be NULL | |
1009 | * @used: returns last issued cookie, can be NULL | |
1010 | * | |
1011 | * If @last and @used are passed in, upon return they reflect the driver | |
1012 | * internal state and can be used with dma_async_is_complete() to check | |
1013 | * the status of multiple cookies without re-checking hardware state. | |
1014 | */ | |
7405f74b | 1015 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
1016 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
1017 | { | |
07934481 LW |
1018 | struct dma_tx_state state; |
1019 | enum dma_status status; | |
1020 | ||
1021 | status = chan->device->device_tx_status(chan, cookie, &state); | |
1022 | if (last) | |
1023 | *last = state.last; | |
1024 | if (used) | |
1025 | *used = state.used; | |
1026 | return status; | |
c13c8260 CL |
1027 | } |
1028 | ||
1029 | /** | |
1030 | * dma_async_is_complete - test a cookie against chan state | |
1031 | * @cookie: transaction identifier to test status of | |
1032 | * @last_complete: last know completed transaction | |
1033 | * @last_used: last cookie value handed out | |
1034 | * | |
e239345f | 1035 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 1036 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
1037 | */ |
1038 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1039 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1040 | { | |
1041 | if (last_complete <= last_used) { | |
1042 | if ((cookie <= last_complete) || (cookie > last_used)) | |
adfedd9a | 1043 | return DMA_COMPLETE; |
c13c8260 CL |
1044 | } else { |
1045 | if ((cookie <= last_complete) && (cookie > last_used)) | |
adfedd9a | 1046 | return DMA_COMPLETE; |
c13c8260 CL |
1047 | } |
1048 | return DMA_IN_PROGRESS; | |
1049 | } | |
1050 | ||
bca34692 DW |
1051 | static inline void |
1052 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1053 | { | |
1054 | if (st) { | |
1055 | st->last = last; | |
1056 | st->used = used; | |
1057 | st->residue = residue; | |
1058 | } | |
1059 | } | |
1060 | ||
07f2211e | 1061 | #ifdef CONFIG_DMA_ENGINE |
4a43f394 JM |
1062 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
1063 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
07f2211e | 1064 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
c50331e8 | 1065 | void dma_issue_pending_all(void); |
a53e28da LPC |
1066 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
1067 | dma_filter_fn fn, void *fn_param); | |
0ad7c000 SW |
1068 | struct dma_chan *dma_request_slave_channel_reason(struct device *dev, |
1069 | const char *name); | |
bef29ec5 | 1070 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
8f33d527 | 1071 | void dma_release_channel(struct dma_chan *chan); |
07f2211e | 1072 | #else |
4a43f394 JM |
1073 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) |
1074 | { | |
1075 | return NULL; | |
1076 | } | |
1077 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1078 | { | |
adfedd9a | 1079 | return DMA_COMPLETE; |
4a43f394 | 1080 | } |
07f2211e DW |
1081 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1082 | { | |
adfedd9a | 1083 | return DMA_COMPLETE; |
07f2211e | 1084 | } |
c50331e8 DW |
1085 | static inline void dma_issue_pending_all(void) |
1086 | { | |
8f33d527 | 1087 | } |
a53e28da | 1088 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
8f33d527 GL |
1089 | dma_filter_fn fn, void *fn_param) |
1090 | { | |
1091 | return NULL; | |
1092 | } | |
0ad7c000 SW |
1093 | static inline struct dma_chan *dma_request_slave_channel_reason( |
1094 | struct device *dev, const char *name) | |
1095 | { | |
1096 | return ERR_PTR(-ENODEV); | |
1097 | } | |
9a6cecc8 | 1098 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 1099 | const char *name) |
9a6cecc8 | 1100 | { |
d18d5f59 | 1101 | return NULL; |
9a6cecc8 | 1102 | } |
8f33d527 GL |
1103 | static inline void dma_release_channel(struct dma_chan *chan) |
1104 | { | |
c50331e8 | 1105 | } |
07f2211e | 1106 | #endif |
c13c8260 CL |
1107 | |
1108 | /* --- DMA device --- */ | |
1109 | ||
1110 | int dma_async_device_register(struct dma_device *device); | |
1111 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 1112 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
7bb587f4 | 1113 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
8010dad5 | 1114 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); |
a2bd1140 | 1115 | struct dma_chan *net_dma_find_channel(void); |
59b5ec21 | 1116 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
864ef69b MP |
1117 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
1118 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1119 | ||
1120 | static inline struct dma_chan | |
a53e28da LPC |
1121 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, |
1122 | dma_filter_fn fn, void *fn_param, | |
1123 | struct device *dev, char *name) | |
864ef69b MP |
1124 | { |
1125 | struct dma_chan *chan; | |
1126 | ||
1127 | chan = dma_request_slave_channel(dev, name); | |
1128 | if (chan) | |
1129 | return chan; | |
1130 | ||
1131 | return __dma_request_channel(mask, fn, fn_param); | |
1132 | } | |
c13c8260 | 1133 | |
de5506e1 CL |
1134 | /* --- Helper iov-locking functions --- */ |
1135 | ||
1136 | struct dma_page_list { | |
b2ddb901 | 1137 | char __user *base_address; |
de5506e1 CL |
1138 | int nr_pages; |
1139 | struct page **pages; | |
1140 | }; | |
1141 | ||
1142 | struct dma_pinned_list { | |
1143 | int nr_iovecs; | |
1144 | struct dma_page_list page_list[0]; | |
1145 | }; | |
1146 | ||
1147 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
1148 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
1149 | ||
1150 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1151 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
1152 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
1153 | struct dma_pinned_list *pinned_list, struct page *page, | |
1154 | unsigned int offset, size_t len); | |
1155 | ||
c13c8260 | 1156 | #endif /* DMAENGINE_H */ |