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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
7405f74b | 26 | #include <linux/dma-mapping.h> |
c13c8260 | 27 | |
c13c8260 | 28 | /** |
fe4ada2d | 29 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
30 | * |
31 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
32 | */ | |
33 | typedef s32 dma_cookie_t; | |
34 | ||
35 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
36 | ||
37 | /** | |
38 | * enum dma_status - DMA transaction status | |
39 | * @DMA_SUCCESS: transaction completed successfully | |
40 | * @DMA_IN_PROGRESS: transaction not yet processed | |
41 | * @DMA_ERROR: transaction failed | |
42 | */ | |
43 | enum dma_status { | |
44 | DMA_SUCCESS, | |
45 | DMA_IN_PROGRESS, | |
46 | DMA_ERROR, | |
47 | }; | |
48 | ||
7405f74b DW |
49 | /** |
50 | * enum dma_transaction_type - DMA transaction types/indexes | |
51 | */ | |
52 | enum dma_transaction_type { | |
53 | DMA_MEMCPY, | |
54 | DMA_XOR, | |
55 | DMA_PQ_XOR, | |
56 | DMA_DUAL_XOR, | |
57 | DMA_PQ_UPDATE, | |
58 | DMA_ZERO_SUM, | |
59 | DMA_PQ_ZERO_SUM, | |
60 | DMA_MEMSET, | |
61 | DMA_MEMCPY_CRC32C, | |
62 | DMA_INTERRUPT, | |
59b5ec21 | 63 | DMA_PRIVATE, |
dc0ee643 | 64 | DMA_SLAVE, |
7405f74b DW |
65 | }; |
66 | ||
67 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
68 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
69 | ||
7405f74b | 70 | |
d4c56f97 | 71 | /** |
636bdeaa DW |
72 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
73 | * control completion, and communicate status. | |
d4c56f97 DW |
74 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
75 | * this transaction | |
636bdeaa DW |
76 | * @DMA_CTRL_ACK - the descriptor cannot be reused until the client |
77 | * acknowledges receipt, i.e. has has a chance to establish any | |
78 | * dependency chains | |
e1d181ef DW |
79 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
80 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
4f005dbe MS |
81 | * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single |
82 | * (if not set, do the source dma-unmapping as page) | |
83 | * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single | |
84 | * (if not set, do the destination dma-unmapping as page) | |
d4c56f97 | 85 | */ |
636bdeaa | 86 | enum dma_ctrl_flags { |
d4c56f97 | 87 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 88 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
89 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
90 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
4f005dbe MS |
91 | DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4), |
92 | DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5), | |
d4c56f97 DW |
93 | }; |
94 | ||
7405f74b DW |
95 | /** |
96 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
97 | * See linux/cpumask.h | |
98 | */ | |
99 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
100 | ||
c13c8260 CL |
101 | /** |
102 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
103 | * @memcpy_count: transaction counter |
104 | * @bytes_transferred: byte counter | |
105 | */ | |
106 | ||
107 | struct dma_chan_percpu { | |
c13c8260 CL |
108 | /* stats */ |
109 | unsigned long memcpy_count; | |
110 | unsigned long bytes_transferred; | |
111 | }; | |
112 | ||
113 | /** | |
114 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 115 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 116 | * @cookie: last cookie value returned to client |
fe4ada2d | 117 | * @chan_id: channel ID for sysfs |
41d5e59c | 118 | * @dev: class device for sysfs |
c13c8260 CL |
119 | * @device_node: used to add this to the device chan list |
120 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 121 | * @client-count: how many clients are using this channel |
bec08513 | 122 | * @table_count: number of appearances in the mem-to-mem allocation table |
287d8592 | 123 | * @private: private data for certain client-channel associations |
c13c8260 CL |
124 | */ |
125 | struct dma_chan { | |
c13c8260 CL |
126 | struct dma_device *device; |
127 | dma_cookie_t cookie; | |
128 | ||
129 | /* sysfs */ | |
130 | int chan_id; | |
41d5e59c | 131 | struct dma_chan_dev *dev; |
c13c8260 | 132 | |
c13c8260 CL |
133 | struct list_head device_node; |
134 | struct dma_chan_percpu *local; | |
7cc5bf9a | 135 | int client_count; |
bec08513 | 136 | int table_count; |
287d8592 | 137 | void *private; |
c13c8260 CL |
138 | }; |
139 | ||
41d5e59c DW |
140 | /** |
141 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
142 | * @chan - driver channel device | |
143 | * @device - sysfs device | |
864498aa DW |
144 | * @dev_id - parent dma_device dev_id |
145 | * @idr_ref - reference count to gate release of dma_device dev_id | |
41d5e59c DW |
146 | */ |
147 | struct dma_chan_dev { | |
148 | struct dma_chan *chan; | |
149 | struct device device; | |
864498aa DW |
150 | int dev_id; |
151 | atomic_t *idr_ref; | |
41d5e59c DW |
152 | }; |
153 | ||
154 | static inline const char *dma_chan_name(struct dma_chan *chan) | |
155 | { | |
156 | return dev_name(&chan->dev->device); | |
157 | } | |
d379b01e | 158 | |
c13c8260 CL |
159 | void dma_chan_cleanup(struct kref *kref); |
160 | ||
59b5ec21 DW |
161 | /** |
162 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
163 | * @chan: channel to be reviewed | |
164 | * @filter_param: opaque parameter passed through dma_request_channel | |
165 | * | |
166 | * When this optional parameter is specified in a call to dma_request_channel a | |
167 | * suitable channel is passed to this routine for further dispositioning before | |
168 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
169 | * satisfies the given capability mask. It returns 'true' to indicate that the |
170 | * channel is suitable. | |
59b5ec21 | 171 | */ |
7dd60251 | 172 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 173 | |
7405f74b DW |
174 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
175 | /** | |
176 | * struct dma_async_tx_descriptor - async transaction descriptor | |
177 | * ---dma generic offload fields--- | |
178 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
179 | * this tx is sitting on a dependency list | |
636bdeaa DW |
180 | * @flags: flags to augment operation preparation, control completion, and |
181 | * communicate status | |
7405f74b DW |
182 | * @phys: physical address of the descriptor |
183 | * @tx_list: driver common field for operations that require multiple | |
184 | * descriptors | |
185 | * @chan: target channel for this operation | |
186 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
187 | * @callback: routine to call after this operation is complete |
188 | * @callback_param: general parameter to pass to the callback routine | |
189 | * ---async_tx api specific fields--- | |
19242d72 | 190 | * @next: at completion submit this descriptor |
7405f74b | 191 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 192 | * @lock: protect the parent and next pointers |
7405f74b DW |
193 | */ |
194 | struct dma_async_tx_descriptor { | |
195 | dma_cookie_t cookie; | |
636bdeaa | 196 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b DW |
197 | dma_addr_t phys; |
198 | struct list_head tx_list; | |
199 | struct dma_chan *chan; | |
200 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
201 | dma_async_tx_callback callback; |
202 | void *callback_param; | |
19242d72 | 203 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
204 | struct dma_async_tx_descriptor *parent; |
205 | spinlock_t lock; | |
206 | }; | |
207 | ||
c13c8260 CL |
208 | /** |
209 | * struct dma_device - info on the entity supplying DMA services | |
210 | * @chancnt: how many DMA channels are supported | |
0f571515 | 211 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
212 | * @channels: the list of struct dma_chan |
213 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
214 | * @cap_mask: one or more dma_capability flags |
215 | * @max_xor: maximum number of xor sources, 0 if no capability | |
fe4ada2d | 216 | * @dev_id: unique device ID |
7405f74b | 217 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
218 | * @device_alloc_chan_resources: allocate resources and return the |
219 | * number of allocated descriptors | |
220 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
221 | * @device_prep_dma_memcpy: prepares a memcpy operation |
222 | * @device_prep_dma_xor: prepares a xor operation | |
223 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | |
224 | * @device_prep_dma_memset: prepares a memset operation | |
225 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
226 | * @device_prep_slave_sg: prepares a slave dma operation |
227 | * @device_terminate_all: terminate all pending operations | |
1d93e52e | 228 | * @device_is_tx_complete: poll for transaction completion |
7405f74b | 229 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
230 | */ |
231 | struct dma_device { | |
232 | ||
233 | unsigned int chancnt; | |
0f571515 | 234 | unsigned int privatecnt; |
c13c8260 CL |
235 | struct list_head channels; |
236 | struct list_head global_node; | |
7405f74b DW |
237 | dma_cap_mask_t cap_mask; |
238 | int max_xor; | |
c13c8260 | 239 | |
c13c8260 | 240 | int dev_id; |
7405f74b | 241 | struct device *dev; |
c13c8260 | 242 | |
aa1e6f1a | 243 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 244 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
245 | |
246 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 247 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 248 | size_t len, unsigned long flags); |
7405f74b | 249 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 250 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 251 | unsigned int src_cnt, size_t len, unsigned long flags); |
7405f74b | 252 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
0036731c | 253 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
d4c56f97 | 254 | size_t len, u32 *result, unsigned long flags); |
7405f74b | 255 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 256 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 257 | unsigned long flags); |
7405f74b | 258 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 259 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 260 | |
dc0ee643 HS |
261 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
262 | struct dma_chan *chan, struct scatterlist *sgl, | |
263 | unsigned int sg_len, enum dma_data_direction direction, | |
264 | unsigned long flags); | |
265 | void (*device_terminate_all)(struct dma_chan *chan); | |
266 | ||
7405f74b | 267 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
268 | dma_cookie_t cookie, dma_cookie_t *last, |
269 | dma_cookie_t *used); | |
7405f74b | 270 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
271 | }; |
272 | ||
273 | /* --- public DMA engine API --- */ | |
274 | ||
649274d9 | 275 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
276 | void dmaengine_get(void); |
277 | void dmaengine_put(void); | |
649274d9 DW |
278 | #else |
279 | static inline void dmaengine_get(void) | |
280 | { | |
281 | } | |
282 | static inline void dmaengine_put(void) | |
283 | { | |
284 | } | |
285 | #endif | |
286 | ||
b4bd07c2 DM |
287 | #ifdef CONFIG_NET_DMA |
288 | #define net_dmaengine_get() dmaengine_get() | |
289 | #define net_dmaengine_put() dmaengine_put() | |
290 | #else | |
291 | static inline void net_dmaengine_get(void) | |
292 | { | |
293 | } | |
294 | static inline void net_dmaengine_put(void) | |
295 | { | |
296 | } | |
297 | #endif | |
298 | ||
729b5d1b DW |
299 | #ifdef CONFIG_ASYNC_TX_DMA |
300 | #define async_dmaengine_get() dmaengine_get() | |
301 | #define async_dmaengine_put() dmaengine_put() | |
302 | #define async_dma_find_channel(type) dma_find_channel(type) | |
303 | #else | |
304 | static inline void async_dmaengine_get(void) | |
305 | { | |
306 | } | |
307 | static inline void async_dmaengine_put(void) | |
308 | { | |
309 | } | |
310 | static inline struct dma_chan * | |
311 | async_dma_find_channel(enum dma_transaction_type type) | |
312 | { | |
313 | return NULL; | |
314 | } | |
315 | #endif | |
316 | ||
7405f74b DW |
317 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
318 | void *dest, void *src, size_t len); | |
319 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
320 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
321 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
322 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
323 | unsigned int src_off, size_t len); | |
324 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
325 | struct dma_chan *chan); | |
c13c8260 | 326 | |
0839875e | 327 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 328 | { |
636bdeaa DW |
329 | tx->flags |= DMA_CTRL_ACK; |
330 | } | |
331 | ||
ef560682 GL |
332 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
333 | { | |
334 | tx->flags &= ~DMA_CTRL_ACK; | |
335 | } | |
336 | ||
0839875e | 337 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 338 | { |
0839875e | 339 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
340 | } |
341 | ||
7405f74b DW |
342 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
343 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 344 | { |
7405f74b DW |
345 | return min_t(int, DMA_TX_TYPE_END, |
346 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
347 | } | |
c13c8260 | 348 | |
7405f74b DW |
349 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
350 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
351 | { | |
352 | return min_t(int, DMA_TX_TYPE_END, | |
353 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
354 | } |
355 | ||
7405f74b DW |
356 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
357 | static inline void | |
358 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 359 | { |
7405f74b DW |
360 | set_bit(tx_type, dstp->bits); |
361 | } | |
c13c8260 | 362 | |
0f571515 AN |
363 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
364 | static inline void | |
365 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
366 | { | |
367 | clear_bit(tx_type, dstp->bits); | |
368 | } | |
369 | ||
33df8ca0 DW |
370 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
371 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
372 | { | |
373 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
374 | } | |
375 | ||
7405f74b DW |
376 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
377 | static inline int | |
378 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
379 | { | |
380 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
381 | } |
382 | ||
7405f74b DW |
383 | #define for_each_dma_cap_mask(cap, mask) \ |
384 | for ((cap) = first_dma_cap(mask); \ | |
385 | (cap) < DMA_TX_TYPE_END; \ | |
386 | (cap) = next_dma_cap((cap), (mask))) | |
387 | ||
c13c8260 | 388 | /** |
7405f74b | 389 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 390 | * @chan: target DMA channel |
c13c8260 CL |
391 | * |
392 | * This allows drivers to push copies to HW in batches, | |
393 | * reducing MMIO writes where possible. | |
394 | */ | |
7405f74b | 395 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 396 | { |
ec8670f1 | 397 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
398 | } |
399 | ||
7405f74b DW |
400 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
401 | ||
c13c8260 | 402 | /** |
7405f74b | 403 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
404 | * @chan: DMA channel |
405 | * @cookie: transaction identifier to check status of | |
406 | * @last: returns last completed cookie, can be NULL | |
407 | * @used: returns last issued cookie, can be NULL | |
408 | * | |
409 | * If @last and @used are passed in, upon return they reflect the driver | |
410 | * internal state and can be used with dma_async_is_complete() to check | |
411 | * the status of multiple cookies without re-checking hardware state. | |
412 | */ | |
7405f74b | 413 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
414 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
415 | { | |
7405f74b | 416 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
417 | } |
418 | ||
7405f74b DW |
419 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
420 | dma_async_is_tx_complete(chan, cookie, last, used) | |
421 | ||
c13c8260 CL |
422 | /** |
423 | * dma_async_is_complete - test a cookie against chan state | |
424 | * @cookie: transaction identifier to test status of | |
425 | * @last_complete: last know completed transaction | |
426 | * @last_used: last cookie value handed out | |
427 | * | |
428 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 429 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
430 | */ |
431 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
432 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
433 | { | |
434 | if (last_complete <= last_used) { | |
435 | if ((cookie <= last_complete) || (cookie > last_used)) | |
436 | return DMA_SUCCESS; | |
437 | } else { | |
438 | if ((cookie <= last_complete) && (cookie > last_used)) | |
439 | return DMA_SUCCESS; | |
440 | } | |
441 | return DMA_IN_PROGRESS; | |
442 | } | |
443 | ||
7405f74b | 444 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
445 | #ifdef CONFIG_DMA_ENGINE |
446 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
c50331e8 | 447 | void dma_issue_pending_all(void); |
07f2211e DW |
448 | #else |
449 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
450 | { | |
451 | return DMA_SUCCESS; | |
452 | } | |
c50331e8 DW |
453 | static inline void dma_issue_pending_all(void) |
454 | { | |
455 | do { } while (0); | |
456 | } | |
07f2211e | 457 | #endif |
c13c8260 CL |
458 | |
459 | /* --- DMA device --- */ | |
460 | ||
461 | int dma_async_device_register(struct dma_device *device); | |
462 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 463 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 464 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
59b5ec21 DW |
465 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
466 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
467 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 468 | |
de5506e1 CL |
469 | /* --- Helper iov-locking functions --- */ |
470 | ||
471 | struct dma_page_list { | |
b2ddb901 | 472 | char __user *base_address; |
de5506e1 CL |
473 | int nr_pages; |
474 | struct page **pages; | |
475 | }; | |
476 | ||
477 | struct dma_pinned_list { | |
478 | int nr_iovecs; | |
479 | struct dma_page_list page_list[0]; | |
480 | }; | |
481 | ||
482 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
483 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
484 | ||
485 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
486 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
487 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
488 | struct dma_pinned_list *pinned_list, struct page *page, | |
489 | unsigned int offset, size_t len); | |
490 | ||
c13c8260 | 491 | #endif /* DMAENGINE_H */ |