[deliverable/linux.git] / include / linux / dmar.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
 */

#ifndef __DMAR_H__
#define __DMAR_H__

#include <linux/acpi.h>
#include <linux/types.h>
#include <linux/msi.h>
#include <linux/irqreturn.h>
#include <linux/rwsem.h>
#include <linux/rcupdate.h>

struct acpi_dmar_header;

/* DMAR Flags */
#define DMAR_INTR_REMAP		0x1
#define DMAR_X2APIC_OPT_OUT	0x2

struct intel_iommu;

struct dmar_dev_scope {
	struct device __rcu *dev;
	u8 bus;
	u8 devfn;
};

#ifdef CONFIG_DMAR_TABLE
extern struct acpi_table_header *dmar_tbl;
struct dmar_drhd_unit {
	struct list_head list;		/* list of drhd units	*/
	struct  acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	reg_base_addr;		/* register base address*/
	struct	dmar_dev_scope *devices;/* target device array	*/
	int	devices_cnt;		/* target device count	*/
	u16	segment;		/* PCI domain		*/
	u8	ignored:1; 		/* ignore drhd		*/
	u8	include_all:1;
	struct intel_iommu *iommu;
};

struct dmar_pci_notify_info {
	struct pci_dev			*dev;
	unsigned long			event;
	int				bus;
	u16				seg;
	u16				level;
	struct acpi_dmar_pci_path	path[];
}  __attribute__((packed));

extern struct rw_semaphore dmar_global_lock;
extern struct list_head dmar_drhd_units;

#define for_each_drhd_unit(drhd) \
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)

#define for_each_active_drhd_unit(drhd)					\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (drhd->ignored) {} else

#define for_each_active_iommu(i, drhd)					\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, drhd->ignored) {} else

#define for_each_iommu(i, drhd)						\
	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)		\
		if (i=drhd->iommu, 0) {} else 

static inline bool dmar_rcu_check(void)
{
	return rwsem_is_locked(&dmar_global_lock) ||
	       system_state == SYSTEM_BOOTING;
}

#define	dmar_rcu_dereference(p)	rcu_dereference_check((p), dmar_rcu_check())

#define	for_each_dev_scope(a, c, p, d)	\
	for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)].dev) : \
			NULL, (p) < (c)); (p)++)

#define	for_each_active_dev_scope(a, c, p, d)	\
	for_each_dev_scope((a), (c), (p), (d))	if (!(d)) { continue; } else

extern int dmar_table_init(void);
extern int dmar_dev_scope_init(void);
extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
				struct dmar_dev_scope **devices, u16 segment);
extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
				 void *start, void*end, u16 segment,
				 struct dmar_dev_scope *devices,
				 int devices_cnt);
extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
				 u16 segment, struct dmar_dev_scope *devices,
				 int count);
/* Intel IOMMU detection */
extern int detect_intel_iommu(void);
extern int enable_drhd_fault_handling(void);

#ifdef CONFIG_INTEL_IOMMU
extern int iommu_detected, no_iommu;
extern int intel_iommu_init(void);
extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
#else /* !CONFIG_INTEL_IOMMU: */
static inline int intel_iommu_init(void) { return -ENODEV; }
static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
{
	return 0;
}
static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
{
	return 0;
}
static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
{
	return 0;
}
#endif /* CONFIG_INTEL_IOMMU */

#endif /* CONFIG_DMAR_TABLE */

struct irte {
	union {
		struct {
			__u64	present 	: 1,
				fpd		: 1,
				dst_mode	: 1,
				redir_hint	: 1,
				trigger_mode	: 1,
				dlvry_mode	: 3,
				avail		: 4,
				__reserved_1	: 4,
				vector		: 8,
				__reserved_2	: 8,
				dest_id		: 32;
		};
		__u64 low;
	};

	union {
		struct {
			__u64	sid		: 16,
				sq		: 2,
				svt		: 2,
				__reserved_3	: 44;
		};
		__u64 high;
	};
};

enum {
	IRQ_REMAP_XAPIC_MODE,
	IRQ_REMAP_X2APIC_MODE,
};

/* Can't use the common MSI interrupt functions
 * since DMAR is not a pci device
 */
struct irq_data;
extern void dmar_msi_unmask(struct irq_data *data);
extern void dmar_msi_mask(struct irq_data *data);
extern void dmar_msi_read(int irq, struct msi_msg *msg);
extern void dmar_msi_write(int irq, struct msi_msg *msg);
extern int dmar_set_interrupt(struct intel_iommu *iommu);
extern irqreturn_t dmar_fault(int irq, void *dev_id);
extern int arch_setup_dmar_msi(unsigned int irq);

#endif /* __DMAR_H__ */
Commit	Line	Data
10e5247f KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
	17	* Copyright (C) Ashok Raj <ashok.raj@intel.com>
	18	* Copyright (C) Shaohua Li <shaohua.li@intel.com>
	19	*/
	20
	21	#ifndef __DMAR_H__
	22	#define __DMAR_H__
	23
	24	#include <linux/acpi.h>
	25	#include <linux/types.h>
ba395927	26	#include <linux/msi.h>
1531a6a6	27	#include <linux/irqreturn.h>
3a5670e8	28	#include <linux/rwsem.h>
0e242612	29	#include <linux/rcupdate.h>
10e5247f	30
6eea69dd AM	31	struct acpi_dmar_header;
6eea69dd AM	32
41750d31 SS	33	/* DMAR Flags */
	34	#define DMAR_INTR_REMAP 0x1
	35	#define DMAR_X2APIC_OPT_OUT 0x2
	36
ba395927	37	struct intel_iommu;
694835dc	38
832bd858 DW	39	struct dmar_dev_scope {
	40	struct device __rcu *dev;
	41	u8 bus;
	42	u8 devfn;
	43	};
	44
d3f13810	45	#ifdef CONFIG_DMAR_TABLE
41750d31	46	extern struct acpi_table_header *dmar_tbl;
2ae21010 SS	47	struct dmar_drhd_unit {
	48	struct list_head list; /* list of drhd units */
	49	struct acpi_dmar_header hdr; / ACPI header */
	50	u64 reg_base_addr; /* register base address*/
832bd858	51	struct dmar_dev_scope devices;/ target device array */
2ae21010	52	int devices_cnt; /* target device count */
276dbf99	53	u16 segment; /* PCI domain */
2ae21010 SS	54	u8 ignored:1; /* ignore drhd */
	55	u8 include_all:1;
	56	struct intel_iommu *iommu;
	57	};
	58
59ce0515 JL	59	struct dmar_pci_notify_info {
	60	struct pci_dev *dev;
	61	unsigned long event;
	62	int bus;
	63	u16 seg;
	64	u16 level;
	65	struct acpi_dmar_pci_path path[];
	66	} __attribute__((packed));
	67
3a5670e8	68	extern struct rw_semaphore dmar_global_lock;
2ae21010 SS	69	extern struct list_head dmar_drhd_units;
	70
	71	#define for_each_drhd_unit(drhd) \
0e242612	72	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)
2ae21010	73
7c919779	74	#define for_each_active_drhd_unit(drhd) \
0e242612	75	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
7c919779 JL	76	if (drhd->ignored) {} else
7c919779 JL	77
8f912ba4	78	#define for_each_active_iommu(i, drhd) \
0e242612	79	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
8f912ba4 DW	80	if (i=drhd->iommu, drhd->ignored) {} else
	81
	82	#define for_each_iommu(i, drhd) \
0e242612	83	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
8f912ba4 DW	84	if (i=drhd->iommu, 0) {} else
8f912ba4 DW	85
0e242612 JL	86	static inline bool dmar_rcu_check(void)
	87	{
	88	return rwsem_is_locked(&dmar_global_lock) \|\|
	89	system_state == SYSTEM_BOOTING;
	90	}
	91
	92	#define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
	93
b683b230	94	#define for_each_dev_scope(a, c, p, d) \
832bd858	95	for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)].dev) : \
0e242612	96	NULL, (p) < (c)); (p)++)
b683b230 JL	97
	98	#define for_each_active_dev_scope(a, c, p, d) \
	99	for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else
	100
2ae21010	101	extern int dmar_table_init(void);
2ae21010	102	extern int dmar_dev_scope_init(void);
ada4d4b2	103	extern int dmar_parse_dev_scope(void start, void end, int *cnt,
832bd858	104	struct dmar_dev_scope **devices, u16 segment);
bb3a6b78	105	extern void dmar_alloc_dev_scope(void start, void end, int cnt);
832bd858	106	extern void dmar_free_dev_scope(struct dmar_dev_scope *devices, int cnt);
59ce0515 JL	107	extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
59ce0515 JL	108	void start, voidend, u16 segment,
832bd858	109	struct dmar_dev_scope *devices,
59ce0515 JL	110	int devices_cnt);
59ce0515 JL	111	extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
832bd858	112	u16 segment, struct dmar_dev_scope *devices,
59ce0515	113	int count);
2ae21010	114	/* Intel IOMMU detection */
480125ba	115	extern int detect_intel_iommu(void);
9d783ba0	116	extern int enable_drhd_fault_handling(void);
8594d832 JL	117
	118	#ifdef CONFIG_INTEL_IOMMU
	119	extern int iommu_detected, no_iommu;
	120	extern int intel_iommu_init(void);
	121	extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
	122	extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
	123	extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
	124	#else /* !CONFIG_INTEL_IOMMU: */
	125	static inline int intel_iommu_init(void) { return -ENODEV; }
	126	static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
2ae21010	127	{
8594d832	128	return 0;
2ae21010	129	}
8594d832	130	static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
2ae21010	131	{
8594d832	132	return 0;
2ae21010	133	}
8594d832	134	static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
29b61be6	135	{
8594d832	136	return 0;
29b61be6	137	}
8594d832 JL	138	#endif /* CONFIG_INTEL_IOMMU */
	139
	140	#endif /* CONFIG_DMAR_TABLE */
2ae21010	141
2ae21010 SS	142	struct irte {
	143	union {
	144	struct {
	145	__u64 present : 1,
	146	fpd : 1,
	147	dst_mode : 1,
	148	redir_hint : 1,
	149	trigger_mode : 1,
	150	dlvry_mode : 3,
	151	avail : 4,
	152	__reserved_1 : 4,
	153	vector : 8,
	154	__reserved_2 : 8,
	155	dest_id : 32;
	156	};
	157	__u64 low;
	158	};
	159
	160	union {
	161	struct {
	162	__u64 sid : 16,
	163	sq : 2,
	164	svt : 2,
	165	__reserved_3 : 44;
	166	};
	167	__u64 high;
	168	};
	169	};
423f0859	170
41750d31 SS	171	enum {
	172	IRQ_REMAP_XAPIC_MODE,
	173	IRQ_REMAP_X2APIC_MODE,
	174	};
	175
3460a6d9 KA	176	/* Can't use the common MSI interrupt functions
	177	* since DMAR is not a pci device
	178	*/
5c2837fb TG	179	struct irq_data;
	180	extern void dmar_msi_unmask(struct irq_data *data);
	181	extern void dmar_msi_mask(struct irq_data *data);
3460a6d9 KA	182	extern void dmar_msi_read(int irq, struct msi_msg *msg);
	183	extern void dmar_msi_write(int irq, struct msi_msg *msg);
	184	extern int dmar_set_interrupt(struct intel_iommu *iommu);
1531a6a6	185	extern irqreturn_t dmar_fault(int irq, void *dev_id);
3460a6d9 KA	186	extern int arch_setup_dmar_msi(unsigned int irq);
3460a6d9 KA	187
10e5247f	188	#endif /* __DMAR_H__ */