projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3bfb1d20 HS |
1 | /* |
| 2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
| 3 | * AVR32 systems.) | |
| 4 | * | |
| 5 | * Copyright (C) 2007 Atmel Corporation | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | #ifndef DW_DMAC_H | |
| 12 | #define DW_DMAC_H | |
| 13 | ||
| 14 | #include <linux/dmaengine.h> | |
| 15 | ||
| 16 | /** | |
| 17 | * struct dw_dma_platform_data - Controller configuration parameters | |
| 18 | * @nr_channels: Number of channels supported by hardware (max 8) | |
| 19 | */ | |
| 20 | struct dw_dma_platform_data { | |
| 21 | unsigned int nr_channels; | |
| 22 | }; | |
| 23 | ||
| 24 | /** | |
| 25 | * struct dw_dma_slave - Controller-specific information about a slave | |
| 26 | * @slave: Generic information about the slave | |
| 27 | * @ctl_lo: Platform-specific initializer for the CTL_LO register | |
| 28 | * @cfg_hi: Platform-specific initializer for the CFG_HI register | |
| 29 | * @cfg_lo: Platform-specific initializer for the CFG_LO register | |
| 30 | */ | |
| 31 | struct dw_dma_slave { | |
| 32 | struct dma_slave slave; | |
| 33 | u32 cfg_hi; | |
| 34 | u32 cfg_lo; | |
| 35 | }; | |
| 36 | ||
| 37 | /* Platform-configurable bits in CFG_HI */ | |
| 38 | #define DWC_CFGH_FCMODE (1 << 0) | |
| 39 | #define DWC_CFGH_FIFO_MODE (1 << 1) | |
| 40 | #define DWC_CFGH_PROTCTL(x) ((x) << 2) | |
| 41 | #define DWC_CFGH_SRC_PER(x) ((x) << 7) | |
| 42 | #define DWC_CFGH_DST_PER(x) ((x) << 11) | |
| 43 | ||
| 44 | /* Platform-configurable bits in CFG_LO */ | |
| 45 | #define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */ | |
| 46 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ | |
| 47 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) | |
| 48 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) | |
| 49 | #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ | |
| 50 | #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) | |
| 51 | #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) | |
| 52 | #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ | |
| 53 | #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ | |
| 54 | #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ | |
| 55 | #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ | |
| 56 | ||
| 57 | static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave) | |
| 58 | { | |
| 59 | return container_of(slave, struct dw_dma_slave, slave); | |
| 60 | } | |
| 61 | ||
| 62 | #endif /* DW_DMAC_H */ |