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1da177e4 LT |
1 | /* |
2 | * include/linux/fsl_devices.h | |
3 | * | |
4 | * Definitions for any platform device related flags or structures for | |
5 | * Freescale processor devices | |
6 | * | |
4c8d3d99 | 7 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
1da177e4 LT |
8 | * |
9 | * Copyright 2004 Freescale Semiconductor, Inc | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #ifndef _FSL_DEVICE_H_ |
18 | #define _FSL_DEVICE_H_ | |
19 | ||
20 | #include <linux/types.h> | |
21 | ||
22 | /* | |
23 | * Some conventions on how we handle peripherals on Freescale chips | |
24 | * | |
25 | * unique device: a platform_device entry in fsl_plat_devs[] plus | |
26 | * associated device information in its platform_data structure. | |
27 | * | |
28 | * A chip is described by a set of unique devices. | |
29 | * | |
30 | * Each sub-arch has its own master list of unique devices and | |
31 | * enumerates them by enum fsl_devices in a sub-arch specific header | |
32 | * | |
33 | * The platform data structure is broken into two parts. The | |
34 | * first is device specific information that help identify any | |
35 | * unique features of a peripheral. The second is any | |
36 | * information that may be defined by the board or how the device | |
37 | * is connected externally of the chip. | |
38 | * | |
39 | * naming conventions: | |
40 | * - platform data structures: <driver>_platform_data | |
41 | * - platform data device flags: FSL_<driver>_DEV_<FLAG> | |
42 | * - platform data board flags: FSL_<driver>_BRD_<FLAG> | |
43 | * | |
44 | */ | |
45 | ||
80cb9aee RV |
46 | enum fsl_usb2_operating_modes { |
47 | FSL_USB2_MPH_HOST, | |
48 | FSL_USB2_DR_HOST, | |
49 | FSL_USB2_DR_DEVICE, | |
50 | FSL_USB2_DR_OTG, | |
51 | }; | |
52 | ||
53 | enum fsl_usb2_phy_modes { | |
54 | FSL_USB2_PHY_NONE, | |
55 | FSL_USB2_PHY_ULPI, | |
56 | FSL_USB2_PHY_UTMI, | |
57 | FSL_USB2_PHY_UTMI_WIDE, | |
58 | FSL_USB2_PHY_SERIAL, | |
59 | }; | |
60 | ||
230f7ede AG |
61 | struct clk; |
62 | struct platform_device; | |
63 | ||
80cb9aee RV |
64 | struct fsl_usb2_platform_data { |
65 | /* board specific information */ | |
98658538 LY |
66 | enum fsl_usb2_operating_modes operating_mode; |
67 | enum fsl_usb2_phy_modes phy_mode; | |
68 | unsigned int port_enables; | |
69cb1ec4 | 69 | unsigned int workaround; |
230f7ede AG |
70 | |
71 | int (*init)(struct platform_device *); | |
72 | void (*exit)(struct platform_device *); | |
73 | void __iomem *regs; /* ioremap'd register base */ | |
74 | struct clk *clk; | |
83722bc9 | 75 | unsigned power_budget; /* hcd->power_budget */ |
230f7ede AG |
76 | unsigned big_endian_mmio:1; |
77 | unsigned big_endian_desc:1; | |
78 | unsigned es:1; /* need USBMODE:ES */ | |
79 | unsigned le_setup_buf:1; | |
80 | unsigned have_sysif_regs:1; | |
81 | unsigned invert_drvvbus:1; | |
82 | unsigned invert_pwr_fault:1; | |
13b7ee2a AG |
83 | |
84 | unsigned suspended:1; | |
85 | unsigned already_suspended:1; | |
86 | ||
87 | /* register save area for suspend/resume */ | |
88 | u32 pm_command; | |
89 | u32 pm_status; | |
90 | u32 pm_intr_enable; | |
91 | u32 pm_frame_index; | |
92 | u32 pm_segment; | |
93 | u32 pm_frame_list; | |
94 | u32 pm_async_next; | |
95 | u32 pm_configured_flag; | |
96 | u32 pm_portsc; | |
97 | u32 pm_usbgenctrl; | |
80cb9aee RV |
98 | }; |
99 | ||
100 | /* Flags in fsl_usb2_mph_platform_data */ | |
101 | #define FSL_USB2_PORT0_ENABLED 0x00000001 | |
102 | #define FSL_USB2_PORT1_ENABLED 0x00000002 | |
103 | ||
69cb1ec4 EB |
104 | #define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0) |
105 | ||
364fdbc0 AV |
106 | struct spi_device; |
107 | ||
ccf06998 KG |
108 | struct fsl_spi_platform_data { |
109 | u32 initial_spmode; /* initial SPMODE value */ | |
35b4b3c0 | 110 | s16 bus_num; |
87ec0e98 | 111 | unsigned int flags; |
7d6709a2 BH |
112 | #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */ |
113 | #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */ | |
114 | #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */ | |
115 | #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */ | |
116 | #define SPI_QE (1 << 4) /* SPI unit is in QE block */ | |
ccf06998 KG |
117 | /* board specific information */ |
118 | u16 max_chipselect; | |
364fdbc0 | 119 | void (*cs_control)(struct spi_device *spi, bool on); |
ccf06998 KG |
120 | u32 sysclk; |
121 | }; | |
122 | ||
80128ff7 VB |
123 | struct mpc8xx_pcmcia_ops { |
124 | void(*hw_ctrl)(int slot, int enable); | |
125 | int(*voltage_set)(int slot, int vcc, int vpp); | |
126 | }; | |
127 | ||
d49747bd SW |
128 | /* Returns non-zero if the current suspend operation would |
129 | * lead to a deep sleep (i.e. power removed from the core, | |
130 | * instead of just the clock). | |
131 | */ | |
2e9d546e | 132 | #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND) |
d49747bd | 133 | int fsl_deep_sleep(void); |
2e9d546e AV |
134 | #else |
135 | static inline int fsl_deep_sleep(void) { return 0; } | |
136 | #endif | |
d49747bd | 137 | |
98658538 | 138 | #endif /* _FSL_DEVICE_H_ */ |