[deliverable/linux.git] / include / linux / gpio / driver.h

#ifndef __LINUX_GPIO_DRIVER_H
#define __LINUX_GPIO_DRIVER_H

#include <linux/device.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/kconfig.h>

struct gpio_desc;
struct of_phandle_args;
struct device_node;
struct seq_file;
struct gpio_device;

#ifdef CONFIG_GPIOLIB

/**
 * enum single_ended_mode - mode for single ended operation
 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
 * @LINE_MODE_OPEN_DRAIN: set line to be open drain
 * @LINE_MODE_OPEN_SOURCE: set line to be open source
 */
enum single_ended_mode {
	LINE_MODE_PUSH_PULL,
	LINE_MODE_OPEN_DRAIN,
	LINE_MODE_OPEN_SOURCE,
};

/**
 * struct gpio_chip - abstract a GPIO controller
 * @label: a functional name for the GPIO device, such as a part
 *	number or the name of the SoC IP-block implementing it.
 * @gpiodev: the internal state holder, opaque struct
 * @parent: optional parent device providing the GPIOs
 * @owner: helps prevent removal of modules exporting active GPIOs
 * @request: optional hook for chip-specific activation, such as
 *	enabling module power and clock; may sleep
 * @free: optional hook for chip-specific deactivation, such as
 *	disabling module power and clock; may sleep
 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 *	(same as GPIOF_DIR_XXX), or negative error
 * @direction_input: configures signal "offset" as input, or returns error
 * @direction_output: configures signal "offset" as output, or returns error
 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 * @set: assigns output value for signal "offset"
 * @set_multiple: assigns output values for multiple signals defined by "mask"
 * @set_debounce: optional hook for setting debounce time for specified gpio in
 *	interrupt triggered gpio chips
 * @set_single_ended: optional hook for setting a line as open drain, open
 *	source, or non-single ended (restore from open drain/source to normal
 *	push-pull mode) this should be implemented if the hardware supports
 *	open drain or open source settings. The GPIOlib will otherwise try
 *	to emulate open drain/source by not actively driving lines high/low
 *	if a consumer request this. The driver may return -ENOTSUPP if e.g.
 *	it supports just open drain but not open source and is called
 *	with LINE_MODE_OPEN_SOURCE as mode argument.
 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 *	implementation may not sleep
 * @dbg_show: optional routine to show contents in debugfs; default code
 *	will be used when this is omitted, but custom code can show extra
 *	state (such as pullup/pulldown configuration).
 * @base: identifies the first GPIO number handled by this chip;
 *	or, if negative during registration, requests dynamic ID allocation.
 *	DEPRECATION: providing anything non-negative and nailing the base
 *	offset of GPIO chips is deprecated. Please pass -1 as base to
 *	let gpiolib select the chip base in all possible cases. We want to
 *	get rid of the static GPIO number space in the long run.
 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 *	handled is (base + ngpio - 1).
 * @names: if set, must be an array of strings to use as alternative
 *      names for the GPIOs in this chip. Any entry in the array
 *      may be NULL if there is no alias for the GPIO, however the
 *      array must be @ngpio entries long.  A name can include a single printk
 *      format specifier for an unsigned int.  It is substituted by the actual
 *      number of the gpio.
 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 *	must while accessing GPIO expander chips over I2C or SPI. This
 *	implies that if the chip supports IRQs, these IRQs need to be threaded
 *	as the chip access may sleep when e.g. reading out the IRQ status
 *	registers.
 * @irq_not_threaded: flag must be set if @can_sleep is set but the
 *	IRQs don't need to be threaded
 * @read_reg: reader function for generic GPIO
 * @write_reg: writer function for generic GPIO
 * @pin2mask: some generic GPIO controllers work with the big-endian bits
 *	notation, e.g. in a 8-bits register, GPIO7 is the least significant
 *	bit. This callback assigns the right bit mask.
 * @reg_dat: data (in) register for generic GPIO
 * @reg_set: output set register (out=high) for generic GPIO
 * @reg_clk: output clear register (out=low) for generic GPIO
 * @reg_dir: direction setting register for generic GPIO
 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 *	<register width> * 8
 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 *	shadowed and real data registers writes together.
 * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
 *	safely.
 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 *	direction safely.
 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
 * @irqdomain: Interrupt translation domain; responsible for mapping
 *	between GPIO hwirq number and linux irq number
 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
 * @irq_handler: the irq handler to use (often a predefined irq core function)
 *	for GPIO IRQs, provided by GPIO driver
 * @irq_default_type: default IRQ triggering type applied during GPIO driver
 *	initialization, provided by GPIO driver
 * @irq_parent: GPIO IRQ chip parent/bank linux irq number,
 *	provided by GPIO driver
 * @lock_key: per GPIO IRQ chip lockdep class
 *
 * A gpio_chip can help platforms abstract various sources of GPIOs so
 * they can all be accessed through a common programing interface.
 * Example sources would be SOC controllers, FPGAs, multifunction
 * chips, dedicated GPIO expanders, and so on.
 *
 * Each chip controls a number of signals, identified in method calls
 * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 * are referenced through calls like gpio_get_value(gpio), the offset
 * is calculated by subtracting @base from the gpio number.
 */
struct gpio_chip {
	const char		*label;
	struct gpio_device	*gpiodev;
	struct device		*parent;
	struct module		*owner;

	int			(*request)(struct gpio_chip *chip,
						unsigned offset);
	void			(*free)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_direction)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_input)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_output)(struct gpio_chip *chip,
						unsigned offset, int value);
	int			(*get)(struct gpio_chip *chip,
						unsigned offset);
	void			(*set)(struct gpio_chip *chip,
						unsigned offset, int value);
	void			(*set_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	int			(*set_debounce)(struct gpio_chip *chip,
						unsigned offset,
						unsigned debounce);
	int			(*set_single_ended)(struct gpio_chip *chip,
						unsigned offset,
						enum single_ended_mode mode);

	int			(*to_irq)(struct gpio_chip *chip,
						unsigned offset);

	void			(*dbg_show)(struct seq_file *s,
						struct gpio_chip *chip);
	int			base;
	u16			ngpio;
	const char		*const *names;
	bool			can_sleep;
	bool			irq_not_threaded;

#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	unsigned long (*read_reg)(void __iomem *reg);
	void (*write_reg)(void __iomem *reg, unsigned long data);
	unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
	void __iomem *reg_dat;
	void __iomem *reg_set;
	void __iomem *reg_clr;
	void __iomem *reg_dir;
	int bgpio_bits;
	spinlock_t bgpio_lock;
	unsigned long bgpio_data;
	unsigned long bgpio_dir;
#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP
	/*
	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
	 * to handle IRQs for most practical cases.
	 */
	struct irq_chip		*irqchip;
	struct irq_domain	*irqdomain;
	unsigned int		irq_base;
	irq_flow_handler_t	irq_handler;
	unsigned int		irq_default_type;
	int			irq_parent;
	struct lock_class_key	*lock_key;
#endif

#if defined(CONFIG_OF_GPIO)
	/*
	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
	 * device tree automatically may have an OF translation
	 */
	struct device_node *of_node;
	int of_gpio_n_cells;
	int (*of_xlate)(struct gpio_chip *gc,
			const struct of_phandle_args *gpiospec, u32 *flags);
#endif
};

extern const char *gpiochip_is_requested(struct gpio_chip *chip,
			unsigned offset);

/* add/remove chips */
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
static inline int gpiochip_add(struct gpio_chip *chip)
{
	return gpiochip_add_data(chip, NULL);
}
extern void gpiochip_remove(struct gpio_chip *chip);
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
				  void *data);
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);

extern struct gpio_chip *gpiochip_find(void *data,
			      int (*match)(struct gpio_chip *chip, void *data));

/* lock/unlock as IRQ */
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);

/* Line status inquiry for drivers */
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);

/* get driver data */
void *gpiochip_get_data(struct gpio_chip *chip);

struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);

struct bgpio_pdata {
	const char *label;
	int base;
	int ngpio;
};

#if IS_ENABLED(CONFIG_GPIO_GENERIC)

int bgpio_init(struct gpio_chip *gc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags);

#define BGPIOF_BIG_ENDIAN		BIT(0)
#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */

#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP

void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		int parent_irq,
		irq_flow_handler_t parent_handler);

int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type,
			  struct lock_class_key *lock_key);

#ifdef CONFIG_LOCKDEP
#define gpiochip_irqchip_add(...)				\
(								\
	({							\
		static struct lock_class_key _key;		\
		_gpiochip_irqchip_add(__VA_ARGS__, &_key);	\
	})							\
)
#else
#define gpiochip_irqchip_add(...)				\
	_gpiochip_irqchip_add(__VA_ARGS__, NULL)
#endif

#endif /* CONFIG_GPIOLIB_IRQCHIP */

int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);

#ifdef CONFIG_PINCTRL

/**
 * struct gpio_pin_range - pin range controlled by a gpio chip
 * @head: list for maintaining set of pin ranges, used internally
 * @pctldev: pinctrl device which handles corresponding pins
 * @range: actual range of pins controlled by a gpio controller
 */

struct gpio_pin_range {
	struct list_head node;
	struct pinctrl_dev *pctldev;
	struct pinctrl_gpio_range range;
};

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
			   unsigned int gpio_offset, unsigned int pin_offset,
			   unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);

#else

static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
		       unsigned int gpio_offset, unsigned int pin_offset,
		       unsigned int npins)
{
	return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group)
{
	return 0;
}

static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
}

#endif /* CONFIG_PINCTRL */

struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
					    const char *label);
void gpiochip_free_own_desc(struct gpio_desc *desc);

#else /* CONFIG_GPIOLIB */

static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
{
	/* GPIO can never have been requested */
	WARN_ON(1);
	return ERR_PTR(-ENODEV);
}

#endif /* CONFIG_GPIOLIB */

#endif
Commit	Line	Data
79a9becd AC	1	#ifndef __LINUX_GPIO_DRIVER_H
	2	#define __LINUX_GPIO_DRIVER_H
	3
ff2b1359	4	#include <linux/device.h>
79a9becd	5	#include <linux/types.h>
c9a9972b	6	#include <linux/module.h>
14250520 LW	7	#include <linux/irq.h>
	8	#include <linux/irqchip/chained_irq.h>
	9	#include <linux/irqdomain.h>
a0a8bcf4	10	#include <linux/lockdep.h>
964cb341	11	#include <linux/pinctrl/pinctrl.h>
0f4630f3	12	#include <linux/kconfig.h>
79a9becd	13
79a9becd	14	struct gpio_desc;
c9a9972b AC	15	struct of_phandle_args;
c9a9972b AC	16	struct device_node;
f3ed0b66	17	struct seq_file;
ff2b1359	18	struct gpio_device;
79a9becd	19
bb1e88cc AC	20	#ifdef CONFIG_GPIOLIB
bb1e88cc AC	21
c663e5f5 LW	22	/**
	23	* enum single_ended_mode - mode for single ended operation
	24	* @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
	25	* @LINE_MODE_OPEN_DRAIN: set line to be open drain
	26	* @LINE_MODE_OPEN_SOURCE: set line to be open source
	27	*/
	28	enum single_ended_mode {
	29	LINE_MODE_PUSH_PULL,
	30	LINE_MODE_OPEN_DRAIN,
	31	LINE_MODE_OPEN_SOURCE,
	32	};
	33
79a9becd AC	34	/**
79a9becd AC	35	* struct gpio_chip - abstract a GPIO controller
df4878e9 LW	36	* @label: a functional name for the GPIO device, such as a part
df4878e9 LW	37	* number or the name of the SoC IP-block implementing it.
ff2b1359	38	* @gpiodev: the internal state holder, opaque struct
58383c78	39	* @parent: optional parent device providing the GPIOs
79a9becd	40	* @owner: helps prevent removal of modules exporting active GPIOs
79a9becd AC	41	* @request: optional hook for chip-specific activation, such as
	42	* enabling module power and clock; may sleep
	43	* @free: optional hook for chip-specific deactivation, such as
	44	* disabling module power and clock; may sleep
	45	* @get_direction: returns direction for signal "offset", 0=out, 1=in,
	46	* (same as GPIOF_DIR_XXX), or negative error
	47	* @direction_input: configures signal "offset" as input, or returns error
	48	* @direction_output: configures signal "offset" as output, or returns error
60befd2e	49	* @get: returns value for signal "offset", 0=low, 1=high, or negative error
79a9becd	50	* @set: assigns output value for signal "offset"
5f424243	51	* @set_multiple: assigns output values for multiple signals defined by "mask"
79a9becd	52	* @set_debounce: optional hook for setting debounce time for specified gpio in
c663e5f5 LW	53	* interrupt triggered gpio chips
	54	* @set_single_ended: optional hook for setting a line as open drain, open
	55	* source, or non-single ended (restore from open drain/source to normal
	56	* push-pull mode) this should be implemented if the hardware supports
	57	* open drain or open source settings. The GPIOlib will otherwise try
	58	* to emulate open drain/source by not actively driving lines high/low
	59	* if a consumer request this. The driver may return -ENOTSUPP if e.g.
	60	* it supports just open drain but not open source and is called
	61	* with LINE_MODE_OPEN_SOURCE as mode argument.
79a9becd AC	62	* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
	63	* implementation may not sleep
	64	* @dbg_show: optional routine to show contents in debugfs; default code
	65	* will be used when this is omitted, but custom code can show extra
	66	* state (such as pullup/pulldown configuration).
af6c235d LW	67	* @base: identifies the first GPIO number handled by this chip;
	68	* or, if negative during registration, requests dynamic ID allocation.
	69	* DEPRECATION: providing anything non-negative and nailing the base
30bb6fb3	70	* offset of GPIO chips is deprecated. Please pass -1 as base to
af6c235d LW	71	* let gpiolib select the chip base in all possible cases. We want to
af6c235d LW	72	* get rid of the static GPIO number space in the long run.
79a9becd AC	73	* @ngpio: the number of GPIOs handled by this controller; the last GPIO
79a9becd AC	74	* handled is (base + ngpio - 1).
79a9becd AC	75	* @names: if set, must be an array of strings to use as alternative
	76	* names for the GPIOs in this chip. Any entry in the array
	77	* may be NULL if there is no alias for the GPIO, however the
	78	* array must be @ngpio entries long. A name can include a single printk
	79	* format specifier for an unsigned int. It is substituted by the actual
	80	* number of the gpio.
9fb1f39e	81	* @can_sleep: flag must be set iff get()/set() methods sleep, as they
1c8732bb LW	82	* must while accessing GPIO expander chips over I2C or SPI. This
	83	* implies that if the chip supports IRQs, these IRQs need to be threaded
	84	* as the chip access may sleep when e.g. reading out the IRQ status
	85	* registers.
295494af OP	86	* @irq_not_threaded: flag must be set if @can_sleep is set but the
295494af OP	87	* IRQs don't need to be threaded
0f4630f3 LW	88	* @read_reg: reader function for generic GPIO
	89	* @write_reg: writer function for generic GPIO
	90	* @pin2mask: some generic GPIO controllers work with the big-endian bits
	91	* notation, e.g. in a 8-bits register, GPIO7 is the least significant
	92	* bit. This callback assigns the right bit mask.
	93	* @reg_dat: data (in) register for generic GPIO
	94	* @reg_set: output set register (out=high) for generic GPIO
	95	* @reg_clk: output clear register (out=low) for generic GPIO
	96	* @reg_dir: direction setting register for generic GPIO
	97	* @bgpio_bits: number of register bits used for a generic GPIO i.e.
	98	* <register width> * 8
	99	* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
	100	* shadowed and real data registers writes together.
	101	* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
	102	* safely.
	103	* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
	104	* direction safely.
41d6bb4c GS	105	* @irqchip: GPIO IRQ chip impl, provided by GPIO driver
	106	* @irqdomain: Interrupt translation domain; responsible for mapping
	107	* between GPIO hwirq number and linux irq number
	108	* @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
	109	* @irq_handler: the irq handler to use (often a predefined irq core function)
	110	* for GPIO IRQs, provided by GPIO driver
	111	* @irq_default_type: default IRQ triggering type applied during GPIO driver
	112	* initialization, provided by GPIO driver
	113	* @irq_parent: GPIO IRQ chip parent/bank linux irq number,
	114	* provided by GPIO driver
	115	* @lock_key: per GPIO IRQ chip lockdep class
79a9becd AC	116	*
	117	* A gpio_chip can help platforms abstract various sources of GPIOs so
	118	* they can all be accessed through a common programing interface.
	119	* Example sources would be SOC controllers, FPGAs, multifunction
	120	* chips, dedicated GPIO expanders, and so on.
	121	*
	122	* Each chip controls a number of signals, identified in method calls
	123	* by "offset" values in the range 0..(@ngpio - 1). When those signals
	124	* are referenced through calls like gpio_get_value(gpio), the offset
	125	* is calculated by subtracting @base from the gpio number.
	126	*/
	127	struct gpio_chip {
	128	const char *label;
ff2b1359	129	struct gpio_device *gpiodev;
58383c78	130	struct device *parent;
79a9becd	131	struct module *owner;
79a9becd AC	132
	133	int (request)(struct gpio_chip chip,
	134	unsigned offset);
	135	void (free)(struct gpio_chip chip,
	136	unsigned offset);
	137	int (get_direction)(struct gpio_chip chip,
	138	unsigned offset);
	139	int (direction_input)(struct gpio_chip chip,
	140	unsigned offset);
	141	int (direction_output)(struct gpio_chip chip,
	142	unsigned offset, int value);
	143	int (get)(struct gpio_chip chip,
	144	unsigned offset);
	145	void (set)(struct gpio_chip chip,
	146	unsigned offset, int value);
5f424243 RI	147	void (set_multiple)(struct gpio_chip chip,
	148	unsigned long *mask,
	149	unsigned long *bits);
79a9becd AC	150	int (set_debounce)(struct gpio_chip chip,
	151	unsigned offset,
	152	unsigned debounce);
c663e5f5 LW	153	int (set_single_ended)(struct gpio_chip chip,
	154	unsigned offset,
	155	enum single_ended_mode mode);
79a9becd AC	156
	157	int (to_irq)(struct gpio_chip chip,
	158	unsigned offset);
	159
	160	void (dbg_show)(struct seq_file s,
	161	struct gpio_chip *chip);
	162	int base;
	163	u16 ngpio;
79a9becd	164	const char const names;
9fb1f39e	165	bool can_sleep;
295494af	166	bool irq_not_threaded;
79a9becd	167
0f4630f3 LW	168	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	169	unsigned long (read_reg)(void __iomem reg);
	170	void (write_reg)(void __iomem reg, unsigned long data);
	171	unsigned long (pin2mask)(struct gpio_chip gc, unsigned int pin);
	172	void __iomem *reg_dat;
	173	void __iomem *reg_set;
	174	void __iomem *reg_clr;
	175	void __iomem *reg_dir;
	176	int bgpio_bits;
	177	spinlock_t bgpio_lock;
	178	unsigned long bgpio_data;
	179	unsigned long bgpio_dir;
	180	#endif
	181
14250520 LW	182	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	183	/*
7d75a871	184	* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
14250520 LW	185	* to handle IRQs for most practical cases.
	186	*/
	187	struct irq_chip *irqchip;
	188	struct irq_domain *irqdomain;
c3626fde	189	unsigned int irq_base;
14250520 LW	190	irq_flow_handler_t irq_handler;
14250520 LW	191	unsigned int irq_default_type;
25e4fe92	192	int irq_parent;
a0a8bcf4	193	struct lock_class_key *lock_key;
14250520 LW	194	#endif
14250520 LW	195
79a9becd AC	196	#if defined(CONFIG_OF_GPIO)
	197	/*
	198	* If CONFIG_OF is enabled, then all GPIO controllers described in the
	199	* device tree automatically may have an OF translation
	200	*/
	201	struct device_node *of_node;
	202	int of_gpio_n_cells;
	203	int (of_xlate)(struct gpio_chip gc,
	204	const struct of_phandle_args gpiospec, u32 flags);
	205	#endif
79a9becd AC	206	};
	207
	208	extern const char gpiochip_is_requested(struct gpio_chip chip,
	209	unsigned offset);
	210
	211	/* add/remove chips */
b08ea35a LW	212	extern int gpiochip_add_data(struct gpio_chip chip, void data);
	213	static inline int gpiochip_add(struct gpio_chip *chip)
	214	{
	215	return gpiochip_add_data(chip, NULL);
	216	}
e1db1706	217	extern void gpiochip_remove(struct gpio_chip *chip);
0cf3292c LD	218	extern int devm_gpiochip_add_data(struct device dev, struct gpio_chip chip,
	219	void *data);
	220	extern void devm_gpiochip_remove(struct device dev, struct gpio_chip chip);
	221
79a9becd AC	222	extern struct gpio_chip gpiochip_find(void data,
	223	int (match)(struct gpio_chip chip, void *data));
	224
	225	/* lock/unlock as IRQ */
e3a2e878 AC	226	int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
e3a2e878 AC	227	void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
6cee3821	228	bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
79a9becd	229
143b65d6 LW	230	/* Line status inquiry for drivers */
	231	bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
	232	bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
	233
b08ea35a	234	/* get driver data */
43c54eca	235	void gpiochip_get_data(struct gpio_chip chip);
b08ea35a	236
bb1e88cc AC	237	struct gpio_chip gpiod_to_chip(const struct gpio_desc desc);
bb1e88cc AC	238
0f4630f3 LW	239	struct bgpio_pdata {
	240	const char *label;
	241	int base;
	242	int ngpio;
	243	};
	244
c474e348 AB	245	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
c474e348 AB	246
0f4630f3 LW	247	int bgpio_init(struct gpio_chip gc, struct device dev,
	248	unsigned long sz, void __iomem dat, void __iomem set,
	249	void __iomem clr, void __iomem dirout, void __iomem *dirin,
	250	unsigned long flags);
	251
	252	#define BGPIOF_BIG_ENDIAN BIT(0)
	253	#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
	254	#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
	255	#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
	256	#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
	257	#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
	258
	259	#endif
	260
14250520 LW	261	#ifdef CONFIG_GPIOLIB_IRQCHIP
	262
	263	void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
	264	struct irq_chip *irqchip,
	265	int parent_irq,
	266	irq_flow_handler_t parent_handler);
	267
a0a8bcf4 GS	268	int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	269	struct irq_chip *irqchip,
	270	unsigned int first_irq,
	271	irq_flow_handler_t handler,
	272	unsigned int type,
	273	struct lock_class_key *lock_key);
	274
	275	#ifdef CONFIG_LOCKDEP
	276	#define gpiochip_irqchip_add(...) \
	277	( \
	278	({ \
	279	static struct lock_class_key _key; \
	280	_gpiochip_irqchip_add(__VA_ARGS__, &_key); \
	281	}) \
	282	)
	283	#else
	284	#define gpiochip_irqchip_add(...) \
	285	_gpiochip_irqchip_add(__VA_ARGS__, NULL)
	286	#endif
14250520	287
7d75a871	288	#endif /* CONFIG_GPIOLIB_IRQCHIP */
14250520	289
c771c2f4 JG	290	int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
	291	void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
	292
964cb341 LW	293	#ifdef CONFIG_PINCTRL
	294
	295	/**
	296	* struct gpio_pin_range - pin range controlled by a gpio chip
	297	* @head: list for maintaining set of pin ranges, used internally
	298	* @pctldev: pinctrl device which handles corresponding pins
	299	* @range: actual range of pins controlled by a gpio controller
	300	*/
	301
	302	struct gpio_pin_range {
	303	struct list_head node;
	304	struct pinctrl_dev *pctldev;
	305	struct pinctrl_gpio_range range;
	306	};
	307
	308	int gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	309	unsigned int gpio_offset, unsigned int pin_offset,
	310	unsigned int npins);
	311	int gpiochip_add_pingroup_range(struct gpio_chip *chip,
	312	struct pinctrl_dev *pctldev,
	313	unsigned int gpio_offset, const char *pin_group);
	314	void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
	315
	316	#else
	317
	318	static inline int
	319	gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	320	unsigned int gpio_offset, unsigned int pin_offset,
	321	unsigned int npins)
	322	{
	323	return 0;
	324	}
	325	static inline int
	326	gpiochip_add_pingroup_range(struct gpio_chip *chip,
	327	struct pinctrl_dev *pctldev,
	328	unsigned int gpio_offset, const char *pin_group)
	329	{
	330	return 0;
	331	}
	332
	333	static inline void
	334	gpiochip_remove_pin_ranges(struct gpio_chip *chip)
	335	{
	336	}
	337
	338	#endif /* CONFIG_PINCTRL */
	339
abdc08a3 AC	340	struct gpio_desc gpiochip_request_own_desc(struct gpio_chip chip, u16 hwnum,
abdc08a3 AC	341	const char *label);
f7d4ad98 GR	342	void gpiochip_free_own_desc(struct gpio_desc *desc);
f7d4ad98 GR	343
bb1e88cc AC	344	#else /* CONFIG_GPIOLIB */
	345
	346	static inline struct gpio_chip gpiod_to_chip(const struct gpio_desc desc)
	347	{
	348	/* GPIO can never have been requested */
	349	WARN_ON(1);
	350	return ERR_PTR(-ENODEV);
	351	}
	352
	353	#endif /* CONFIG_GPIOLIB */
	354
79a9becd	355	#endif