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1da177e4 LT |
1 | /* |
2 | * I2O kernel space accessible structures/APIs | |
3 | * | |
4 | * (c) Copyright 1999, 2000 Red Hat Software | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | ************************************************************************* | |
12 | * | |
13 | * This header file defined the I2O APIs/structures for use by | |
14 | * the I2O kernel modules. | |
15 | * | |
16 | */ | |
17 | ||
18 | #ifndef _I2O_H | |
19 | #define _I2O_H | |
20 | ||
21 | #ifdef __KERNEL__ /* This file to be included by kernel only */ | |
22 | ||
23 | #include <linux/i2o-dev.h> | |
24 | ||
25 | /* How many different OSM's are we allowing */ | |
26 | #define I2O_MAX_DRIVERS 8 | |
27 | ||
28 | #include <asm/io.h> | |
29 | #include <asm/semaphore.h> /* Needed for MUTEX init macros */ | |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | ||
33 | /* message queue empty */ | |
34 | #define I2O_QUEUE_EMPTY 0xffffffff | |
35 | ||
36 | /* | |
37 | * Message structures | |
38 | */ | |
39 | struct i2o_message { | |
40 | union { | |
41 | struct { | |
42 | u8 version_offset; | |
43 | u8 flags; | |
44 | u16 size; | |
45 | u32 target_tid:12; | |
46 | u32 init_tid:12; | |
47 | u32 function:8; | |
48 | u32 icntxt; /* initiator context */ | |
49 | u32 tcntxt; /* transaction context */ | |
50 | } s; | |
51 | u32 head[4]; | |
52 | } u; | |
53 | /* List follows */ | |
54 | u32 body[0]; | |
55 | }; | |
56 | ||
57 | /* | |
58 | * Each I2O device entity has one of these. There is one per device. | |
59 | */ | |
60 | struct i2o_device { | |
61 | i2o_lct_entry lct_data; /* Device LCT information */ | |
62 | ||
63 | struct i2o_controller *iop; /* Controlling IOP */ | |
64 | struct list_head list; /* node in IOP devices list */ | |
65 | ||
66 | struct device device; | |
67 | ||
68 | struct semaphore lock; /* device lock */ | |
69 | ||
70 | struct class_device classdev; /* i2o device class */ | |
71 | }; | |
72 | ||
73 | /* | |
74 | * Event structure provided to the event handling function | |
75 | */ | |
76 | struct i2o_event { | |
77 | struct work_struct work; | |
78 | struct i2o_device *i2o_dev; /* I2O device pointer from which the | |
79 | event reply was initiated */ | |
80 | u16 size; /* Size of data in 32-bit words */ | |
81 | u32 tcntxt; /* Transaction context used at | |
82 | registration */ | |
83 | u32 event_indicator; /* Event indicator from reply */ | |
84 | u32 data[0]; /* Event data from reply */ | |
85 | }; | |
86 | ||
87 | /* | |
88 | * I2O classes which could be handled by the OSM | |
89 | */ | |
90 | struct i2o_class_id { | |
91 | u16 class_id:12; | |
92 | }; | |
93 | ||
94 | /* | |
95 | * I2O driver structure for OSMs | |
96 | */ | |
97 | struct i2o_driver { | |
98 | char *name; /* OSM name */ | |
99 | int context; /* Low 8 bits of the transaction info */ | |
100 | struct i2o_class_id *classes; /* I2O classes that this OSM handles */ | |
101 | ||
102 | /* Message reply handler */ | |
103 | int (*reply) (struct i2o_controller *, u32, struct i2o_message *); | |
104 | ||
105 | /* Event handler */ | |
106 | void (*event) (struct i2o_event *); | |
107 | ||
108 | struct workqueue_struct *event_queue; /* Event queue */ | |
109 | ||
110 | struct device_driver driver; | |
111 | ||
112 | /* notification of changes */ | |
113 | void (*notify_controller_add) (struct i2o_controller *); | |
114 | void (*notify_controller_remove) (struct i2o_controller *); | |
115 | void (*notify_device_add) (struct i2o_device *); | |
116 | void (*notify_device_remove) (struct i2o_device *); | |
117 | ||
118 | struct semaphore lock; | |
119 | }; | |
120 | ||
121 | /* | |
122 | * Contains all information which are necessary for DMA operations | |
123 | */ | |
124 | struct i2o_dma { | |
125 | void *virt; | |
126 | dma_addr_t phys; | |
127 | u32 len; | |
128 | }; | |
129 | ||
130 | /* | |
131 | * Context queue entry, used for 32-bit context on 64-bit systems | |
132 | */ | |
133 | struct i2o_context_list_element { | |
134 | struct list_head list; | |
135 | u32 context; | |
136 | void *ptr; | |
137 | unsigned long timestamp; | |
138 | }; | |
139 | ||
140 | /* | |
141 | * Each I2O controller has one of these objects | |
142 | */ | |
143 | struct i2o_controller { | |
144 | char name[16]; | |
145 | int unit; | |
146 | int type; | |
147 | ||
148 | struct pci_dev *pdev; /* PCI device */ | |
149 | ||
150 | unsigned int short_req:1; /* use small block sizes */ | |
151 | unsigned int no_quiesce:1; /* dont quiesce before reset */ | |
152 | unsigned int raptor:1; /* split bar */ | |
153 | unsigned int promise:1; /* Promise controller */ | |
154 | ||
1da177e4 | 155 | struct list_head devices; /* list of I2O devices */ |
1da177e4 | 156 | struct list_head list; /* Controller list */ |
f88e119c ML |
157 | |
158 | void __iomem *in_port; /* Inbout port address */ | |
159 | void __iomem *out_port; /* Outbound port address */ | |
1da177e4 LT |
160 | void __iomem *irq_mask; /* Interrupt register address */ |
161 | ||
162 | /* Dynamic LCT related data */ | |
163 | ||
164 | struct i2o_dma status; /* status of IOP */ | |
165 | ||
166 | struct i2o_dma hrt; /* HW Resource Table */ | |
167 | i2o_lct *lct; /* Logical Config Table */ | |
168 | struct i2o_dma dlct; /* Temp LCT */ | |
169 | struct semaphore lct_lock; /* Lock for LCT updates */ | |
170 | struct i2o_dma status_block; /* IOP status block */ | |
171 | ||
172 | struct i2o_dma base; /* controller messaging unit */ | |
173 | struct i2o_dma in_queue; /* inbound message queue Host->IOP */ | |
174 | struct i2o_dma out_queue; /* outbound message queue IOP->Host */ | |
175 | ||
176 | unsigned int battery:1; /* Has a battery backup */ | |
177 | unsigned int io_alloc:1; /* An I/O resource was allocated */ | |
178 | unsigned int mem_alloc:1; /* A memory resource was allocated */ | |
179 | ||
180 | struct resource io_resource; /* I/O resource allocated to the IOP */ | |
181 | struct resource mem_resource; /* Mem resource allocated to the IOP */ | |
182 | ||
1da177e4 LT |
183 | struct device device; |
184 | struct i2o_device *exec; /* Executive */ | |
185 | #if BITS_PER_LONG == 64 | |
186 | spinlock_t context_list_lock; /* lock for context_list */ | |
187 | atomic_t context_list_counter; /* needed for unique contexts */ | |
188 | struct list_head context_list; /* list of context id's | |
189 | and pointers */ | |
190 | #endif | |
191 | spinlock_t lock; /* lock for controller | |
192 | configuration */ | |
193 | ||
194 | void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */ | |
195 | }; | |
196 | ||
197 | /* | |
198 | * I2O System table entry | |
199 | * | |
200 | * The system table contains information about all the IOPs in the | |
201 | * system. It is sent to all IOPs so that they can create peer2peer | |
202 | * connections between them. | |
203 | */ | |
204 | struct i2o_sys_tbl_entry { | |
205 | u16 org_id; | |
206 | u16 reserved1; | |
207 | u32 iop_id:12; | |
208 | u32 reserved2:20; | |
209 | u16 seg_num:12; | |
210 | u16 i2o_version:4; | |
211 | u8 iop_state; | |
212 | u8 msg_type; | |
213 | u16 frame_size; | |
214 | u16 reserved3; | |
215 | u32 last_changed; | |
216 | u32 iop_capabilities; | |
217 | u32 inbound_low; | |
218 | u32 inbound_high; | |
219 | }; | |
220 | ||
221 | struct i2o_sys_tbl { | |
222 | u8 num_entries; | |
223 | u8 version; | |
224 | u16 reserved1; | |
225 | u32 change_ind; | |
226 | u32 reserved2; | |
227 | u32 reserved3; | |
228 | struct i2o_sys_tbl_entry iops[0]; | |
229 | }; | |
230 | ||
231 | extern struct list_head i2o_controllers; | |
232 | ||
233 | /* Message functions */ | |
234 | static inline u32 i2o_msg_get(struct i2o_controller *, struct i2o_message __iomem **); | |
235 | extern u32 i2o_msg_get_wait(struct i2o_controller *, struct i2o_message __iomem **, | |
236 | int); | |
237 | static inline void i2o_msg_post(struct i2o_controller *, u32); | |
238 | static inline int i2o_msg_post_wait(struct i2o_controller *, u32, | |
239 | unsigned long); | |
240 | extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long, | |
241 | struct i2o_dma *); | |
242 | extern void i2o_msg_nop(struct i2o_controller *, u32); | |
243 | static inline void i2o_flush_reply(struct i2o_controller *, u32); | |
244 | ||
245 | /* DMA handling functions */ | |
246 | static inline int i2o_dma_alloc(struct device *, struct i2o_dma *, size_t, | |
247 | unsigned int); | |
248 | static inline void i2o_dma_free(struct device *, struct i2o_dma *); | |
249 | int i2o_dma_realloc(struct device *, struct i2o_dma *, size_t, unsigned int); | |
250 | ||
251 | static inline int i2o_dma_map(struct device *, struct i2o_dma *); | |
252 | static inline void i2o_dma_unmap(struct device *, struct i2o_dma *); | |
253 | ||
254 | /* IOP functions */ | |
255 | extern int i2o_status_get(struct i2o_controller *); | |
256 | ||
257 | extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int, | |
258 | u32); | |
259 | extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16); | |
260 | extern struct i2o_controller *i2o_find_iop(int); | |
261 | ||
262 | /* Functions needed for handling 64-bit pointers in 32-bit context */ | |
263 | #if BITS_PER_LONG == 64 | |
264 | extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *); | |
265 | extern void *i2o_cntxt_list_get(struct i2o_controller *, u32); | |
266 | extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *); | |
267 | extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *); | |
268 | ||
269 | static inline u32 i2o_ptr_low(void *ptr) | |
270 | { | |
271 | return (u32) (u64) ptr; | |
272 | }; | |
273 | ||
274 | static inline u32 i2o_ptr_high(void *ptr) | |
275 | { | |
276 | return (u32) ((u64) ptr >> 32); | |
277 | }; | |
278 | #else | |
279 | static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr) | |
280 | { | |
281 | return (u32) ptr; | |
282 | }; | |
283 | ||
284 | static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context) | |
285 | { | |
286 | return (void *)context; | |
287 | }; | |
288 | ||
289 | static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr) | |
290 | { | |
291 | return (u32) ptr; | |
292 | }; | |
293 | ||
294 | static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr) | |
295 | { | |
296 | return (u32) ptr; | |
297 | }; | |
298 | ||
299 | static inline u32 i2o_ptr_low(void *ptr) | |
300 | { | |
301 | return (u32) ptr; | |
302 | }; | |
303 | ||
304 | static inline u32 i2o_ptr_high(void *ptr) | |
305 | { | |
306 | return 0; | |
307 | }; | |
308 | #endif | |
309 | ||
310 | /* I2O driver (OSM) functions */ | |
311 | extern int i2o_driver_register(struct i2o_driver *); | |
312 | extern void i2o_driver_unregister(struct i2o_driver *); | |
313 | ||
314 | /** | |
315 | * i2o_driver_notify_controller_add - Send notification of added controller | |
316 | * to a single I2O driver | |
317 | * | |
318 | * Send notification of added controller to a single registered driver. | |
319 | */ | |
320 | static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv, | |
321 | struct i2o_controller *c) | |
322 | { | |
323 | if (drv->notify_controller_add) | |
324 | drv->notify_controller_add(c); | |
325 | }; | |
326 | ||
327 | /** | |
328 | * i2o_driver_notify_controller_remove - Send notification of removed | |
329 | * controller to a single I2O driver | |
330 | * | |
331 | * Send notification of removed controller to a single registered driver. | |
332 | */ | |
333 | static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv, | |
334 | struct i2o_controller *c) | |
335 | { | |
336 | if (drv->notify_controller_remove) | |
337 | drv->notify_controller_remove(c); | |
338 | }; | |
339 | ||
340 | /** | |
341 | * i2o_driver_notify_device_add - Send notification of added device to a | |
342 | * single I2O driver | |
343 | * | |
344 | * Send notification of added device to a single registered driver. | |
345 | */ | |
346 | static inline void i2o_driver_notify_device_add(struct i2o_driver *drv, | |
347 | struct i2o_device *i2o_dev) | |
348 | { | |
349 | if (drv->notify_device_add) | |
350 | drv->notify_device_add(i2o_dev); | |
351 | }; | |
352 | ||
353 | /** | |
354 | * i2o_driver_notify_device_remove - Send notification of removed device | |
355 | * to a single I2O driver | |
356 | * | |
357 | * Send notification of removed device to a single registered driver. | |
358 | */ | |
359 | static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv, | |
360 | struct i2o_device *i2o_dev) | |
361 | { | |
362 | if (drv->notify_device_remove) | |
363 | drv->notify_device_remove(i2o_dev); | |
364 | }; | |
365 | ||
366 | extern void i2o_driver_notify_controller_add_all(struct i2o_controller *); | |
367 | extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *); | |
368 | extern void i2o_driver_notify_device_add_all(struct i2o_device *); | |
369 | extern void i2o_driver_notify_device_remove_all(struct i2o_device *); | |
370 | ||
371 | /* I2O device functions */ | |
372 | extern int i2o_device_claim(struct i2o_device *); | |
373 | extern int i2o_device_claim_release(struct i2o_device *); | |
374 | ||
375 | /* Exec OSM functions */ | |
376 | extern int i2o_exec_lct_get(struct i2o_controller *); | |
377 | ||
f88e119c | 378 | /* device / driver conversion functions */ |
1da177e4 LT |
379 | #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver) |
380 | #define to_i2o_device(dev) container_of(dev, struct i2o_device, device) | |
f88e119c | 381 | #define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device) |
1da177e4 LT |
382 | |
383 | /** | |
384 | * i2o_msg_get - obtain an I2O message from the IOP | |
385 | * @c: I2O controller | |
386 | * @msg: pointer to a I2O message pointer | |
387 | * | |
388 | * This function tries to get a message slot. If no message slot is | |
389 | * available do not wait until one is availabe (see also i2o_msg_get_wait). | |
390 | * | |
391 | * On a success the message is returned and the pointer to the message is | |
392 | * set in msg. The returned message is the physical page frame offset | |
393 | * address from the read port (see the i2o spec). If no message is | |
394 | * available returns I2O_QUEUE_EMPTY and msg is leaved untouched. | |
395 | */ | |
396 | static inline u32 i2o_msg_get(struct i2o_controller *c, | |
397 | struct i2o_message __iomem **msg) | |
398 | { | |
f88e119c | 399 | u32 m = readl(c->in_port); |
1da177e4 | 400 | |
f88e119c | 401 | if (m != I2O_QUEUE_EMPTY) { |
1da177e4 | 402 | *msg = c->in_queue.virt + m; |
f88e119c ML |
403 | rmb(); |
404 | } | |
1da177e4 LT |
405 | |
406 | return m; | |
407 | }; | |
408 | ||
409 | /** | |
410 | * i2o_msg_post - Post I2O message to I2O controller | |
411 | * @c: I2O controller to which the message should be send | |
412 | * @m: the message identifier | |
413 | * | |
414 | * Post the message to the I2O controller. | |
415 | */ | |
416 | static inline void i2o_msg_post(struct i2o_controller *c, u32 m) | |
417 | { | |
f88e119c ML |
418 | wmb(); |
419 | writel(m, c->in_port); | |
1da177e4 LT |
420 | }; |
421 | ||
422 | /** | |
423 | * i2o_msg_post_wait - Post and wait a message and wait until return | |
424 | * @c: controller | |
425 | * @m: message to post | |
426 | * @timeout: time in seconds to wait | |
427 | * | |
428 | * This API allows an OSM to post a message and then be told whether or | |
429 | * not the system received a successful reply. If the message times out | |
430 | * then the value '-ETIMEDOUT' is returned. | |
431 | * | |
432 | * Returns 0 on success or negative error code on failure. | |
433 | */ | |
434 | static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m, | |
435 | unsigned long timeout) | |
436 | { | |
437 | return i2o_msg_post_wait_mem(c, m, timeout, NULL); | |
438 | }; | |
439 | ||
440 | /** | |
441 | * i2o_flush_reply - Flush reply from I2O controller | |
442 | * @c: I2O controller | |
443 | * @m: the message identifier | |
444 | * | |
445 | * The I2O controller must be informed that the reply message is not needed | |
446 | * anymore. If you forget to flush the reply, the message frame can't be | |
447 | * used by the controller anymore and is therefore lost. | |
1da177e4 LT |
448 | */ |
449 | static inline void i2o_flush_reply(struct i2o_controller *c, u32 m) | |
450 | { | |
f88e119c | 451 | writel(m, c->out_port); |
1da177e4 LT |
452 | }; |
453 | ||
454 | /** | |
455 | * i2o_out_to_virt - Turn an I2O message to a virtual address | |
456 | * @c: controller | |
457 | * @m: message engine value | |
458 | * | |
459 | * Turn a receive message from an I2O controller bus address into | |
460 | * a Linux virtual address. The shared page frame is a linear block | |
461 | * so we simply have to shift the offset. This function does not | |
462 | * work for sender side messages as they are ioremap objects | |
463 | * provided by the I2O controller. | |
464 | */ | |
f88e119c ML |
465 | static inline struct i2o_message __iomem *i2o_msg_out_to_virt(struct |
466 | i2o_controller *c, | |
467 | u32 m) | |
1da177e4 LT |
468 | { |
469 | BUG_ON(m < c->out_queue.phys | |
470 | || m >= c->out_queue.phys + c->out_queue.len); | |
471 | ||
472 | return c->out_queue.virt + (m - c->out_queue.phys); | |
473 | }; | |
474 | ||
475 | /** | |
476 | * i2o_msg_in_to_virt - Turn an I2O message to a virtual address | |
477 | * @c: controller | |
478 | * @m: message engine value | |
479 | * | |
480 | * Turn a send message from an I2O controller bus address into | |
481 | * a Linux virtual address. The shared page frame is a linear block | |
482 | * so we simply have to shift the offset. This function does not | |
483 | * work for receive side messages as they are kmalloc objects | |
484 | * in a different pool. | |
485 | */ | |
486 | static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct i2o_controller *c, | |
487 | u32 m) | |
488 | { | |
489 | return c->in_queue.virt + m; | |
490 | }; | |
491 | ||
492 | /** | |
493 | * i2o_dma_alloc - Allocate DMA memory | |
494 | * @dev: struct device pointer to the PCI device of the I2O controller | |
495 | * @addr: i2o_dma struct which should get the DMA buffer | |
496 | * @len: length of the new DMA memory | |
497 | * @gfp_mask: GFP mask | |
498 | * | |
499 | * Allocate a coherent DMA memory and write the pointers into addr. | |
500 | * | |
501 | * Returns 0 on success or -ENOMEM on failure. | |
502 | */ | |
503 | static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, | |
504 | size_t len, unsigned int gfp_mask) | |
505 | { | |
506 | addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask); | |
507 | if (!addr->virt) | |
508 | return -ENOMEM; | |
509 | ||
510 | memset(addr->virt, 0, len); | |
511 | addr->len = len; | |
512 | ||
513 | return 0; | |
514 | }; | |
515 | ||
516 | /** | |
517 | * i2o_dma_free - Free DMA memory | |
518 | * @dev: struct device pointer to the PCI device of the I2O controller | |
519 | * @addr: i2o_dma struct which contains the DMA buffer | |
520 | * | |
521 | * Free a coherent DMA memory and set virtual address of addr to NULL. | |
522 | */ | |
523 | static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr) | |
524 | { | |
525 | if (addr->virt) { | |
526 | if (addr->phys) | |
527 | dma_free_coherent(dev, addr->len, addr->virt, | |
528 | addr->phys); | |
529 | else | |
530 | kfree(addr->virt); | |
531 | addr->virt = NULL; | |
532 | } | |
533 | }; | |
534 | ||
535 | /** | |
536 | * i2o_dma_map - Map the memory to DMA | |
537 | * @dev: struct device pointer to the PCI device of the I2O controller | |
538 | * @addr: i2o_dma struct which should be mapped | |
539 | * | |
540 | * Map the memory in addr->virt to coherent DMA memory and write the | |
541 | * physical address into addr->phys. | |
542 | * | |
543 | * Returns 0 on success or -ENOMEM on failure. | |
544 | */ | |
545 | static inline int i2o_dma_map(struct device *dev, struct i2o_dma *addr) | |
546 | { | |
547 | if (!addr->virt) | |
548 | return -EFAULT; | |
549 | ||
550 | if (!addr->phys) | |
551 | addr->phys = dma_map_single(dev, addr->virt, addr->len, | |
552 | DMA_BIDIRECTIONAL); | |
553 | if (!addr->phys) | |
554 | return -ENOMEM; | |
555 | ||
556 | return 0; | |
557 | }; | |
558 | ||
559 | /** | |
560 | * i2o_dma_unmap - Unmap the DMA memory | |
561 | * @dev: struct device pointer to the PCI device of the I2O controller | |
562 | * @addr: i2o_dma struct which should be unmapped | |
563 | * | |
564 | * Unmap the memory in addr->virt from DMA memory. | |
565 | */ | |
566 | static inline void i2o_dma_unmap(struct device *dev, struct i2o_dma *addr) | |
567 | { | |
568 | if (!addr->virt) | |
569 | return; | |
570 | ||
571 | if (addr->phys) { | |
572 | dma_unmap_single(dev, addr->phys, addr->len, DMA_BIDIRECTIONAL); | |
573 | addr->phys = 0; | |
574 | } | |
575 | }; | |
576 | ||
577 | /* | |
578 | * Endian handling wrapped into the macro - keeps the core code | |
579 | * cleaner. | |
580 | */ | |
581 | ||
582 | #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem) | |
583 | ||
584 | extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int); | |
585 | extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int, | |
586 | void *, int); | |
587 | ||
588 | /* debugging and troubleshooting/diagnostic helpers. */ | |
589 | #define osm_printk(level, format, arg...) \ | |
590 | printk(level "%s: " format, OSM_NAME , ## arg) | |
591 | ||
592 | #ifdef DEBUG | |
593 | #define osm_debug(format, arg...) \ | |
594 | osm_printk(KERN_DEBUG, format , ## arg) | |
595 | #else | |
596 | #define osm_debug(format, arg...) \ | |
597 | do { } while (0) | |
598 | #endif | |
599 | ||
600 | #define osm_err(format, arg...) \ | |
601 | osm_printk(KERN_ERR, format , ## arg) | |
602 | #define osm_info(format, arg...) \ | |
603 | osm_printk(KERN_INFO, format , ## arg) | |
604 | #define osm_warn(format, arg...) \ | |
605 | osm_printk(KERN_WARNING, format , ## arg) | |
606 | ||
607 | /* debugging functions */ | |
608 | extern void i2o_report_status(const char *, const char *, struct i2o_message *); | |
609 | extern void i2o_dump_message(struct i2o_message *); | |
610 | extern void i2o_dump_hrt(struct i2o_controller *c); | |
611 | extern void i2o_debug_state(struct i2o_controller *c); | |
612 | ||
613 | /* | |
614 | * Cache strategies | |
615 | */ | |
616 | ||
617 | /* The NULL strategy leaves everything up to the controller. This tends to be a | |
618 | * pessimal but functional choice. | |
619 | */ | |
620 | #define CACHE_NULL 0 | |
621 | /* Prefetch data when reading. We continually attempt to load the next 32 sectors | |
622 | * into the controller cache. | |
623 | */ | |
624 | #define CACHE_PREFETCH 1 | |
625 | /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors | |
626 | * into the controller cache. When an I/O is less <= 8K we assume its probably | |
627 | * not sequential and don't prefetch (default) | |
628 | */ | |
629 | #define CACHE_SMARTFETCH 2 | |
630 | /* Data is written to the cache and then out on to the disk. The I/O must be | |
631 | * physically on the medium before the write is acknowledged (default without | |
632 | * NVRAM) | |
633 | */ | |
634 | #define CACHE_WRITETHROUGH 17 | |
635 | /* Data is written to the cache and then out on to the disk. The controller | |
636 | * is permitted to write back the cache any way it wants. (default if battery | |
637 | * backed NVRAM is present). It can be useful to set this for swap regardless of | |
638 | * battery state. | |
639 | */ | |
640 | #define CACHE_WRITEBACK 18 | |
641 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We | |
642 | * write large I/O's directly to disk bypassing the cache to avoid the extra | |
643 | * memory copy hits. Small writes are writeback cached | |
644 | */ | |
645 | #define CACHE_SMARTBACK 19 | |
646 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We | |
647 | * write large I/O's directly to disk bypassing the cache to avoid the extra | |
648 | * memory copy hits. Small writes are writethrough cached. Suitable for devices | |
649 | * lacking battery backup | |
650 | */ | |
651 | #define CACHE_SMARTTHROUGH 20 | |
652 | ||
653 | /* | |
654 | * Ioctl structures | |
655 | */ | |
656 | ||
657 | #define BLKI2OGRSTRAT _IOR('2', 1, int) | |
658 | #define BLKI2OGWSTRAT _IOR('2', 2, int) | |
659 | #define BLKI2OSRSTRAT _IOW('2', 3, int) | |
660 | #define BLKI2OSWSTRAT _IOW('2', 4, int) | |
661 | ||
662 | /* | |
663 | * I2O Function codes | |
664 | */ | |
665 | ||
666 | /* | |
667 | * Executive Class | |
668 | */ | |
669 | #define I2O_CMD_ADAPTER_ASSIGN 0xB3 | |
670 | #define I2O_CMD_ADAPTER_READ 0xB2 | |
671 | #define I2O_CMD_ADAPTER_RELEASE 0xB5 | |
672 | #define I2O_CMD_BIOS_INFO_SET 0xA5 | |
673 | #define I2O_CMD_BOOT_DEVICE_SET 0xA7 | |
674 | #define I2O_CMD_CONFIG_VALIDATE 0xBB | |
675 | #define I2O_CMD_CONN_SETUP 0xCA | |
676 | #define I2O_CMD_DDM_DESTROY 0xB1 | |
677 | #define I2O_CMD_DDM_ENABLE 0xD5 | |
678 | #define I2O_CMD_DDM_QUIESCE 0xC7 | |
679 | #define I2O_CMD_DDM_RESET 0xD9 | |
680 | #define I2O_CMD_DDM_SUSPEND 0xAF | |
681 | #define I2O_CMD_DEVICE_ASSIGN 0xB7 | |
682 | #define I2O_CMD_DEVICE_RELEASE 0xB9 | |
683 | #define I2O_CMD_HRT_GET 0xA8 | |
684 | #define I2O_CMD_ADAPTER_CLEAR 0xBE | |
685 | #define I2O_CMD_ADAPTER_CONNECT 0xC9 | |
686 | #define I2O_CMD_ADAPTER_RESET 0xBD | |
687 | #define I2O_CMD_LCT_NOTIFY 0xA2 | |
688 | #define I2O_CMD_OUTBOUND_INIT 0xA1 | |
689 | #define I2O_CMD_PATH_ENABLE 0xD3 | |
690 | #define I2O_CMD_PATH_QUIESCE 0xC5 | |
691 | #define I2O_CMD_PATH_RESET 0xD7 | |
692 | #define I2O_CMD_STATIC_MF_CREATE 0xDD | |
693 | #define I2O_CMD_STATIC_MF_RELEASE 0xDF | |
694 | #define I2O_CMD_STATUS_GET 0xA0 | |
695 | #define I2O_CMD_SW_DOWNLOAD 0xA9 | |
696 | #define I2O_CMD_SW_UPLOAD 0xAB | |
697 | #define I2O_CMD_SW_REMOVE 0xAD | |
698 | #define I2O_CMD_SYS_ENABLE 0xD1 | |
699 | #define I2O_CMD_SYS_MODIFY 0xC1 | |
700 | #define I2O_CMD_SYS_QUIESCE 0xC3 | |
701 | #define I2O_CMD_SYS_TAB_SET 0xA3 | |
702 | ||
703 | /* | |
704 | * Utility Class | |
705 | */ | |
706 | #define I2O_CMD_UTIL_NOP 0x00 | |
707 | #define I2O_CMD_UTIL_ABORT 0x01 | |
708 | #define I2O_CMD_UTIL_CLAIM 0x09 | |
709 | #define I2O_CMD_UTIL_RELEASE 0x0B | |
710 | #define I2O_CMD_UTIL_PARAMS_GET 0x06 | |
711 | #define I2O_CMD_UTIL_PARAMS_SET 0x05 | |
712 | #define I2O_CMD_UTIL_EVT_REGISTER 0x13 | |
713 | #define I2O_CMD_UTIL_EVT_ACK 0x14 | |
714 | #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10 | |
715 | #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D | |
716 | #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F | |
717 | #define I2O_CMD_UTIL_LOCK 0x17 | |
718 | #define I2O_CMD_UTIL_LOCK_RELEASE 0x19 | |
719 | #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15 | |
720 | ||
721 | /* | |
722 | * SCSI Host Bus Adapter Class | |
723 | */ | |
724 | #define I2O_CMD_SCSI_EXEC 0x81 | |
725 | #define I2O_CMD_SCSI_ABORT 0x83 | |
726 | #define I2O_CMD_SCSI_BUSRESET 0x27 | |
727 | ||
728 | /* | |
729 | * Random Block Storage Class | |
730 | */ | |
731 | #define I2O_CMD_BLOCK_READ 0x30 | |
732 | #define I2O_CMD_BLOCK_WRITE 0x31 | |
733 | #define I2O_CMD_BLOCK_CFLUSH 0x37 | |
734 | #define I2O_CMD_BLOCK_MLOCK 0x49 | |
735 | #define I2O_CMD_BLOCK_MUNLOCK 0x4B | |
736 | #define I2O_CMD_BLOCK_MMOUNT 0x41 | |
737 | #define I2O_CMD_BLOCK_MEJECT 0x43 | |
738 | #define I2O_CMD_BLOCK_POWER 0x70 | |
739 | ||
740 | #define I2O_PRIVATE_MSG 0xFF | |
741 | ||
742 | /* Command status values */ | |
743 | ||
744 | #define I2O_CMD_IN_PROGRESS 0x01 | |
745 | #define I2O_CMD_REJECTED 0x02 | |
746 | #define I2O_CMD_FAILED 0x03 | |
747 | #define I2O_CMD_COMPLETED 0x04 | |
748 | ||
749 | /* I2O API function return values */ | |
750 | ||
751 | #define I2O_RTN_NO_ERROR 0 | |
752 | #define I2O_RTN_NOT_INIT 1 | |
753 | #define I2O_RTN_FREE_Q_EMPTY 2 | |
754 | #define I2O_RTN_TCB_ERROR 3 | |
755 | #define I2O_RTN_TRANSACTION_ERROR 4 | |
756 | #define I2O_RTN_ADAPTER_ALREADY_INIT 5 | |
757 | #define I2O_RTN_MALLOC_ERROR 6 | |
758 | #define I2O_RTN_ADPTR_NOT_REGISTERED 7 | |
759 | #define I2O_RTN_MSG_REPLY_TIMEOUT 8 | |
760 | #define I2O_RTN_NO_STATUS 9 | |
761 | #define I2O_RTN_NO_FIRM_VER 10 | |
762 | #define I2O_RTN_NO_LINK_SPEED 11 | |
763 | ||
764 | /* Reply message status defines for all messages */ | |
765 | ||
766 | #define I2O_REPLY_STATUS_SUCCESS 0x00 | |
767 | #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01 | |
768 | #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02 | |
769 | #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03 | |
770 | #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04 | |
771 | #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05 | |
772 | #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06 | |
773 | #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08 | |
774 | #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09 | |
775 | #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A | |
776 | #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B | |
777 | #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80 | |
778 | ||
779 | /* Status codes and Error Information for Parameter functions */ | |
780 | ||
781 | #define I2O_PARAMS_STATUS_SUCCESS 0x00 | |
782 | #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01 | |
783 | #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02 | |
784 | #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03 | |
785 | #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04 | |
786 | #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05 | |
787 | #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06 | |
788 | #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07 | |
789 | #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08 | |
790 | #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09 | |
791 | #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A | |
792 | #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B | |
793 | #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C | |
794 | #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D | |
795 | #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E | |
796 | #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F | |
797 | #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10 | |
798 | ||
799 | /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error | |
800 | * messages: Table 3-2 Detailed Status Codes.*/ | |
801 | ||
802 | #define I2O_DSC_SUCCESS 0x0000 | |
803 | #define I2O_DSC_BAD_KEY 0x0002 | |
804 | #define I2O_DSC_TCL_ERROR 0x0003 | |
805 | #define I2O_DSC_REPLY_BUFFER_FULL 0x0004 | |
806 | #define I2O_DSC_NO_SUCH_PAGE 0x0005 | |
807 | #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006 | |
808 | #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007 | |
809 | #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009 | |
810 | #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A | |
811 | #define I2O_DSC_DEVICE_LOCKED 0x000B | |
812 | #define I2O_DSC_DEVICE_RESET 0x000C | |
813 | #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D | |
814 | #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E | |
815 | #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F | |
816 | #define I2O_DSC_INVALID_OFFSET 0x0010 | |
817 | #define I2O_DSC_INVALID_PARAMETER 0x0011 | |
818 | #define I2O_DSC_INVALID_REQUEST 0x0012 | |
819 | #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013 | |
820 | #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014 | |
821 | #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015 | |
822 | #define I2O_DSC_MISSING_PARAMETER 0x0016 | |
823 | #define I2O_DSC_TIMEOUT 0x0017 | |
824 | #define I2O_DSC_UNKNOWN_ERROR 0x0018 | |
825 | #define I2O_DSC_UNKNOWN_FUNCTION 0x0019 | |
826 | #define I2O_DSC_UNSUPPORTED_VERSION 0x001A | |
827 | #define I2O_DSC_DEVICE_BUSY 0x001B | |
828 | #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C | |
829 | ||
830 | /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed | |
831 | Status Codes.*/ | |
832 | ||
833 | #define I2O_BSA_DSC_SUCCESS 0x0000 | |
834 | #define I2O_BSA_DSC_MEDIA_ERROR 0x0001 | |
835 | #define I2O_BSA_DSC_ACCESS_ERROR 0x0002 | |
836 | #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003 | |
837 | #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004 | |
838 | #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005 | |
839 | #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006 | |
840 | #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007 | |
841 | #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008 | |
842 | #define I2O_BSA_DSC_BUS_FAILURE 0x0009 | |
843 | #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A | |
844 | #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B | |
845 | #define I2O_BSA_DSC_DEVICE_RESET 0x000C | |
846 | #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D | |
847 | #define I2O_BSA_DSC_TIMEOUT 0x000E | |
848 | ||
849 | /* FailureStatusCodes, Table 3-3 Message Failure Codes */ | |
850 | ||
851 | #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81 | |
852 | #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82 | |
853 | #define I2O_FSC_TRANSPORT_CONGESTION 0x83 | |
854 | #define I2O_FSC_TRANSPORT_FAILURE 0x84 | |
855 | #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85 | |
856 | #define I2O_FSC_TRANSPORT_TIME_OUT 0x86 | |
857 | #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87 | |
858 | #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88 | |
859 | #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89 | |
860 | #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A | |
861 | #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B | |
862 | #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C | |
863 | #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D | |
864 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E | |
865 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F | |
866 | #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF | |
867 | ||
868 | /* Device Claim Types */ | |
869 | #define I2O_CLAIM_PRIMARY 0x01000000 | |
870 | #define I2O_CLAIM_MANAGEMENT 0x02000000 | |
871 | #define I2O_CLAIM_AUTHORIZED 0x03000000 | |
872 | #define I2O_CLAIM_SECONDARY 0x04000000 | |
873 | ||
874 | /* Message header defines for VersionOffset */ | |
875 | #define I2OVER15 0x0001 | |
876 | #define I2OVER20 0x0002 | |
877 | ||
f88e119c | 878 | /* Default is 1.5 */ |
1da177e4 LT |
879 | #define I2OVERSION I2OVER15 |
880 | ||
881 | #define SGL_OFFSET_0 I2OVERSION | |
882 | #define SGL_OFFSET_4 (0x0040 | I2OVERSION) | |
883 | #define SGL_OFFSET_5 (0x0050 | I2OVERSION) | |
884 | #define SGL_OFFSET_6 (0x0060 | I2OVERSION) | |
885 | #define SGL_OFFSET_7 (0x0070 | I2OVERSION) | |
886 | #define SGL_OFFSET_8 (0x0080 | I2OVERSION) | |
887 | #define SGL_OFFSET_9 (0x0090 | I2OVERSION) | |
888 | #define SGL_OFFSET_10 (0x00A0 | I2OVERSION) | |
889 | ||
890 | #define TRL_OFFSET_5 (0x0050 | I2OVERSION) | |
891 | #define TRL_OFFSET_6 (0x0060 | I2OVERSION) | |
892 | ||
893 | /* Transaction Reply Lists (TRL) Control Word structure */ | |
894 | #define TRL_SINGLE_FIXED_LENGTH 0x00 | |
895 | #define TRL_SINGLE_VARIABLE_LENGTH 0x40 | |
896 | #define TRL_MULTIPLE_FIXED_LENGTH 0x80 | |
897 | ||
898 | /* msg header defines for MsgFlags */ | |
899 | #define MSG_STATIC 0x0100 | |
900 | #define MSG_64BIT_CNTXT 0x0200 | |
901 | #define MSG_MULTI_TRANS 0x1000 | |
902 | #define MSG_FAIL 0x2000 | |
903 | #define MSG_FINAL 0x4000 | |
904 | #define MSG_REPLY 0x8000 | |
905 | ||
906 | /* minimum size msg */ | |
907 | #define THREE_WORD_MSG_SIZE 0x00030000 | |
908 | #define FOUR_WORD_MSG_SIZE 0x00040000 | |
909 | #define FIVE_WORD_MSG_SIZE 0x00050000 | |
910 | #define SIX_WORD_MSG_SIZE 0x00060000 | |
911 | #define SEVEN_WORD_MSG_SIZE 0x00070000 | |
912 | #define EIGHT_WORD_MSG_SIZE 0x00080000 | |
913 | #define NINE_WORD_MSG_SIZE 0x00090000 | |
914 | #define TEN_WORD_MSG_SIZE 0x000A0000 | |
915 | #define ELEVEN_WORD_MSG_SIZE 0x000B0000 | |
916 | #define I2O_MESSAGE_SIZE(x) ((x)<<16) | |
917 | ||
918 | /* Special TID Assignments */ | |
919 | ||
920 | #define ADAPTER_TID 0 | |
921 | #define HOST_TID 1 | |
922 | ||
923 | #define MSG_FRAME_SIZE 128 /* i2o_scsi assumes >= 32 */ | |
924 | #define REPLY_FRAME_SIZE 17 | |
925 | #define SG_TABLESIZE 30 | |
926 | #define NMBR_MSG_FRAMES 128 | |
927 | ||
928 | #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32)) | |
929 | ||
930 | #define I2O_POST_WAIT_OK 0 | |
931 | #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT | |
932 | ||
933 | #define I2O_CONTEXT_LIST_MIN_LENGTH 15 | |
934 | #define I2O_CONTEXT_LIST_USED 0x01 | |
935 | #define I2O_CONTEXT_LIST_DELETED 0x02 | |
936 | ||
937 | /* timeouts */ | |
938 | #define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15 | |
939 | #define I2O_TIMEOUT_MESSAGE_GET 5 | |
940 | #define I2O_TIMEOUT_RESET 30 | |
941 | #define I2O_TIMEOUT_STATUS_GET 5 | |
942 | #define I2O_TIMEOUT_LCT_GET 360 | |
943 | #define I2O_TIMEOUT_SCSI_SCB_ABORT 240 | |
944 | ||
945 | /* retries */ | |
946 | #define I2O_HRT_GET_TRIES 3 | |
947 | #define I2O_LCT_GET_TRIES 3 | |
948 | ||
949 | /* request queue sizes */ | |
950 | #define I2O_MAX_SECTORS 1024 | |
951 | #define I2O_MAX_SEGMENTS 128 | |
952 | ||
953 | #define I2O_REQ_MEMPOOL_SIZE 32 | |
954 | ||
955 | #endif /* __KERNEL__ */ | |
956 | #endif /* _I2O_H */ |