[deliverable/linux.git] / include / linux / intel-iommu.h

/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * Copyright (C) 2006-2008 Intel Corporation
 * Author: Ashok Raj <ashok.raj@intel.com>
 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
 */

#ifndef _INTEL_IOMMU_H_
#define _INTEL_IOMMU_H_

#include <linux/types.h>
#include <linux/iova.h>
#include <linux/io.h>
#include <linux/dma_remapping.h>
#include <asm/cacheflush.h>
#include <asm/iommu.h>

/*
 * Intel IOMMU register specification per version 1.0 public spec.
 */

#define	DMAR_VER_REG	0x0	/* Arch version supported by this IOMMU */
#define	DMAR_CAP_REG	0x8	/* Hardware supported capabilities */
#define	DMAR_ECAP_REG	0x10	/* Extended capabilities supported */
#define	DMAR_GCMD_REG	0x18	/* Global command register */
#define	DMAR_GSTS_REG	0x1c	/* Global status register */
#define	DMAR_RTADDR_REG	0x20	/* Root entry table */
#define	DMAR_CCMD_REG	0x28	/* Context command reg */
#define	DMAR_FSTS_REG	0x34	/* Fault Status register */
#define	DMAR_FECTL_REG	0x38	/* Fault control register */
#define	DMAR_FEDATA_REG	0x3c	/* Fault event interrupt data register */
#define	DMAR_FEADDR_REG	0x40	/* Fault event interrupt addr register */
#define	DMAR_FEUADDR_REG 0x44	/* Upper address register */
#define	DMAR_AFLOG_REG	0x58	/* Advanced Fault control */
#define	DMAR_PMEN_REG	0x64	/* Enable Protected Memory Region */
#define	DMAR_PLMBASE_REG 0x68	/* PMRR Low addr */
#define	DMAR_PLMLIMIT_REG 0x6c	/* PMRR low limit */
#define	DMAR_PHMBASE_REG 0x70	/* pmrr high base addr */
#define	DMAR_PHMLIMIT_REG 0x78	/* pmrr high limit */
#define DMAR_IQH_REG	0x80	/* Invalidation queue head register */
#define DMAR_IQT_REG	0x88	/* Invalidation queue tail register */
#define DMAR_IQA_REG	0x90	/* Invalidation queue addr register */
#define DMAR_ICS_REG	0x98	/* Invalidation complete status register */
#define DMAR_IRTA_REG	0xb8    /* Interrupt remapping table addr register */

#define OFFSET_STRIDE		(9)
/*
#define dmar_readl(dmar, reg) readl(dmar + reg)
#define dmar_readq(dmar, reg) ({ \
		u32 lo, hi; \
		lo = readl(dmar + reg); \
		hi = readl(dmar + reg + 4); \
		(((u64) hi) << 32) + lo; })
*/
static inline u64 dmar_readq(void __iomem *addr)
{
	u32 lo, hi;
	lo = readl(addr);
	hi = readl(addr + 4);
	return (((u64) hi) << 32) + lo;
}

static inline void dmar_writeq(void __iomem *addr, u64 val)
{
	writel((u32)val, addr);
	writel((u32)(val >> 32), addr + 4);
}

#define DMAR_VER_MAJOR(v)		(((v) & 0xf0) >> 4)
#define DMAR_VER_MINOR(v)		((v) & 0x0f)

/*
 * Decoding Capability Register
 */
#define cap_read_drain(c)	(((c) >> 55) & 1)
#define cap_write_drain(c)	(((c) >> 54) & 1)
#define cap_max_amask_val(c)	(((c) >> 48) & 0x3f)
#define cap_num_fault_regs(c)	((((c) >> 40) & 0xff) + 1)
#define cap_pgsel_inv(c)	(((c) >> 39) & 1)

#define cap_super_page_val(c)	(((c) >> 34) & 0xf)
#define cap_super_offset(c)	(((find_first_bit(&cap_super_page_val(c), 4)) \
					* OFFSET_STRIDE) + 21)

#define cap_fault_reg_offset(c)	((((c) >> 24) & 0x3ff) * 16)
#define cap_max_fault_reg_offset(c) \
	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)

#define cap_zlr(c)		(((c) >> 22) & 1)
#define cap_isoch(c)		(((c) >> 23) & 1)
#define cap_mgaw(c)		((((c) >> 16) & 0x3f) + 1)
#define cap_sagaw(c)		(((c) >> 8) & 0x1f)
#define cap_caching_mode(c)	(((c) >> 7) & 1)
#define cap_phmr(c)		(((c) >> 6) & 1)
#define cap_plmr(c)		(((c) >> 5) & 1)
#define cap_rwbf(c)		(((c) >> 4) & 1)
#define cap_afl(c)		(((c) >> 3) & 1)
#define cap_ndoms(c)		(((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
/*
 * Extended Capability Register
 */

#define ecap_niotlb_iunits(e)	((((e) >> 24) & 0xff) + 1)
#define ecap_iotlb_offset(e) 	((((e) >> 8) & 0x3ff) * 16)
#define ecap_max_iotlb_offset(e) \
	(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
#define ecap_coherent(e)	((e) & 0x1)
#define ecap_qis(e)		((e) & 0x2)
#define ecap_eim_support(e)	((e >> 4) & 0x1)
#define ecap_ir_support(e)	((e >> 3) & 0x1)
#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
#define ecap_sc_support(e)	((e >> 7) & 0x1) /* Snooping Control */

/* IOTLB_REG */
#define DMA_TLB_FLUSH_GRANU_OFFSET  60
#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
#define DMA_TLB_DID(id)	(((u64)((id) & 0xffff)) << 32)
#define DMA_TLB_IVT (((u64)1) << 63)
#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
#define DMA_TLB_MAX_SIZE (0x3f)

/* INVALID_DESC */
#define DMA_CCMD_INVL_GRANU_OFFSET  61
#define DMA_ID_TLB_GLOBAL_FLUSH	(((u64)1) << 3)
#define DMA_ID_TLB_DSI_FLUSH	(((u64)2) << 3)
#define DMA_ID_TLB_PSI_FLUSH	(((u64)3) << 3)
#define DMA_ID_TLB_READ_DRAIN	(((u64)1) << 7)
#define DMA_ID_TLB_WRITE_DRAIN	(((u64)1) << 6)
#define DMA_ID_TLB_DID(id)	(((u64)((id & 0xffff) << 16)))
#define DMA_ID_TLB_IH_NONLEAF	(((u64)1) << 6)
#define DMA_ID_TLB_ADDR(addr)	(addr)
#define DMA_ID_TLB_ADDR_MASK(mask)	(mask)

/* PMEN_REG */
#define DMA_PMEN_EPM (((u32)1)<<31)
#define DMA_PMEN_PRS (((u32)1)<<0)

/* GCMD_REG */
#define DMA_GCMD_TE (((u32)1) << 31)
#define DMA_GCMD_SRTP (((u32)1) << 30)
#define DMA_GCMD_SFL (((u32)1) << 29)
#define DMA_GCMD_EAFL (((u32)1) << 28)
#define DMA_GCMD_WBF (((u32)1) << 27)
#define DMA_GCMD_QIE (((u32)1) << 26)
#define DMA_GCMD_SIRTP (((u32)1) << 24)
#define DMA_GCMD_IRE (((u32) 1) << 25)
#define DMA_GCMD_CFI (((u32) 1) << 23)

/* GSTS_REG */
#define DMA_GSTS_TES (((u32)1) << 31)
#define DMA_GSTS_RTPS (((u32)1) << 30)
#define DMA_GSTS_FLS (((u32)1) << 29)
#define DMA_GSTS_AFLS (((u32)1) << 28)
#define DMA_GSTS_WBFS (((u32)1) << 27)
#define DMA_GSTS_QIES (((u32)1) << 26)
#define DMA_GSTS_IRTPS (((u32)1) << 24)
#define DMA_GSTS_IRES (((u32)1) << 25)
#define DMA_GSTS_CFIS (((u32)1) << 23)

/* CCMD_REG */
#define DMA_CCMD_ICC (((u64)1) << 63)
#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
#define DMA_CCMD_MASK_NOBIT 0
#define DMA_CCMD_MASK_1BIT 1
#define DMA_CCMD_MASK_2BIT 2
#define DMA_CCMD_MASK_3BIT 3
#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))

/* FECTL_REG */
#define DMA_FECTL_IM (((u32)1) << 31)

/* FSTS_REG */
#define DMA_FSTS_PPF ((u32)2)
#define DMA_FSTS_PFO ((u32)1)
#define DMA_FSTS_IQE (1 << 4)
#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)

/* FRCD_REG, 32 bits access */
#define DMA_FRCD_F (((u32)1) << 31)
#define dma_frcd_type(d) ((d >> 30) & 1)
#define dma_frcd_fault_reason(c) (c & 0xff)
#define dma_frcd_source_id(c) (c & 0xffff)
/* low 64 bit */
#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))

#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)			\
do {									\
	cycles_t start_time = get_cycles();				\
	while (1) {							\
		sts = op(iommu->reg + offset);				\
		if (cond)						\
			break;						\
		if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
			panic("DMAR hardware is malfunctioning\n");	\
		cpu_relax();						\
	}								\
} while (0)

#define QI_LENGTH	256	/* queue length */

enum {
	QI_FREE,
	QI_IN_USE,
	QI_DONE
};

#define QI_CC_TYPE		0x1
#define QI_IOTLB_TYPE		0x2
#define QI_DIOTLB_TYPE		0x3
#define QI_IEC_TYPE		0x4
#define QI_IWD_TYPE		0x5

#define QI_IEC_SELECTIVE	(((u64)1) << 4)
#define QI_IEC_IIDEX(idx)	(((u64)(idx & 0xffff) << 32))
#define QI_IEC_IM(m)		(((u64)(m & 0x1f) << 27))

#define QI_IWD_STATUS_DATA(d)	(((u64)d) << 32)
#define QI_IWD_STATUS_WRITE	(((u64)1) << 5)

#define QI_IOTLB_DID(did) 	(((u64)did) << 16)
#define QI_IOTLB_DR(dr) 	(((u64)dr) << 7)
#define QI_IOTLB_DW(dw) 	(((u64)dw) << 6)
#define QI_IOTLB_GRAN(gran) 	(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
#define QI_IOTLB_ADDR(addr)	(((u64)addr) & VTD_PAGE_MASK)
#define QI_IOTLB_IH(ih)		(((u64)ih) << 6)
#define QI_IOTLB_AM(am)		(((u8)am))

#define QI_CC_FM(fm)		(((u64)fm) << 48)
#define QI_CC_SID(sid)		(((u64)sid) << 32)
#define QI_CC_DID(did)		(((u64)did) << 16)
#define QI_CC_GRAN(gran)	(((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))

struct qi_desc {
	u64 low, high;
};

struct q_inval {
	spinlock_t      q_lock;
	struct qi_desc  *desc;          /* invalidation queue */
	int             *desc_status;   /* desc status */
	int             free_head;      /* first free entry */
	int             free_tail;      /* last free entry */
	int             free_cnt;
};

#ifdef CONFIG_INTR_REMAP
/* 1MB - maximum possible interrupt remapping table size */
#define INTR_REMAP_PAGE_ORDER	8
#define INTR_REMAP_TABLE_REG_SIZE	0xf

#define INTR_REMAP_TABLE_ENTRIES	65536

struct ir_table {
	struct irte *base;
};
#endif

struct iommu_flush {
	int (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
		u64 type, int non_present_entry_flush);
	int (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
		unsigned int size_order, u64 type, int non_present_entry_flush);
};

enum {
	SR_DMAR_FECTL_REG,
	SR_DMAR_FEDATA_REG,
	SR_DMAR_FEADDR_REG,
	SR_DMAR_FEUADDR_REG,
	MAX_SR_DMAR_REGS
};

struct intel_iommu {
	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
	u64		cap;
	u64		ecap;
	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
	spinlock_t	register_lock; /* protect register handling */
	int		seq_id;	/* sequence id of the iommu */
	int		agaw; /* agaw of this iommu */
	unsigned int 	irq;
	unsigned char 	name[13];    /* Device Name */

#ifdef CONFIG_DMAR
	unsigned long 	*domain_ids; /* bitmap of domains */
	struct dmar_domain **domains; /* ptr to domains */
	spinlock_t	lock; /* protect context, domain ids */
	struct root_entry *root_entry; /* virtual address */

	struct iommu_flush flush;
#endif
	struct q_inval  *qi;            /* Queued invalidation info */
	u32 *iommu_state; /* Store iommu states between suspend and resume.*/

#ifdef CONFIG_INTR_REMAP
	struct ir_table *ir_table;	/* Interrupt remapping info */
#endif
};

static inline void __iommu_flush_cache(
	struct intel_iommu *iommu, void *addr, int size)
{
	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(addr, size);
}

extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);

extern int alloc_iommu(struct dmar_drhd_unit *drhd);
extern void free_iommu(struct intel_iommu *iommu);
extern int dmar_enable_qi(struct intel_iommu *iommu);
extern void dmar_disable_qi(struct intel_iommu *iommu);
extern int dmar_reenable_qi(struct intel_iommu *iommu);
extern void qi_global_iec(struct intel_iommu *iommu);

extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
			        u8 fm, u64 type, int non_present_entry_flush);
extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
			  unsigned int size_order, u64 type,
			  int non_present_entry_flush);

extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);

#endif
Commit	Line	Data
ba395927 KA	1	/*
	2	* Copyright (c) 2006, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	15	* Place - Suite 330, Boston, MA 02111-1307 USA.
	16	*
98bcef56	17	* Copyright (C) 2006-2008 Intel Corporation
	18	* Author: Ashok Raj <ashok.raj@intel.com>
	19	* Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
ba395927 KA	20	*/
	21
	22	#ifndef _INTEL_IOMMU_H_
	23	#define _INTEL_IOMMU_H_
	24
	25	#include <linux/types.h>
38717946	26	#include <linux/iova.h>
ba395927	27	#include <linux/io.h>
38717946	28	#include <linux/dma_remapping.h>
fe962e90	29	#include <asm/cacheflush.h>
5b6985ce	30	#include <asm/iommu.h>
f661197e	31
ba395927 KA	32	/*
	33	* Intel IOMMU register specification per version 1.0 public spec.
	34	*/
	35
	36	#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
	37	#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
	38	#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
	39	#define DMAR_GCMD_REG 0x18 /* Global command register */
	40	#define DMAR_GSTS_REG 0x1c /* Global status register */
	41	#define DMAR_RTADDR_REG 0x20 /* Root entry table */
	42	#define DMAR_CCMD_REG 0x28 /* Context command reg */
	43	#define DMAR_FSTS_REG 0x34 /* Fault Status register */
	44	#define DMAR_FECTL_REG 0x38 /* Fault control register */
	45	#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
	46	#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
	47	#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
	48	#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
	49	#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
	50	#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
	51	#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
	52	#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
	53	#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
fe962e90 SS	54	#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
	55	#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
	56	#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
	57	#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
2ae21010	58	#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
ba395927 KA	59
	60	#define OFFSET_STRIDE (9)
	61	/*
	62	#define dmar_readl(dmar, reg) readl(dmar + reg)
	63	#define dmar_readq(dmar, reg) ({ \
	64	u32 lo, hi; \
	65	lo = readl(dmar + reg); \
	66	hi = readl(dmar + reg + 4); \
	67	(((u64) hi) << 32) + lo; })
	68	*/
4fe05bbc	69	static inline u64 dmar_readq(void __iomem *addr)
ba395927 KA	70	{
	71	u32 lo, hi;
	72	lo = readl(addr);
	73	hi = readl(addr + 4);
	74	return (((u64) hi) << 32) + lo;
	75	}
	76
	77	static inline void dmar_writeq(void __iomem *addr, u64 val)
	78	{
	79	writel((u32)val, addr);
	80	writel((u32)(val >> 32), addr + 4);
	81	}
	82
	83	#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
	84	#define DMAR_VER_MINOR(v) ((v) & 0x0f)
	85
	86	/*
	87	* Decoding Capability Register
	88	*/
	89	#define cap_read_drain(c) (((c) >> 55) & 1)
	90	#define cap_write_drain(c) (((c) >> 54) & 1)
	91	#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
	92	#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
	93	#define cap_pgsel_inv(c) (((c) >> 39) & 1)
	94
	95	#define cap_super_page_val(c) (((c) >> 34) & 0xf)
	96	#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
	97	* OFFSET_STRIDE) + 21)
	98
	99	#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
	100	#define cap_max_fault_reg_offset(c) \
	101	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
	102
	103	#define cap_zlr(c) (((c) >> 22) & 1)
	104	#define cap_isoch(c) (((c) >> 23) & 1)
	105	#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
	106	#define cap_sagaw(c) (((c) >> 8) & 0x1f)
	107	#define cap_caching_mode(c) (((c) >> 7) & 1)
	108	#define cap_phmr(c) (((c) >> 6) & 1)
	109	#define cap_plmr(c) (((c) >> 5) & 1)
	110	#define cap_rwbf(c) (((c) >> 4) & 1)
	111	#define cap_afl(c) (((c) >> 3) & 1)
	112	#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
	113	/*
	114	* Extended Capability Register
	115	*/
	116
	117	#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
	118	#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
	119	#define ecap_max_iotlb_offset(e) \
	120	(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
	121	#define ecap_coherent(e) ((e) & 0x1)
fe962e90	122	#define ecap_qis(e) ((e) & 0x2)
ad3ad3f6 SS	123	#define ecap_eim_support(e) ((e >> 4) & 0x1)
ad3ad3f6 SS	124	#define ecap_ir_support(e) ((e >> 3) & 0x1)
b6fcb33a	125	#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
58c610bd	126	#define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
ba395927 KA	127
ba395927 KA	128	/* IOTLB_REG */
3481f210	129	#define DMA_TLB_FLUSH_GRANU_OFFSET 60
ba395927 KA	130	#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
	131	#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
	132	#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
	133	#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
	134	#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
	135	#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
	136	#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
	137	#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
	138	#define DMA_TLB_IVT (((u64)1) << 63)
	139	#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
	140	#define DMA_TLB_MAX_SIZE (0x3f)
	141
fe962e90	142	/* INVALID_DESC */
3481f210	143	#define DMA_CCMD_INVL_GRANU_OFFSET 61
fe962e90 SS	144	#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
	145	#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
	146	#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
	147	#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
	148	#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
	149	#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
	150	#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
	151	#define DMA_ID_TLB_ADDR(addr) (addr)
	152	#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
	153
f8bab735	154	/* PMEN_REG */
	155	#define DMA_PMEN_EPM (((u32)1)<<31)
	156	#define DMA_PMEN_PRS (((u32)1)<<0)
	157
ba395927 KA	158	/* GCMD_REG */
	159	#define DMA_GCMD_TE (((u32)1) << 31)
	160	#define DMA_GCMD_SRTP (((u32)1) << 30)
	161	#define DMA_GCMD_SFL (((u32)1) << 29)
	162	#define DMA_GCMD_EAFL (((u32)1) << 28)
	163	#define DMA_GCMD_WBF (((u32)1) << 27)
2ae21010 SS	164	#define DMA_GCMD_QIE (((u32)1) << 26)
	165	#define DMA_GCMD_SIRTP (((u32)1) << 24)
	166	#define DMA_GCMD_IRE (((u32) 1) << 25)
161fde08	167	#define DMA_GCMD_CFI (((u32) 1) << 23)
ba395927 KA	168
	169	/* GSTS_REG */
	170	#define DMA_GSTS_TES (((u32)1) << 31)
	171	#define DMA_GSTS_RTPS (((u32)1) << 30)
	172	#define DMA_GSTS_FLS (((u32)1) << 29)
	173	#define DMA_GSTS_AFLS (((u32)1) << 28)
	174	#define DMA_GSTS_WBFS (((u32)1) << 27)
2ae21010 SS	175	#define DMA_GSTS_QIES (((u32)1) << 26)
	176	#define DMA_GSTS_IRTPS (((u32)1) << 24)
	177	#define DMA_GSTS_IRES (((u32)1) << 25)
161fde08	178	#define DMA_GSTS_CFIS (((u32)1) << 23)
ba395927 KA	179
	180	/* CCMD_REG */
	181	#define DMA_CCMD_ICC (((u64)1) << 63)
	182	#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
	183	#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
	184	#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
	185	#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
	186	#define DMA_CCMD_MASK_NOBIT 0
	187	#define DMA_CCMD_MASK_1BIT 1
	188	#define DMA_CCMD_MASK_2BIT 2
	189	#define DMA_CCMD_MASK_3BIT 3
	190	#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
	191	#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
	192
	193	/* FECTL_REG */
	194	#define DMA_FECTL_IM (((u32)1) << 31)
	195
	196	/* FSTS_REG */
	197	#define DMA_FSTS_PPF ((u32)2)
	198	#define DMA_FSTS_PFO ((u32)1)
704126ad	199	#define DMA_FSTS_IQE (1 << 4)
ba395927 KA	200	#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
	201
	202	/* FRCD_REG, 32 bits access */
	203	#define DMA_FRCD_F (((u32)1) << 31)
	204	#define dma_frcd_type(d) ((d >> 30) & 1)
	205	#define dma_frcd_fault_reason(c) (c & 0xff)
	206	#define dma_frcd_source_id(c) (c & 0xffff)
5b6985ce FY	207	/* low 64 bit */
	208	#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
	209
	210	#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
	211	do { \
	212	cycles_t start_time = get_cycles(); \
	213	while (1) { \
	214	sts = op(iommu->reg + offset); \
	215	if (cond) \
	216	break; \
cf1337f0	217	if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
5b6985ce FY	218	panic("DMAR hardware is malfunctioning\n"); \
	219	cpu_relax(); \
	220	} \
	221	} while (0)
cf1337f0	222
fe962e90 SS	223	#define QI_LENGTH 256 /* queue length */
	224
	225	enum {
	226	QI_FREE,
	227	QI_IN_USE,
	228	QI_DONE
	229	};
	230
	231	#define QI_CC_TYPE 0x1
	232	#define QI_IOTLB_TYPE 0x2
	233	#define QI_DIOTLB_TYPE 0x3
	234	#define QI_IEC_TYPE 0x4
	235	#define QI_IWD_TYPE 0x5
	236
	237	#define QI_IEC_SELECTIVE (((u64)1) << 4)
	238	#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
	239	#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
	240
	241	#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
	242	#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
	243
3481f210 YS	244	#define QI_IOTLB_DID(did) (((u64)did) << 16)
	245	#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
	246	#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
	247	#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
5b6985ce	248	#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
3481f210 YS	249	#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
	250	#define QI_IOTLB_AM(am) (((u8)am))
	251
	252	#define QI_CC_FM(fm) (((u64)fm) << 48)
	253	#define QI_CC_SID(sid) (((u64)sid) << 32)
	254	#define QI_CC_DID(did) (((u64)did) << 16)
	255	#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
	256
fe962e90 SS	257	struct qi_desc {
	258	u64 low, high;
	259	};
	260
	261	struct q_inval {
	262	spinlock_t q_lock;
	263	struct qi_desc desc; / invalidation queue */
	264	int desc_status; / desc status */
	265	int free_head; /* first free entry */
	266	int free_tail; /* last free entry */
	267	int free_cnt;
	268	};
	269
2ae21010 SS	270	#ifdef CONFIG_INTR_REMAP
	271	/* 1MB - maximum possible interrupt remapping table size */
	272	#define INTR_REMAP_PAGE_ORDER 8
	273	#define INTR_REMAP_TABLE_REG_SIZE 0xf
	274
b6fcb33a SS	275	#define INTR_REMAP_TABLE_ENTRIES 65536
b6fcb33a SS	276
2ae21010 SS	277	struct ir_table {
	278	struct irte *base;
	279	};
	280	#endif
	281
a77b67d4 YS	282	struct iommu_flush {
	283	int (flush_context)(struct intel_iommu iommu, u16 did, u16 sid, u8 fm,
	284	u64 type, int non_present_entry_flush);
	285	int (flush_iotlb)(struct intel_iommu iommu, u16 did, u64 addr,
	286	unsigned int size_order, u64 type, int non_present_entry_flush);
	287	};
	288
f59c7b69 FY	289	enum {
	290	SR_DMAR_FECTL_REG,
	291	SR_DMAR_FEDATA_REG,
	292	SR_DMAR_FEADDR_REG,
	293	SR_DMAR_FEUADDR_REG,
	294	MAX_SR_DMAR_REGS
	295	};
	296
ba395927 KA	297	struct intel_iommu {
	298	void __iomem reg; / Pointer to hardware regs, virtual addr */
	299	u64 cap;
	300	u64 ecap;
ba395927	301	u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
ba395927	302	spinlock_t register_lock; /* protect register handling */
c42d9f32	303	int seq_id; /* sequence id of the iommu */
1b573683	304	int agaw; /* agaw of this iommu */
9d783ba0 SS	305	unsigned int irq;
9d783ba0 SS	306	unsigned char name[13]; /* Device Name */
e61d98d8 SS	307
	308	#ifdef CONFIG_DMAR
	309	unsigned long domain_ids; / bitmap of domains */
	310	struct dmar_domain *domains; / ptr to domains */
	311	spinlock_t lock; /* protect context, domain ids */
ba395927 KA	312	struct root_entry root_entry; / virtual address */
ba395927 KA	313
a77b67d4	314	struct iommu_flush flush;
e61d98d8	315	#endif
fe962e90	316	struct q_inval qi; / Queued invalidation info */
f59c7b69 FY	317	u32 iommu_state; / Store iommu states between suspend and resume.*/
f59c7b69 FY	318
2ae21010 SS	319	#ifdef CONFIG_INTR_REMAP
	320	struct ir_table ir_table; / Interrupt remapping info */
	321	#endif
ba395927 KA	322	};
ba395927 KA	323
fe962e90 SS	324	static inline void __iommu_flush_cache(
	325	struct intel_iommu iommu, void addr, int size)
	326	{
	327	if (!ecap_coherent(iommu->ecap))
	328	clflush_cache_range(addr, size);
	329	}
	330
e61d98d8 SS	331	extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
e61d98d8 SS	332
1886e8a9	333	extern int alloc_iommu(struct dmar_drhd_unit *drhd);
e61d98d8	334	extern void free_iommu(struct intel_iommu *iommu);
2ae21010	335	extern int dmar_enable_qi(struct intel_iommu *iommu);
eba67e5d	336	extern void dmar_disable_qi(struct intel_iommu *iommu);
f59c7b69	337	extern int dmar_reenable_qi(struct intel_iommu *iommu);
2ae21010	338	extern void qi_global_iec(struct intel_iommu *iommu);
e820482c	339
3481f210 YS	340	extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
	341	u8 fm, u64 type, int non_present_entry_flush);
	342	extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
	343	unsigned int size_order, u64 type,
	344	int non_present_entry_flush);
	345
704126ad	346	extern int qi_submit_sync(struct qi_desc desc, struct intel_iommu iommu);
38717946	347
ba395927	348	#endif