genirq: Support per-IRQ thread disabling.
[deliverable/linux.git] / include / linux / irq.h
CommitLineData
06fcb0c6
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1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
1da177e4
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3
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
23f9b317 12#include <linux/smp.h>
1da177e4 13
06fcb0c6 14#ifndef CONFIG_S390
1da177e4
LT
15
16#include <linux/linkage.h>
17#include <linux/cache.h>
18#include <linux/spinlock.h>
19#include <linux/cpumask.h>
503e5763 20#include <linux/gfp.h>
908dcecd 21#include <linux/irqreturn.h>
dd3a1db9 22#include <linux/irqnr.h>
77904fd6 23#include <linux/errno.h>
503e5763 24#include <linux/topology.h>
3aa551c9 25#include <linux/wait.h>
1da177e4
LT
26
27#include <asm/irq.h>
28#include <asm/ptrace.h>
7d12e780 29#include <asm/irq_regs.h>
1da177e4 30
ab7798ff 31struct seq_file;
57a58a94 32struct irq_desc;
78129576 33struct irq_data;
ec701584 34typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780 35 struct irq_desc *desc);
78129576 36typedef void (*irq_preflow_handler_t)(struct irq_data *data);
57a58a94 37
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38/*
39 * IRQ line status.
6e213616 40 *
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41 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
42 *
43 * IRQ_TYPE_NONE - default, unspecified type
44 * IRQ_TYPE_EDGE_RISING - rising edge triggered
45 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
46 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
47 * IRQ_TYPE_LEVEL_HIGH - high level triggered
48 * IRQ_TYPE_LEVEL_LOW - low level triggered
49 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
50 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
51 * IRQ_TYPE_PROBE - Special flag for probing in progress
52 *
53 * Bits which can be modified via irq_set/clear/modify_status_flags()
54 * IRQ_LEVEL - Interrupt is level type. Will be also
55 * updated in the code when the above trigger
0911f124 56 * bits are modified via irq_set_irq_type()
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57 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
58 * it from affinity setting
59 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
60 * IRQ_NOREQUEST - Interrupt cannot be requested via
61 * request_irq()
7f1b1244 62 * IRQ_NOTHREAD - Interrupt cannot be threaded
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63 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
64 * request/setup_irq()
65 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
66 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
67 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
1da177e4 68 */
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69enum {
70 IRQ_TYPE_NONE = 0x00000000,
71 IRQ_TYPE_EDGE_RISING = 0x00000001,
72 IRQ_TYPE_EDGE_FALLING = 0x00000002,
73 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
74 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
75 IRQ_TYPE_LEVEL_LOW = 0x00000008,
76 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
77 IRQ_TYPE_SENSE_MASK = 0x0000000f,
78
79 IRQ_TYPE_PROBE = 0x00000010,
80
81 IRQ_LEVEL = (1 << 8),
82 IRQ_PER_CPU = (1 << 9),
83 IRQ_NOPROBE = (1 << 10),
84 IRQ_NOREQUEST = (1 << 11),
85 IRQ_NOAUTOEN = (1 << 12),
86 IRQ_NO_BALANCING = (1 << 13),
87 IRQ_MOVE_PCNTXT = (1 << 14),
88 IRQ_NESTED_THREAD = (1 << 15),
7f1b1244 89 IRQ_NOTHREAD = (1 << 16),
5d4d8fc9 90};
950f4427 91
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92#define IRQF_MODIFY_MASK \
93 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
872434d6 94 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
6f91a52d 95 IRQ_PER_CPU | IRQ_NESTED_THREAD)
44247184 96
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97#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
98
99static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status)
100{
101 return status & IRQ_PER_CPU;
102}
1da177e4 103
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104/*
105 * Return value for chip->irq_set_affinity()
106 *
107 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
108 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
109 */
110enum {
111 IRQ_SET_MASK_OK = 0,
112 IRQ_SET_MASK_OK_NOCOPY,
113};
114
5b912c10 115struct msi_desc;
6a6de9ef 116
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117/**
118 * struct irq_data - per irq and irq chip data passed down to chip functions
119 * @irq: interrupt number
120 * @node: node index useful for balancing
30398bf6 121 * @state_use_accessors: status information for irq chip functions.
91c49917 122 * Use accessor functions to deal with it
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123 * @chip: low level interrupt hardware access
124 * @handler_data: per-IRQ data for the irq_chip methods
125 * @chip_data: platform-specific per-chip private data for the chip
126 * methods, to allow shared chip implementations
127 * @msi_desc: MSI descriptor
128 * @affinity: IRQ affinity on SMP
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129 *
130 * The fields here need to overlay the ones in irq_desc until we
131 * cleaned up the direct references and switched everything over to
132 * irq_data.
133 */
134struct irq_data {
135 unsigned int irq;
136 unsigned int node;
91c49917 137 unsigned int state_use_accessors;
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138 struct irq_chip *chip;
139 void *handler_data;
140 void *chip_data;
141 struct msi_desc *msi_desc;
142#ifdef CONFIG_SMP
143 cpumask_var_t affinity;
144#endif
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145};
146
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147/*
148 * Bit masks for irq_data.state
149 *
876dbd4c 150 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
f230b6d5 151 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
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152 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
153 * IRQD_PER_CPU - Interrupt is per cpu
2bdd1055 154 * IRQD_AFFINITY_SET - Interrupt affinity was set
876dbd4c 155 * IRQD_LEVEL - Interrupt is level triggered
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156 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
157 * from suspend
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158 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
159 * context
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160 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
161 * IRQD_IRQ_MASKED - Masked state of the interrupt
162 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
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163 */
164enum {
876dbd4c 165 IRQD_TRIGGER_MASK = 0xf,
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166 IRQD_SETAFFINITY_PENDING = (1 << 8),
167 IRQD_NO_BALANCING = (1 << 10),
168 IRQD_PER_CPU = (1 << 11),
2bdd1055 169 IRQD_AFFINITY_SET = (1 << 12),
876dbd4c 170 IRQD_LEVEL = (1 << 13),
7f94226f 171 IRQD_WAKEUP_STATE = (1 << 14),
e1ef8241 172 IRQD_MOVE_PCNTXT = (1 << 15),
801a0e9a 173 IRQD_IRQ_DISABLED = (1 << 16),
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174 IRQD_IRQ_MASKED = (1 << 17),
175 IRQD_IRQ_INPROGRESS = (1 << 18),
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176};
177
178static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
179{
180 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
181}
182
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183static inline bool irqd_is_per_cpu(struct irq_data *d)
184{
185 return d->state_use_accessors & IRQD_PER_CPU;
186}
187
188static inline bool irqd_can_balance(struct irq_data *d)
189{
190 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
191}
192
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193static inline bool irqd_affinity_was_set(struct irq_data *d)
194{
195 return d->state_use_accessors & IRQD_AFFINITY_SET;
196}
197
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198static inline void irqd_mark_affinity_was_set(struct irq_data *d)
199{
200 d->state_use_accessors |= IRQD_AFFINITY_SET;
201}
202
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203static inline u32 irqd_get_trigger_type(struct irq_data *d)
204{
205 return d->state_use_accessors & IRQD_TRIGGER_MASK;
206}
207
208/*
209 * Must only be called inside irq_chip.irq_set_type() functions.
210 */
211static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
212{
213 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
214 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
215}
216
217static inline bool irqd_is_level_type(struct irq_data *d)
218{
219 return d->state_use_accessors & IRQD_LEVEL;
220}
221
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222static inline bool irqd_is_wakeup_set(struct irq_data *d)
223{
224 return d->state_use_accessors & IRQD_WAKEUP_STATE;
225}
226
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227static inline bool irqd_can_move_in_process_context(struct irq_data *d)
228{
229 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
230}
231
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232static inline bool irqd_irq_disabled(struct irq_data *d)
233{
234 return d->state_use_accessors & IRQD_IRQ_DISABLED;
235}
236
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237static inline bool irqd_irq_masked(struct irq_data *d)
238{
239 return d->state_use_accessors & IRQD_IRQ_MASKED;
240}
241
242static inline bool irqd_irq_inprogress(struct irq_data *d)
243{
244 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
245}
246
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TG
247/*
248 * Functions for chained handlers which can be enabled/disabled by the
249 * standard disable_irq/enable_irq calls. Must be called with
250 * irq_desc->lock held.
251 */
252static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
253{
254 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
255}
256
257static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
258{
259 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
260}
261
8fee5c36 262/**
6a6de9ef 263 * struct irq_chip - hardware interrupt chip descriptor
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IM
264 *
265 * @name: name for /proc/interrupts
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266 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
267 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
268 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
269 * @irq_disable: disable the interrupt
270 * @irq_ack: start of a new interrupt
271 * @irq_mask: mask an interrupt source
272 * @irq_mask_ack: ack and mask an interrupt source
273 * @irq_unmask: unmask an interrupt source
274 * @irq_eoi: end of interrupt
275 * @irq_set_affinity: set the CPU affinity on SMP machines
276 * @irq_retrigger: resend an IRQ to the CPU
277 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
278 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
279 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
280 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
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281 * @irq_cpu_online: configure an interrupt source for a secondary CPU
282 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
ab7798ff 283 * @irq_print_chip: optional to print special chip info in show_interrupts
2bff17ad 284 * @flags: chip specific flags
70aedd24 285 *
8fee5c36 286 * @release: release function solely used by UML
1da177e4 287 */
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288struct irq_chip {
289 const char *name;
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290 unsigned int (*irq_startup)(struct irq_data *data);
291 void (*irq_shutdown)(struct irq_data *data);
292 void (*irq_enable)(struct irq_data *data);
293 void (*irq_disable)(struct irq_data *data);
294
295 void (*irq_ack)(struct irq_data *data);
296 void (*irq_mask)(struct irq_data *data);
297 void (*irq_mask_ack)(struct irq_data *data);
298 void (*irq_unmask)(struct irq_data *data);
299 void (*irq_eoi)(struct irq_data *data);
300
301 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
302 int (*irq_retrigger)(struct irq_data *data);
303 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
304 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
305
306 void (*irq_bus_lock)(struct irq_data *data);
307 void (*irq_bus_sync_unlock)(struct irq_data *data);
308
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DD
309 void (*irq_cpu_online)(struct irq_data *data);
310 void (*irq_cpu_offline)(struct irq_data *data);
311
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312 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
313
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314 unsigned long flags;
315
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316 /* Currently used only by UML, might disappear one day.*/
317#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7 318 void (*release)(unsigned int irq, void *dev_id);
b77d6adc 319#endif
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LT
320};
321
d4d5e089
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322/*
323 * irq_chip specific flags
324 *
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325 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
326 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
d209a699 327 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
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328 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
329 * when irq enabled
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330 */
331enum {
332 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
77694b40 333 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
d209a699 334 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
b3d42232 335 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
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TG
336};
337
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338/* This include will go away once we isolated irq_desc usage to core code */
339#include <linux/irqdesc.h>
0b8f1efa 340
34ffdb72
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341/*
342 * Pick up the arch-dependent methods:
343 */
344#include <asm/hw_irq.h>
1da177e4 345
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346#ifndef NR_IRQS_LEGACY
347# define NR_IRQS_LEGACY 0
348#endif
349
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TG
350#ifndef ARCH_IRQ_INIT_FLAGS
351# define ARCH_IRQ_INIT_FLAGS 0
352#endif
353
c1594b77 354#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
1318a481 355
e144710b 356struct irqaction;
06fcb0c6 357extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06 358extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4 359
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DD
360extern void irq_cpu_online(void);
361extern void irq_cpu_offline(void);
c2d0c555 362extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask);
0fdb4b25 363
1da177e4 364#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6 365
3a3856d0 366#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
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367void irq_move_irq(struct irq_data *data);
368void irq_move_masked_irq(struct irq_data *data);
e144710b 369#else
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370static inline void irq_move_irq(struct irq_data *data) { }
371static inline void irq_move_masked_irq(struct irq_data *data) { }
e144710b 372#endif
54d5d424 373
1da177e4 374extern int no_irq_affinity;
1da177e4 375
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376/*
377 * Built-in IRQ handlers for various IRQ types,
bebd04cc 378 * callable via desc->handle_irq()
6a6de9ef 379 */
ec701584
HH
380extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
381extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
382extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
0521c8fb 383extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
ec701584
HH
384extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
385extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
386extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
31b47cf7 387extern void handle_nested_irq(unsigned int irq);
6a6de9ef 388
6a6de9ef 389/* Handling of unhandled and spurious interrupts: */
34ffdb72 390extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9 391 irqreturn_t action_ret);
1da177e4 392
a4633adc 393
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TG
394/* Enable/disable irq debugging output: */
395extern int noirqdebug_setup(char *str);
396
397/* Checks whether the interrupt can be requested by request_irq(): */
398extern int can_request_irq(unsigned int irq, unsigned long irqflags);
399
f8b5473f 400/* Dummy irq-chip implementations: */
6a6de9ef 401extern struct irq_chip no_irq_chip;
f8b5473f 402extern struct irq_chip dummy_irq_chip;
6a6de9ef 403
145fc655 404extern void
3836ca08 405irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745
IM
406 irq_flow_handler_t handle, const char *name);
407
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TG
408static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
409 irq_flow_handler_t handle)
410{
411 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
412}
413
6a6de9ef 414extern void
3836ca08 415__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 416 const char *name);
1da177e4 417
6a6de9ef 418static inline void
3836ca08 419irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef 420{
3836ca08 421 __irq_set_handler(irq, handle, 0, NULL);
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TG
422}
423
424/*
425 * Set a highlevel chained flow handler for a given IRQ.
426 * (a chained handler is automatically enabled and set to
7f1b1244 427 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
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TG
428 */
429static inline void
3836ca08 430irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef 431{
3836ca08 432 __irq_set_handler(irq, handle, 1, NULL);
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433}
434
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435void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
436
437static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
438{
439 irq_modify_status(irq, 0, set);
440}
441
442static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
443{
444 irq_modify_status(irq, clr, 0);
445}
446
a0cd9ca2 447static inline void irq_set_noprobe(unsigned int irq)
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448{
449 irq_modify_status(irq, 0, IRQ_NOPROBE);
450}
451
a0cd9ca2 452static inline void irq_set_probe(unsigned int irq)
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453{
454 irq_modify_status(irq, IRQ_NOPROBE, 0);
455}
46f4f8f6 456
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457static inline void irq_set_nothread(unsigned int irq)
458{
459 irq_modify_status(irq, 0, IRQ_NOTHREAD);
460}
461
462static inline void irq_set_thread(unsigned int irq)
463{
464 irq_modify_status(irq, IRQ_NOTHREAD, 0);
465}
466
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467static inline void irq_set_nested_thread(unsigned int irq, bool nest)
468{
469 if (nest)
470 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
471 else
472 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
473}
474
3a16d713 475/* Handle dynamic irq creation and destruction */
d047f53a 476extern unsigned int create_irq_nr(unsigned int irq_want, int node);
3a16d713
EB
477extern int create_irq(void);
478extern void destroy_irq(unsigned int irq);
479
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480/*
481 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
482 * irq_free_desc instead.
483 */
3a16d713 484extern void dynamic_irq_cleanup(unsigned int irq);
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485static inline void dynamic_irq_init(unsigned int irq)
486{
487 dynamic_irq_cleanup(irq);
488}
dd87eb3a 489
3a16d713 490/* Set/get chip/data for an IRQ: */
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491extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
492extern int irq_set_handler_data(unsigned int irq, void *data);
493extern int irq_set_chip_data(unsigned int irq, void *data);
494extern int irq_set_irq_type(unsigned int irq, unsigned int type);
495extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
f303a6dd 496extern struct irq_data *irq_get_irq_data(unsigned int irq);
dd87eb3a 497
a0cd9ca2 498static inline struct irq_chip *irq_get_chip(unsigned int irq)
f303a6dd
TG
499{
500 struct irq_data *d = irq_get_irq_data(irq);
501 return d ? d->chip : NULL;
502}
503
504static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
505{
506 return d->chip;
507}
508
a0cd9ca2 509static inline void *irq_get_chip_data(unsigned int irq)
f303a6dd
TG
510{
511 struct irq_data *d = irq_get_irq_data(irq);
512 return d ? d->chip_data : NULL;
513}
514
515static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
516{
517 return d->chip_data;
518}
519
a0cd9ca2 520static inline void *irq_get_handler_data(unsigned int irq)
f303a6dd
TG
521{
522 struct irq_data *d = irq_get_irq_data(irq);
523 return d ? d->handler_data : NULL;
524}
525
a0cd9ca2 526static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
f303a6dd
TG
527{
528 return d->handler_data;
529}
530
a0cd9ca2 531static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
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532{
533 struct irq_data *d = irq_get_irq_data(irq);
534 return d ? d->msi_desc : NULL;
535}
536
537static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
538{
539 return d->msi_desc;
540}
541
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542int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node);
543void irq_free_descs(unsigned int irq, unsigned int cnt);
06f6c339 544int irq_reserve_irqs(unsigned int from, unsigned int cnt);
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545
546static inline int irq_alloc_desc(int node)
547{
548 return irq_alloc_descs(-1, 0, 1, node);
549}
550
551static inline int irq_alloc_desc_at(unsigned int at, int node)
552{
553 return irq_alloc_descs(at, at, 1, node);
554}
555
556static inline int irq_alloc_desc_from(unsigned int from, int node)
557{
558 return irq_alloc_descs(-1, from, 1, node);
559}
560
561static inline void irq_free_desc(unsigned int irq)
562{
563 irq_free_descs(irq, 1);
564}
565
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566static inline int irq_reserve_irq(unsigned int irq)
567{
568 return irq_reserve_irqs(irq, 1);
569}
570
6a6de9ef 571#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4 572
06fcb0c6 573#endif /* !CONFIG_S390 */
1da177e4 574
06fcb0c6 575#endif /* _LINUX_IRQ_H */
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