Commit | Line | Data |
---|---|---|
06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
3aa551c9 | 25 | #include <linux/wait.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
57a58a94 | 31 | struct irq_desc; |
ec701584 | 32 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 33 | struct irq_desc *desc); |
57a58a94 DH |
34 | |
35 | ||
1da177e4 LT |
36 | /* |
37 | * IRQ line status. | |
6e213616 | 38 | * |
5d4d8fc9 TG |
39 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
40 | * | |
41 | * IRQ_TYPE_NONE - default, unspecified type | |
42 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
43 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
44 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
45 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
46 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
47 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
48 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
49 | * IRQ_TYPE_PROBE - Special flag for probing in progress | |
50 | * | |
51 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
52 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
53 | * updated in the code when the above trigger | |
54 | * bits are modified via set_irq_type() | |
55 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect | |
56 | * it from affinity setting | |
57 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
58 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
59 | * request_irq() | |
60 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in | |
61 | * request/setup_irq() | |
62 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
63 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
64 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
65 | * | |
66 | * Deprecated bits. They are kept updated as long as | |
67 | * CONFIG_GENERIC_HARDIRQS_NO_COMPAT is not set. Will go away soon. These bits | |
68 | * are internal state of the core code and if you really need to acces | |
69 | * them then talk to the genirq maintainer instead of hacking | |
70 | * something weird. | |
6e213616 | 71 | * |
1da177e4 | 72 | */ |
5d4d8fc9 TG |
73 | enum { |
74 | IRQ_TYPE_NONE = 0x00000000, | |
75 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
76 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
77 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
78 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
79 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
80 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
81 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
82 | ||
83 | IRQ_TYPE_PROBE = 0x00000010, | |
84 | ||
85 | IRQ_LEVEL = (1 << 8), | |
86 | IRQ_PER_CPU = (1 << 9), | |
87 | IRQ_NOPROBE = (1 << 10), | |
88 | IRQ_NOREQUEST = (1 << 11), | |
89 | IRQ_NOAUTOEN = (1 << 12), | |
90 | IRQ_NO_BALANCING = (1 << 13), | |
91 | IRQ_MOVE_PCNTXT = (1 << 14), | |
92 | IRQ_NESTED_THREAD = (1 << 15), | |
009b4c3b TG |
93 | |
94 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT | |
5d4d8fc9 TG |
95 | IRQ_INPROGRESS = (1 << 16), |
96 | IRQ_REPLAY = (1 << 17), | |
97 | IRQ_WAITING = (1 << 18), | |
98 | IRQ_DISABLED = (1 << 19), | |
99 | IRQ_PENDING = (1 << 20), | |
100 | IRQ_MASKED = (1 << 21), | |
101 | IRQ_MOVE_PENDING = (1 << 22), | |
102 | IRQ_AFFINITY_SET = (1 << 23), | |
103 | IRQ_WAKEUP = (1 << 24), | |
009b4c3b | 104 | #endif |
5d4d8fc9 | 105 | }; |
950f4427 | 106 | |
44247184 TG |
107 | #define IRQF_MODIFY_MASK \ |
108 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 109 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
6f91a52d | 110 | IRQ_PER_CPU | IRQ_NESTED_THREAD) |
44247184 | 111 | |
8f53f924 TG |
112 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
113 | ||
114 | static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status) | |
115 | { | |
116 | return status & IRQ_PER_CPU; | |
117 | } | |
1da177e4 | 118 | |
3b8249e7 TG |
119 | /* |
120 | * Return value for chip->irq_set_affinity() | |
121 | * | |
122 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
123 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
124 | */ | |
125 | enum { | |
126 | IRQ_SET_MASK_OK = 0, | |
127 | IRQ_SET_MASK_OK_NOCOPY, | |
128 | }; | |
129 | ||
5b912c10 | 130 | struct msi_desc; |
6a6de9ef | 131 | |
ff7dcd44 TG |
132 | /** |
133 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
134 | * @irq: interrupt number | |
135 | * @node: node index useful for balancing | |
91c49917 TG |
136 | * @state_use_accessor: status information for irq chip functions. |
137 | * Use accessor functions to deal with it | |
ff7dcd44 TG |
138 | * @chip: low level interrupt hardware access |
139 | * @handler_data: per-IRQ data for the irq_chip methods | |
140 | * @chip_data: platform-specific per-chip private data for the chip | |
141 | * methods, to allow shared chip implementations | |
142 | * @msi_desc: MSI descriptor | |
143 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
144 | * |
145 | * The fields here need to overlay the ones in irq_desc until we | |
146 | * cleaned up the direct references and switched everything over to | |
147 | * irq_data. | |
148 | */ | |
149 | struct irq_data { | |
150 | unsigned int irq; | |
151 | unsigned int node; | |
91c49917 | 152 | unsigned int state_use_accessors; |
ff7dcd44 TG |
153 | struct irq_chip *chip; |
154 | void *handler_data; | |
155 | void *chip_data; | |
156 | struct msi_desc *msi_desc; | |
157 | #ifdef CONFIG_SMP | |
158 | cpumask_var_t affinity; | |
159 | #endif | |
ff7dcd44 TG |
160 | }; |
161 | ||
f230b6d5 TG |
162 | /* |
163 | * Bit masks for irq_data.state | |
164 | * | |
876dbd4c | 165 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 166 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
167 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
168 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 169 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 170 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
171 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
172 | * from suspend | |
f230b6d5 TG |
173 | */ |
174 | enum { | |
876dbd4c | 175 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
176 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
177 | IRQD_NO_BALANCING = (1 << 10), | |
178 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 179 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 180 | IRQD_LEVEL = (1 << 13), |
7f94226f | 181 | IRQD_WAKEUP_STATE = (1 << 14), |
f230b6d5 TG |
182 | }; |
183 | ||
184 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
185 | { | |
186 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
187 | } | |
188 | ||
a005677b TG |
189 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
190 | { | |
191 | return d->state_use_accessors & IRQD_PER_CPU; | |
192 | } | |
193 | ||
194 | static inline bool irqd_can_balance(struct irq_data *d) | |
195 | { | |
196 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
197 | } | |
198 | ||
2bdd1055 TG |
199 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
200 | { | |
201 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
202 | } | |
203 | ||
876dbd4c TG |
204 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
205 | { | |
206 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Must only be called inside irq_chip.irq_set_type() functions. | |
211 | */ | |
212 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
213 | { | |
214 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
215 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
216 | } | |
217 | ||
218 | static inline bool irqd_is_level_type(struct irq_data *d) | |
219 | { | |
220 | return d->state_use_accessors & IRQD_LEVEL; | |
221 | } | |
222 | ||
7f94226f TG |
223 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
224 | { | |
225 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
226 | } | |
227 | ||
8fee5c36 | 228 | /** |
6a6de9ef | 229 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
230 | * |
231 | * @name: name for /proc/interrupts | |
f8822657 TG |
232 | * @startup: deprecated, replaced by irq_startup |
233 | * @shutdown: deprecated, replaced by irq_shutdown | |
234 | * @enable: deprecated, replaced by irq_enable | |
235 | * @disable: deprecated, replaced by irq_disable | |
236 | * @ack: deprecated, replaced by irq_ack | |
237 | * @mask: deprecated, replaced by irq_mask | |
238 | * @mask_ack: deprecated, replaced by irq_mask_ack | |
239 | * @unmask: deprecated, replaced by irq_unmask | |
240 | * @eoi: deprecated, replaced by irq_eoi | |
241 | * @end: deprecated, will go away with __do_IRQ() | |
242 | * @set_affinity: deprecated, replaced by irq_set_affinity | |
243 | * @retrigger: deprecated, replaced by irq_retrigger | |
244 | * @set_type: deprecated, replaced by irq_set_type | |
245 | * @set_wake: deprecated, replaced by irq_wake | |
246 | * @bus_lock: deprecated, replaced by irq_bus_lock | |
247 | * @bus_sync_unlock: deprecated, replaced by irq_bus_sync_unlock | |
8fee5c36 | 248 | * |
f8822657 TG |
249 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
250 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
251 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
252 | * @irq_disable: disable the interrupt | |
253 | * @irq_ack: start of a new interrupt | |
254 | * @irq_mask: mask an interrupt source | |
255 | * @irq_mask_ack: ack and mask an interrupt source | |
256 | * @irq_unmask: unmask an interrupt source | |
257 | * @irq_eoi: end of interrupt | |
258 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
259 | * @irq_retrigger: resend an IRQ to the CPU | |
260 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
261 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
262 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
263 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
2bff17ad | 264 | * @flags: chip specific flags |
70aedd24 | 265 | * |
8fee5c36 | 266 | * @release: release function solely used by UML |
1da177e4 | 267 | */ |
6a6de9ef TG |
268 | struct irq_chip { |
269 | const char *name; | |
bd151412 | 270 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
71d218b7 IM |
271 | unsigned int (*startup)(unsigned int irq); |
272 | void (*shutdown)(unsigned int irq); | |
273 | void (*enable)(unsigned int irq); | |
274 | void (*disable)(unsigned int irq); | |
6a6de9ef | 275 | |
71d218b7 | 276 | void (*ack)(unsigned int irq); |
6a6de9ef TG |
277 | void (*mask)(unsigned int irq); |
278 | void (*mask_ack)(unsigned int irq); | |
279 | void (*unmask)(unsigned int irq); | |
47c2a3aa | 280 | void (*eoi)(unsigned int irq); |
6a6de9ef | 281 | |
71d218b7 | 282 | void (*end)(unsigned int irq); |
d5dedd45 | 283 | int (*set_affinity)(unsigned int irq, |
0de26520 | 284 | const struct cpumask *dest); |
c0ad90a3 | 285 | int (*retrigger)(unsigned int irq); |
6a6de9ef TG |
286 | int (*set_type)(unsigned int irq, unsigned int flow_type); |
287 | int (*set_wake)(unsigned int irq, unsigned int on); | |
c0ad90a3 | 288 | |
70aedd24 TG |
289 | void (*bus_lock)(unsigned int irq); |
290 | void (*bus_sync_unlock)(unsigned int irq); | |
bd151412 | 291 | #endif |
f8822657 TG |
292 | unsigned int (*irq_startup)(struct irq_data *data); |
293 | void (*irq_shutdown)(struct irq_data *data); | |
294 | void (*irq_enable)(struct irq_data *data); | |
295 | void (*irq_disable)(struct irq_data *data); | |
296 | ||
297 | void (*irq_ack)(struct irq_data *data); | |
298 | void (*irq_mask)(struct irq_data *data); | |
299 | void (*irq_mask_ack)(struct irq_data *data); | |
300 | void (*irq_unmask)(struct irq_data *data); | |
301 | void (*irq_eoi)(struct irq_data *data); | |
302 | ||
303 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
304 | int (*irq_retrigger)(struct irq_data *data); | |
305 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
306 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
307 | ||
308 | void (*irq_bus_lock)(struct irq_data *data); | |
309 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
310 | ||
2bff17ad TG |
311 | unsigned long flags; |
312 | ||
b77d6adc PBG |
313 | /* Currently used only by UML, might disappear one day.*/ |
314 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 315 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 316 | #endif |
1da177e4 LT |
317 | }; |
318 | ||
d4d5e089 TG |
319 | /* |
320 | * irq_chip specific flags | |
321 | * | |
322 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() | |
323 | */ | |
324 | enum { | |
325 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
326 | }; | |
327 | ||
e144710b TG |
328 | /* This include will go away once we isolated irq_desc usage to core code */ |
329 | #include <linux/irqdesc.h> | |
0b8f1efa | 330 | |
34ffdb72 IM |
331 | /* |
332 | * Pick up the arch-dependent methods: | |
333 | */ | |
334 | #include <asm/hw_irq.h> | |
1da177e4 | 335 | |
b683de2b TG |
336 | #ifndef NR_IRQS_LEGACY |
337 | # define NR_IRQS_LEGACY 0 | |
338 | #endif | |
339 | ||
1318a481 TG |
340 | #ifndef ARCH_IRQ_INIT_FLAGS |
341 | # define ARCH_IRQ_INIT_FLAGS 0 | |
342 | #endif | |
343 | ||
c1594b77 | 344 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 345 | |
e144710b | 346 | struct irqaction; |
06fcb0c6 | 347 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 348 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
1da177e4 LT |
349 | |
350 | #ifdef CONFIG_GENERIC_HARDIRQS | |
06fcb0c6 | 351 | |
3a3856d0 | 352 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
c777ac55 | 353 | void move_native_irq(int irq); |
e7b946e9 | 354 | void move_masked_irq(int irq); |
e144710b TG |
355 | #else |
356 | static inline void move_native_irq(int irq) { } | |
357 | static inline void move_masked_irq(int irq) { } | |
358 | #endif | |
54d5d424 | 359 | |
1da177e4 | 360 | extern int no_irq_affinity; |
1da177e4 | 361 | |
6a6de9ef | 362 | /* Handle irq action chains: */ |
bedd30d9 | 363 | extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action); |
6a6de9ef TG |
364 | |
365 | /* | |
366 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 367 | * callable via desc->handle_irq() |
6a6de9ef | 368 | */ |
ec701584 HH |
369 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
370 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
371 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
372 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); | |
373 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
374 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); | |
31b47cf7 | 375 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 376 | |
6a6de9ef | 377 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 378 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 379 | irqreturn_t action_ret); |
1da177e4 | 380 | |
a4633adc | 381 | |
6a6de9ef TG |
382 | /* Enable/disable irq debugging output: */ |
383 | extern int noirqdebug_setup(char *str); | |
384 | ||
385 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
386 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
387 | ||
f8b5473f | 388 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 389 | extern struct irq_chip no_irq_chip; |
f8b5473f | 390 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 391 | |
145fc655 IM |
392 | extern void |
393 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
394 | irq_flow_handler_t handle); | |
6a6de9ef | 395 | extern void |
a460e745 IM |
396 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
397 | irq_flow_handler_t handle, const char *name); | |
398 | ||
6a6de9ef | 399 | extern void |
a460e745 IM |
400 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
401 | const char *name); | |
1da177e4 | 402 | |
6a6de9ef TG |
403 | /* |
404 | * Set a highlevel flow handler for a given IRQ: | |
405 | */ | |
406 | static inline void | |
57a58a94 | 407 | set_irq_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 408 | { |
a460e745 | 409 | __set_irq_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
410 | } |
411 | ||
412 | /* | |
413 | * Set a highlevel chained flow handler for a given IRQ. | |
414 | * (a chained handler is automatically enabled and set to | |
415 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
416 | */ | |
417 | static inline void | |
a0cd9ca2 | 418 | set_irq_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 419 | { |
a460e745 | 420 | __set_irq_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
421 | } |
422 | ||
44247184 TG |
423 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
424 | ||
425 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
426 | { | |
427 | irq_modify_status(irq, 0, set); | |
428 | } | |
429 | ||
430 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
431 | { | |
432 | irq_modify_status(irq, clr, 0); | |
433 | } | |
434 | ||
a0cd9ca2 | 435 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
436 | { |
437 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
438 | } | |
439 | ||
a0cd9ca2 | 440 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
441 | { |
442 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
443 | } | |
46f4f8f6 | 444 | |
6f91a52d TG |
445 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
446 | { | |
447 | if (nest) | |
448 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
449 | else | |
450 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
451 | } | |
452 | ||
3a16d713 | 453 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 454 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
3a16d713 EB |
455 | extern int create_irq(void); |
456 | extern void destroy_irq(unsigned int irq); | |
457 | ||
b7b29338 TG |
458 | /* |
459 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and | |
460 | * irq_free_desc instead. | |
461 | */ | |
3a16d713 | 462 | extern void dynamic_irq_cleanup(unsigned int irq); |
b7b29338 TG |
463 | static inline void dynamic_irq_init(unsigned int irq) |
464 | { | |
465 | dynamic_irq_cleanup(irq); | |
466 | } | |
dd87eb3a | 467 | |
3a16d713 | 468 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
469 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
470 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
471 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
472 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
473 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
f303a6dd | 474 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 475 | |
a0cd9ca2 | 476 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
477 | { |
478 | struct irq_data *d = irq_get_irq_data(irq); | |
479 | return d ? d->chip : NULL; | |
480 | } | |
481 | ||
482 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
483 | { | |
484 | return d->chip; | |
485 | } | |
486 | ||
a0cd9ca2 | 487 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
488 | { |
489 | struct irq_data *d = irq_get_irq_data(irq); | |
490 | return d ? d->chip_data : NULL; | |
491 | } | |
492 | ||
493 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
494 | { | |
495 | return d->chip_data; | |
496 | } | |
497 | ||
a0cd9ca2 | 498 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
499 | { |
500 | struct irq_data *d = irq_get_irq_data(irq); | |
501 | return d ? d->handler_data : NULL; | |
502 | } | |
503 | ||
a0cd9ca2 | 504 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
505 | { |
506 | return d->handler_data; | |
507 | } | |
508 | ||
a0cd9ca2 | 509 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
510 | { |
511 | struct irq_data *d = irq_get_irq_data(irq); | |
512 | return d ? d->msi_desc : NULL; | |
513 | } | |
514 | ||
515 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
516 | { | |
517 | return d->msi_desc; | |
518 | } | |
519 | ||
a0cd9ca2 TG |
520 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT |
521 | /* Please do not use: Use the replacement functions instead */ | |
522 | static inline int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
523 | { | |
524 | return irq_set_chip(irq, chip); | |
525 | } | |
526 | static inline int set_irq_data(unsigned int irq, void *data) | |
527 | { | |
528 | return irq_set_handler_data(irq, data); | |
529 | } | |
530 | static inline int set_irq_chip_data(unsigned int irq, void *data) | |
531 | { | |
532 | return irq_set_chip_data(irq, data); | |
533 | } | |
534 | static inline int set_irq_type(unsigned int irq, unsigned int type) | |
535 | { | |
536 | return irq_set_irq_type(irq, type); | |
537 | } | |
538 | static inline int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
539 | { | |
540 | return irq_set_msi_desc(irq, entry); | |
541 | } | |
542 | static inline struct irq_chip *get_irq_chip(unsigned int irq) | |
543 | { | |
544 | return irq_get_chip(irq); | |
545 | } | |
546 | static inline void *get_irq_chip_data(unsigned int irq) | |
547 | { | |
548 | return irq_get_chip_data(irq); | |
549 | } | |
550 | static inline void *get_irq_data(unsigned int irq) | |
551 | { | |
552 | return irq_get_handler_data(irq); | |
553 | } | |
554 | static inline void *irq_data_get_irq_data(struct irq_data *d) | |
555 | { | |
556 | return irq_data_get_irq_handler_data(d); | |
557 | } | |
558 | static inline struct msi_desc *get_irq_msi(unsigned int irq) | |
559 | { | |
560 | return irq_get_msi_desc(irq); | |
561 | } | |
562 | static inline void set_irq_noprobe(unsigned int irq) | |
563 | { | |
564 | irq_set_noprobe(irq); | |
565 | } | |
566 | static inline void set_irq_probe(unsigned int irq) | |
567 | { | |
568 | irq_set_probe(irq); | |
569 | } | |
6f91a52d TG |
570 | static inline void set_irq_nested_thread(unsigned int irq, int nest) |
571 | { | |
572 | irq_set_nested_thread(irq, nest); | |
573 | } | |
a0cd9ca2 TG |
574 | #endif |
575 | ||
1f5a5b87 TG |
576 | int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node); |
577 | void irq_free_descs(unsigned int irq, unsigned int cnt); | |
06f6c339 | 578 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); |
1f5a5b87 TG |
579 | |
580 | static inline int irq_alloc_desc(int node) | |
581 | { | |
582 | return irq_alloc_descs(-1, 0, 1, node); | |
583 | } | |
584 | ||
585 | static inline int irq_alloc_desc_at(unsigned int at, int node) | |
586 | { | |
587 | return irq_alloc_descs(at, at, 1, node); | |
588 | } | |
589 | ||
590 | static inline int irq_alloc_desc_from(unsigned int from, int node) | |
591 | { | |
592 | return irq_alloc_descs(-1, from, 1, node); | |
593 | } | |
594 | ||
595 | static inline void irq_free_desc(unsigned int irq) | |
596 | { | |
597 | irq_free_descs(irq, 1); | |
598 | } | |
599 | ||
639bd12f PM |
600 | static inline int irq_reserve_irq(unsigned int irq) |
601 | { | |
602 | return irq_reserve_irqs(irq, 1); | |
603 | } | |
604 | ||
6a6de9ef | 605 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 606 | |
06fcb0c6 | 607 | #endif /* !CONFIG_S390 */ |
1da177e4 | 608 | |
06fcb0c6 | 609 | #endif /* _LINUX_IRQ_H */ |