Commit | Line | Data |
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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
75ffc007 | 18 | #include <linux/irqhandler.h> |
908dcecd | 19 | #include <linux/irqreturn.h> |
dd3a1db9 | 20 | #include <linux/irqnr.h> |
77904fd6 | 21 | #include <linux/errno.h> |
503e5763 | 22 | #include <linux/topology.h> |
3aa551c9 | 23 | #include <linux/wait.h> |
332fd7c4 | 24 | #include <linux/io.h> |
1da177e4 LT |
25 | |
26 | #include <asm/irq.h> | |
27 | #include <asm/ptrace.h> | |
7d12e780 | 28 | #include <asm/irq_regs.h> |
1da177e4 | 29 | |
ab7798ff | 30 | struct seq_file; |
ec53cf23 | 31 | struct module; |
515085ef | 32 | struct msi_msg; |
1b7047ed | 33 | enum irqchip_irq_state; |
57a58a94 | 34 | |
1da177e4 LT |
35 | /* |
36 | * IRQ line status. | |
6e213616 | 37 | * |
5d4d8fc9 TG |
38 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
39 | * | |
40 | * IRQ_TYPE_NONE - default, unspecified type | |
41 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
42 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
43 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
44 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
45 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
46 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
47 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
48 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
49 | * to setup the HW to a sane default (used | |
50 | * by irqdomain map() callbacks to synchronize | |
51 | * the HW state and SW flags for a newly | |
52 | * allocated descriptor). | |
53 | * | |
5d4d8fc9 TG |
54 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
55 | * | |
56 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
57 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
58 | * updated in the code when the above trigger | |
0911f124 | 59 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
60 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
61 | * it from affinity setting | |
62 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
63 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
64 | * request_irq() | |
7f1b1244 | 65 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
66 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
67 | * request/setup_irq() | |
68 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
69 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
92068d17 | 70 | * IRQ_NESTED_THREAD - Interrupt nests into another thread |
31d9d9b6 | 71 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
72 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
73 | * it from the spurious interrupt detection | |
74 | * mechanism and from core side polling. | |
e9849777 | 75 | * IRQ_DISABLE_UNLAZY - Disable lazy irq disable |
1da177e4 | 76 | */ |
5d4d8fc9 TG |
77 | enum { |
78 | IRQ_TYPE_NONE = 0x00000000, | |
79 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
80 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
81 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
82 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
83 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
84 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
85 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 86 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
87 | |
88 | IRQ_TYPE_PROBE = 0x00000010, | |
89 | ||
90 | IRQ_LEVEL = (1 << 8), | |
91 | IRQ_PER_CPU = (1 << 9), | |
92 | IRQ_NOPROBE = (1 << 10), | |
93 | IRQ_NOREQUEST = (1 << 11), | |
94 | IRQ_NOAUTOEN = (1 << 12), | |
95 | IRQ_NO_BALANCING = (1 << 13), | |
96 | IRQ_MOVE_PCNTXT = (1 << 14), | |
97 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 98 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 99 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 100 | IRQ_IS_POLLED = (1 << 18), |
e9849777 | 101 | IRQ_DISABLE_UNLAZY = (1 << 19), |
5d4d8fc9 | 102 | }; |
950f4427 | 103 | |
44247184 TG |
104 | #define IRQF_MODIFY_MASK \ |
105 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 106 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd | 107 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
e9849777 | 108 | IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) |
44247184 | 109 | |
8f53f924 TG |
110 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
111 | ||
3b8249e7 TG |
112 | /* |
113 | * Return value for chip->irq_set_affinity() | |
114 | * | |
9df872fa JL |
115 | * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity |
116 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity | |
2cb62547 JL |
117 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
118 | * support stacked irqchips, which indicates skipping | |
119 | * all descendent irqchips. | |
3b8249e7 TG |
120 | */ |
121 | enum { | |
122 | IRQ_SET_MASK_OK = 0, | |
123 | IRQ_SET_MASK_OK_NOCOPY, | |
2cb62547 | 124 | IRQ_SET_MASK_OK_DONE, |
3b8249e7 TG |
125 | }; |
126 | ||
5b912c10 | 127 | struct msi_desc; |
08a543ad | 128 | struct irq_domain; |
6a6de9ef | 129 | |
ff7dcd44 | 130 | /** |
0d0b4c86 JL |
131 | * struct irq_common_data - per irq data shared by all irqchips |
132 | * @state_use_accessors: status information for irq chip functions. | |
133 | * Use accessor functions to deal with it | |
449e9cae | 134 | * @node: node index useful for balancing |
af7080e0 | 135 | * @handler_data: per-IRQ data for the irq_chip methods |
955bfe59 QY |
136 | * @affinity: IRQ affinity on SMP. If this is an IPI |
137 | * related irq, then this is the mask of the | |
138 | * CPUs to which an IPI can be sent. | |
b237721c | 139 | * @msi_desc: MSI descriptor |
0d0b4c86 JL |
140 | */ |
141 | struct irq_common_data { | |
142 | unsigned int state_use_accessors; | |
449e9cae JL |
143 | #ifdef CONFIG_NUMA |
144 | unsigned int node; | |
145 | #endif | |
af7080e0 | 146 | void *handler_data; |
b237721c | 147 | struct msi_desc *msi_desc; |
9df872fa | 148 | cpumask_var_t affinity; |
0d0b4c86 JL |
149 | }; |
150 | ||
151 | /** | |
152 | * struct irq_data - per irq chip data passed down to chip functions | |
966dc736 | 153 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 154 | * @irq: interrupt number |
08a543ad | 155 | * @hwirq: hardware interrupt number, local to the interrupt domain |
0d0b4c86 | 156 | * @common: point to data shared by all irqchips |
ff7dcd44 | 157 | * @chip: low level interrupt hardware access |
08a543ad GL |
158 | * @domain: Interrupt translation domain; responsible for mapping |
159 | * between hwirq number and linux irq number. | |
f8264e34 JL |
160 | * @parent_data: pointer to parent struct irq_data to support hierarchy |
161 | * irq_domain | |
ff7dcd44 TG |
162 | * @chip_data: platform-specific per-chip private data for the chip |
163 | * methods, to allow shared chip implementations | |
ff7dcd44 TG |
164 | */ |
165 | struct irq_data { | |
966dc736 | 166 | u32 mask; |
ff7dcd44 | 167 | unsigned int irq; |
08a543ad | 168 | unsigned long hwirq; |
0d0b4c86 | 169 | struct irq_common_data *common; |
ff7dcd44 | 170 | struct irq_chip *chip; |
08a543ad | 171 | struct irq_domain *domain; |
f8264e34 JL |
172 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
173 | struct irq_data *parent_data; | |
174 | #endif | |
ff7dcd44 | 175 | void *chip_data; |
ff7dcd44 TG |
176 | }; |
177 | ||
f230b6d5 | 178 | /* |
0d0b4c86 | 179 | * Bit masks for irq_common_data.state_use_accessors |
f230b6d5 | 180 | * |
876dbd4c | 181 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 182 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
183 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
184 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 185 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 186 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
187 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
188 | * from suspend | |
e1ef8241 TG |
189 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
190 | * context | |
32f4125e TG |
191 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
192 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
193 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 194 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
fc569712 | 195 | * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU |
f230b6d5 TG |
196 | */ |
197 | enum { | |
876dbd4c | 198 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
199 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
200 | IRQD_NO_BALANCING = (1 << 10), | |
201 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 202 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 203 | IRQD_LEVEL = (1 << 13), |
7f94226f | 204 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 205 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 206 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
207 | IRQD_IRQ_MASKED = (1 << 17), |
208 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 209 | IRQD_WAKEUP_ARMED = (1 << 19), |
fc569712 | 210 | IRQD_FORWARDED_TO_VCPU = (1 << 20), |
f230b6d5 TG |
211 | }; |
212 | ||
0d0b4c86 JL |
213 | #define __irqd_to_state(d) ((d)->common->state_use_accessors) |
214 | ||
f230b6d5 TG |
215 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
216 | { | |
0d0b4c86 | 217 | return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; |
f230b6d5 TG |
218 | } |
219 | ||
a005677b TG |
220 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
221 | { | |
0d0b4c86 | 222 | return __irqd_to_state(d) & IRQD_PER_CPU; |
a005677b TG |
223 | } |
224 | ||
225 | static inline bool irqd_can_balance(struct irq_data *d) | |
226 | { | |
0d0b4c86 | 227 | return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
a005677b TG |
228 | } |
229 | ||
2bdd1055 TG |
230 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
231 | { | |
0d0b4c86 | 232 | return __irqd_to_state(d) & IRQD_AFFINITY_SET; |
2bdd1055 TG |
233 | } |
234 | ||
ee38c04b TG |
235 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
236 | { | |
0d0b4c86 | 237 | __irqd_to_state(d) |= IRQD_AFFINITY_SET; |
ee38c04b TG |
238 | } |
239 | ||
876dbd4c TG |
240 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
241 | { | |
0d0b4c86 | 242 | return __irqd_to_state(d) & IRQD_TRIGGER_MASK; |
876dbd4c TG |
243 | } |
244 | ||
245 | /* | |
246 | * Must only be called inside irq_chip.irq_set_type() functions. | |
247 | */ | |
248 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
249 | { | |
0d0b4c86 JL |
250 | __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; |
251 | __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; | |
876dbd4c TG |
252 | } |
253 | ||
254 | static inline bool irqd_is_level_type(struct irq_data *d) | |
255 | { | |
0d0b4c86 | 256 | return __irqd_to_state(d) & IRQD_LEVEL; |
876dbd4c TG |
257 | } |
258 | ||
7f94226f TG |
259 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
260 | { | |
0d0b4c86 | 261 | return __irqd_to_state(d) & IRQD_WAKEUP_STATE; |
7f94226f TG |
262 | } |
263 | ||
e1ef8241 TG |
264 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
265 | { | |
0d0b4c86 | 266 | return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; |
e1ef8241 TG |
267 | } |
268 | ||
801a0e9a TG |
269 | static inline bool irqd_irq_disabled(struct irq_data *d) |
270 | { | |
0d0b4c86 | 271 | return __irqd_to_state(d) & IRQD_IRQ_DISABLED; |
801a0e9a TG |
272 | } |
273 | ||
32f4125e TG |
274 | static inline bool irqd_irq_masked(struct irq_data *d) |
275 | { | |
0d0b4c86 | 276 | return __irqd_to_state(d) & IRQD_IRQ_MASKED; |
32f4125e TG |
277 | } |
278 | ||
279 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
280 | { | |
0d0b4c86 | 281 | return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; |
32f4125e TG |
282 | } |
283 | ||
b76f1674 TG |
284 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
285 | { | |
0d0b4c86 | 286 | return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; |
b76f1674 TG |
287 | } |
288 | ||
fc569712 TG |
289 | static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) |
290 | { | |
291 | return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; | |
292 | } | |
293 | ||
294 | static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) | |
295 | { | |
296 | __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; | |
297 | } | |
298 | ||
299 | static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) | |
300 | { | |
301 | __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; | |
302 | } | |
b76f1674 | 303 | |
a699e4e4 GL |
304 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
305 | { | |
306 | return d->hwirq; | |
307 | } | |
308 | ||
8fee5c36 | 309 | /** |
6a6de9ef | 310 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
311 | * |
312 | * @name: name for /proc/interrupts | |
f8822657 TG |
313 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
314 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
315 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
316 | * @irq_disable: disable the interrupt | |
317 | * @irq_ack: start of a new interrupt | |
318 | * @irq_mask: mask an interrupt source | |
319 | * @irq_mask_ack: ack and mask an interrupt source | |
320 | * @irq_unmask: unmask an interrupt source | |
321 | * @irq_eoi: end of interrupt | |
322 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
323 | * @irq_retrigger: resend an IRQ to the CPU | |
324 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
325 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
326 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
327 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
328 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
329 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
be9b22b6 BN |
330 | * @irq_suspend: function called from core code on suspend once per |
331 | * chip, when one or more interrupts are installed | |
332 | * @irq_resume: function called from core code on resume once per chip, | |
333 | * when one ore more interrupts are installed | |
cfefd21e | 334 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
d0051816 | 335 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 336 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
337 | * @irq_request_resources: optional to request resources before calling |
338 | * any other callback related to this irq | |
339 | * @irq_release_resources: optional to release resources acquired with | |
340 | * irq_request_resources | |
515085ef | 341 | * @irq_compose_msi_msg: optional to compose message content for MSI |
9dde55b7 | 342 | * @irq_write_msi_msg: optional to write message content for MSI |
1b7047ed MZ |
343 | * @irq_get_irqchip_state: return the internal state of an interrupt |
344 | * @irq_set_irqchip_state: set the internal state of a interrupt | |
0a4377de | 345 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
2bff17ad | 346 | * @flags: chip specific flags |
1da177e4 | 347 | */ |
6a6de9ef TG |
348 | struct irq_chip { |
349 | const char *name; | |
f8822657 TG |
350 | unsigned int (*irq_startup)(struct irq_data *data); |
351 | void (*irq_shutdown)(struct irq_data *data); | |
352 | void (*irq_enable)(struct irq_data *data); | |
353 | void (*irq_disable)(struct irq_data *data); | |
354 | ||
355 | void (*irq_ack)(struct irq_data *data); | |
356 | void (*irq_mask)(struct irq_data *data); | |
357 | void (*irq_mask_ack)(struct irq_data *data); | |
358 | void (*irq_unmask)(struct irq_data *data); | |
359 | void (*irq_eoi)(struct irq_data *data); | |
360 | ||
361 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
362 | int (*irq_retrigger)(struct irq_data *data); | |
363 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
364 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
365 | ||
366 | void (*irq_bus_lock)(struct irq_data *data); | |
367 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
368 | ||
0fdb4b25 DD |
369 | void (*irq_cpu_online)(struct irq_data *data); |
370 | void (*irq_cpu_offline)(struct irq_data *data); | |
371 | ||
cfefd21e TG |
372 | void (*irq_suspend)(struct irq_data *data); |
373 | void (*irq_resume)(struct irq_data *data); | |
374 | void (*irq_pm_shutdown)(struct irq_data *data); | |
375 | ||
d0051816 TG |
376 | void (*irq_calc_mask)(struct irq_data *data); |
377 | ||
ab7798ff | 378 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
379 | int (*irq_request_resources)(struct irq_data *data); |
380 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 381 | |
515085ef | 382 | void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
9dde55b7 | 383 | void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
515085ef | 384 | |
1b7047ed MZ |
385 | int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); |
386 | int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); | |
387 | ||
0a4377de JL |
388 | int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); |
389 | ||
2bff17ad | 390 | unsigned long flags; |
1da177e4 LT |
391 | }; |
392 | ||
d4d5e089 TG |
393 | /* |
394 | * irq_chip specific flags | |
395 | * | |
77694b40 TG |
396 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
397 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 398 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
399 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
400 | * when irq enabled | |
60f96b41 | 401 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 402 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 403 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
404 | */ |
405 | enum { | |
406 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 407 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 408 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 409 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 410 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 411 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 412 | IRQCHIP_EOI_THREADED = (1 << 6), |
d4d5e089 TG |
413 | }; |
414 | ||
e144710b | 415 | #include <linux/irqdesc.h> |
0b8f1efa | 416 | |
34ffdb72 IM |
417 | /* |
418 | * Pick up the arch-dependent methods: | |
419 | */ | |
420 | #include <asm/hw_irq.h> | |
1da177e4 | 421 | |
b683de2b TG |
422 | #ifndef NR_IRQS_LEGACY |
423 | # define NR_IRQS_LEGACY 0 | |
424 | #endif | |
425 | ||
1318a481 TG |
426 | #ifndef ARCH_IRQ_INIT_FLAGS |
427 | # define ARCH_IRQ_INIT_FLAGS 0 | |
428 | #endif | |
429 | ||
c1594b77 | 430 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 431 | |
e144710b | 432 | struct irqaction; |
06fcb0c6 | 433 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 434 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
435 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
436 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 437 | |
0fdb4b25 DD |
438 | extern void irq_cpu_online(void); |
439 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
440 | extern int irq_set_affinity_locked(struct irq_data *data, |
441 | const struct cpumask *cpumask, bool force); | |
0a4377de | 442 | extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); |
0fdb4b25 | 443 | |
f1e0bb0a YY |
444 | extern void irq_migrate_all_off_this_cpu(void); |
445 | ||
3a3856d0 | 446 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
447 | void irq_move_irq(struct irq_data *data); |
448 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 449 | #else |
a439520f TG |
450 | static inline void irq_move_irq(struct irq_data *data) { } |
451 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 452 | #endif |
54d5d424 | 453 | |
1da177e4 | 454 | extern int no_irq_affinity; |
1da177e4 | 455 | |
293a7a0a TG |
456 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
457 | int irq_set_parent(int irq, int parent_irq); | |
458 | #else | |
459 | static inline int irq_set_parent(int irq, int parent_irq) | |
460 | { | |
461 | return 0; | |
462 | } | |
463 | #endif | |
464 | ||
6a6de9ef TG |
465 | /* |
466 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 467 | * callable via desc->handle_irq() |
6a6de9ef | 468 | */ |
bd0b9ac4 TG |
469 | extern void handle_level_irq(struct irq_desc *desc); |
470 | extern void handle_fasteoi_irq(struct irq_desc *desc); | |
471 | extern void handle_edge_irq(struct irq_desc *desc); | |
472 | extern void handle_edge_eoi_irq(struct irq_desc *desc); | |
473 | extern void handle_simple_irq(struct irq_desc *desc); | |
474 | extern void handle_percpu_irq(struct irq_desc *desc); | |
475 | extern void handle_percpu_devid_irq(struct irq_desc *desc); | |
476 | extern void handle_bad_irq(struct irq_desc *desc); | |
31b47cf7 | 477 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 478 | |
515085ef | 479 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
85f08c17 | 480 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
3cfeffc2 SA |
481 | extern void irq_chip_enable_parent(struct irq_data *data); |
482 | extern void irq_chip_disable_parent(struct irq_data *data); | |
85f08c17 JL |
483 | extern void irq_chip_ack_parent(struct irq_data *data); |
484 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); | |
56e8abab YC |
485 | extern void irq_chip_mask_parent(struct irq_data *data); |
486 | extern void irq_chip_unmask_parent(struct irq_data *data); | |
487 | extern void irq_chip_eoi_parent(struct irq_data *data); | |
488 | extern int irq_chip_set_affinity_parent(struct irq_data *data, | |
489 | const struct cpumask *dest, | |
490 | bool force); | |
08b55e2a | 491 | extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); |
0a4377de JL |
492 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
493 | void *vcpu_info); | |
b7560de1 | 494 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
85f08c17 JL |
495 | #endif |
496 | ||
6a6de9ef | 497 | /* Handling of unhandled and spurious interrupts: */ |
0dcdbc97 | 498 | extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); |
1da177e4 | 499 | |
a4633adc | 500 | |
6a6de9ef TG |
501 | /* Enable/disable irq debugging output: */ |
502 | extern int noirqdebug_setup(char *str); | |
503 | ||
504 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
505 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
506 | ||
f8b5473f | 507 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 508 | extern struct irq_chip no_irq_chip; |
f8b5473f | 509 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 510 | |
145fc655 | 511 | extern void |
3836ca08 | 512 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
513 | irq_flow_handler_t handle, const char *name); |
514 | ||
3836ca08 TG |
515 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
516 | irq_flow_handler_t handle) | |
517 | { | |
518 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
519 | } | |
520 | ||
31d9d9b6 MZ |
521 | extern int irq_set_percpu_devid(unsigned int irq); |
522 | ||
6a6de9ef | 523 | extern void |
3836ca08 | 524 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 525 | const char *name); |
1da177e4 | 526 | |
6a6de9ef | 527 | static inline void |
3836ca08 | 528 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 529 | { |
3836ca08 | 530 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
531 | } |
532 | ||
533 | /* | |
534 | * Set a highlevel chained flow handler for a given IRQ. | |
535 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 536 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
537 | */ |
538 | static inline void | |
3836ca08 | 539 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 540 | { |
3836ca08 | 541 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
542 | } |
543 | ||
3b0f95be RK |
544 | /* |
545 | * Set a highlevel chained flow handler and its data for a given IRQ. | |
546 | * (a chained handler is automatically enabled and set to | |
547 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) | |
548 | */ | |
549 | void | |
550 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
551 | void *data); | |
552 | ||
44247184 TG |
553 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
554 | ||
555 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
556 | { | |
557 | irq_modify_status(irq, 0, set); | |
558 | } | |
559 | ||
560 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
561 | { | |
562 | irq_modify_status(irq, clr, 0); | |
563 | } | |
564 | ||
a0cd9ca2 | 565 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
566 | { |
567 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
568 | } | |
569 | ||
a0cd9ca2 | 570 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
571 | { |
572 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
573 | } | |
46f4f8f6 | 574 | |
7f1b1244 PM |
575 | static inline void irq_set_nothread(unsigned int irq) |
576 | { | |
577 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
578 | } | |
579 | ||
580 | static inline void irq_set_thread(unsigned int irq) | |
581 | { | |
582 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
583 | } | |
584 | ||
6f91a52d TG |
585 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
586 | { | |
587 | if (nest) | |
588 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
589 | else | |
590 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
591 | } | |
592 | ||
31d9d9b6 MZ |
593 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
594 | { | |
595 | irq_set_status_flags(irq, | |
596 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
597 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
598 | } | |
599 | ||
3a16d713 | 600 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
601 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
602 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
603 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
604 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
605 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
606 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
607 | struct msi_desc *entry); | |
f303a6dd | 608 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 609 | |
a0cd9ca2 | 610 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
611 | { |
612 | struct irq_data *d = irq_get_irq_data(irq); | |
613 | return d ? d->chip : NULL; | |
614 | } | |
615 | ||
616 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
617 | { | |
618 | return d->chip; | |
619 | } | |
620 | ||
a0cd9ca2 | 621 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
622 | { |
623 | struct irq_data *d = irq_get_irq_data(irq); | |
624 | return d ? d->chip_data : NULL; | |
625 | } | |
626 | ||
627 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
628 | { | |
629 | return d->chip_data; | |
630 | } | |
631 | ||
a0cd9ca2 | 632 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
633 | { |
634 | struct irq_data *d = irq_get_irq_data(irq); | |
af7080e0 | 635 | return d ? d->common->handler_data : NULL; |
f303a6dd TG |
636 | } |
637 | ||
a0cd9ca2 | 638 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd | 639 | { |
af7080e0 | 640 | return d->common->handler_data; |
f303a6dd TG |
641 | } |
642 | ||
a0cd9ca2 | 643 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
644 | { |
645 | struct irq_data *d = irq_get_irq_data(irq); | |
b237721c | 646 | return d ? d->common->msi_desc : NULL; |
f303a6dd TG |
647 | } |
648 | ||
c391f262 | 649 | static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) |
f303a6dd | 650 | { |
b237721c | 651 | return d->common->msi_desc; |
f303a6dd TG |
652 | } |
653 | ||
1f6236bf JMC |
654 | static inline u32 irq_get_trigger_type(unsigned int irq) |
655 | { | |
656 | struct irq_data *d = irq_get_irq_data(irq); | |
657 | return d ? irqd_get_trigger_type(d) : 0; | |
658 | } | |
659 | ||
449e9cae | 660 | static inline int irq_common_data_get_node(struct irq_common_data *d) |
6783011b | 661 | { |
449e9cae | 662 | #ifdef CONFIG_NUMA |
6783011b | 663 | return d->node; |
449e9cae JL |
664 | #else |
665 | return 0; | |
666 | #endif | |
667 | } | |
668 | ||
669 | static inline int irq_data_get_node(struct irq_data *d) | |
670 | { | |
671 | return irq_common_data_get_node(d->common); | |
6783011b JL |
672 | } |
673 | ||
c64301a2 JL |
674 | static inline struct cpumask *irq_get_affinity_mask(int irq) |
675 | { | |
676 | struct irq_data *d = irq_get_irq_data(irq); | |
677 | ||
9df872fa | 678 | return d ? d->common->affinity : NULL; |
c64301a2 JL |
679 | } |
680 | ||
681 | static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) | |
682 | { | |
9df872fa | 683 | return d->common->affinity; |
c64301a2 JL |
684 | } |
685 | ||
62a08ae2 TG |
686 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
687 | ||
b6873807 SAS |
688 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
689 | struct module *owner); | |
690 | ||
ec53cf23 PG |
691 | /* use macros to avoid needing export.h for THIS_MODULE */ |
692 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
693 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) | |
b6873807 | 694 | |
ec53cf23 PG |
695 | #define irq_alloc_desc(node) \ |
696 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 697 | |
ec53cf23 PG |
698 | #define irq_alloc_desc_at(at, node) \ |
699 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 700 | |
ec53cf23 PG |
701 | #define irq_alloc_desc_from(from, node) \ |
702 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 703 | |
51906e77 AG |
704 | #define irq_alloc_descs_from(from, cnt, node) \ |
705 | irq_alloc_descs(-1, from, cnt, node) | |
706 | ||
ec53cf23 | 707 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
708 | static inline void irq_free_desc(unsigned int irq) |
709 | { | |
710 | irq_free_descs(irq, 1); | |
711 | } | |
712 | ||
7b6ef126 TG |
713 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
714 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
715 | static inline unsigned int irq_alloc_hwirq(int node) | |
716 | { | |
717 | return irq_alloc_hwirqs(1, node); | |
718 | } | |
719 | void irq_free_hwirqs(unsigned int from, int cnt); | |
720 | static inline void irq_free_hwirq(unsigned int irq) | |
721 | { | |
722 | return irq_free_hwirqs(irq, 1); | |
723 | } | |
724 | int arch_setup_hwirq(unsigned int irq, int node); | |
725 | void arch_teardown_hwirq(unsigned int irq); | |
726 | #endif | |
727 | ||
c940e01c TG |
728 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
729 | void irq_init_desc(unsigned int irq); | |
730 | #endif | |
731 | ||
7d828062 TG |
732 | /** |
733 | * struct irq_chip_regs - register offsets for struct irq_gci | |
734 | * @enable: Enable register offset to reg_base | |
735 | * @disable: Disable register offset to reg_base | |
736 | * @mask: Mask register offset to reg_base | |
737 | * @ack: Ack register offset to reg_base | |
738 | * @eoi: Eoi register offset to reg_base | |
739 | * @type: Type configuration register offset to reg_base | |
740 | * @polarity: Polarity configuration register offset to reg_base | |
741 | */ | |
742 | struct irq_chip_regs { | |
743 | unsigned long enable; | |
744 | unsigned long disable; | |
745 | unsigned long mask; | |
746 | unsigned long ack; | |
747 | unsigned long eoi; | |
748 | unsigned long type; | |
749 | unsigned long polarity; | |
750 | }; | |
751 | ||
752 | /** | |
753 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
754 | * @chip: The real interrupt chip which provides the callbacks | |
755 | * @regs: Register offsets for this chip | |
756 | * @handler: Flow handler associated with this chip | |
757 | * @type: Chip can handle these flow types | |
899f0e66 GF |
758 | * @mask_cache_priv: Cached mask register private to the chip type |
759 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
760 | * |
761 | * A irq_generic_chip can have several instances of irq_chip_type when | |
762 | * it requires different functions and register offsets for different | |
763 | * flow types. | |
764 | */ | |
765 | struct irq_chip_type { | |
766 | struct irq_chip chip; | |
767 | struct irq_chip_regs regs; | |
768 | irq_flow_handler_t handler; | |
769 | u32 type; | |
899f0e66 GF |
770 | u32 mask_cache_priv; |
771 | u32 *mask_cache; | |
7d828062 TG |
772 | }; |
773 | ||
774 | /** | |
775 | * struct irq_chip_generic - Generic irq chip data structure | |
776 | * @lock: Lock to protect register and cache data access | |
777 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
778 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
779 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
be9b22b6 BN |
780 | * @suspend: Function called from core code on suspend once per |
781 | * chip; can be useful instead of irq_chip::suspend to | |
782 | * handle chip details even when no interrupts are in use | |
783 | * @resume: Function called from core code on resume once per chip; | |
784 | * can be useful instead of irq_chip::suspend to handle | |
785 | * chip details even when no interrupts are in use | |
7d828062 TG |
786 | * @irq_base: Interrupt base nr for this chip |
787 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 788 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
789 | * @type_cache: Cached type register |
790 | * @polarity_cache: Cached polarity register | |
791 | * @wake_enabled: Interrupt can wakeup from suspend | |
792 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
793 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
794 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 795 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 796 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 797 | * @domain: irq domain pointer |
cfefd21e | 798 | * @list: List head for keeping track of instances |
7d828062 TG |
799 | * @chip_types: Array of interrupt irq_chip_types |
800 | * | |
801 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
802 | * implementations which can be associated to a particular irq line of | |
803 | * an irq_chip_generic instance. That allows to share and protect | |
804 | * state in an irq_chip_generic instance when we need to implement | |
805 | * different flow mechanisms (level/edge) for it. | |
806 | */ | |
807 | struct irq_chip_generic { | |
808 | raw_spinlock_t lock; | |
809 | void __iomem *reg_base; | |
2b280376 KC |
810 | u32 (*reg_readl)(void __iomem *addr); |
811 | void (*reg_writel)(u32 val, void __iomem *addr); | |
be9b22b6 BN |
812 | void (*suspend)(struct irq_chip_generic *gc); |
813 | void (*resume)(struct irq_chip_generic *gc); | |
7d828062 TG |
814 | unsigned int irq_base; |
815 | unsigned int irq_cnt; | |
816 | u32 mask_cache; | |
817 | u32 type_cache; | |
818 | u32 polarity_cache; | |
819 | u32 wake_enabled; | |
820 | u32 wake_active; | |
821 | unsigned int num_ct; | |
822 | void *private; | |
088f40b7 | 823 | unsigned long installed; |
e8bd834f | 824 | unsigned long unused; |
088f40b7 | 825 | struct irq_domain *domain; |
cfefd21e | 826 | struct list_head list; |
7d828062 TG |
827 | struct irq_chip_type chip_types[0]; |
828 | }; | |
829 | ||
830 | /** | |
831 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
832 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
833 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
834 | * irq chips which need to call irq_set_wake() on | |
835 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 836 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 837 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
b7905595 | 838 | * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) |
7d828062 TG |
839 | */ |
840 | enum irq_gc_flags { | |
841 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
842 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 843 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 844 | IRQ_GC_NO_MASK = 1 << 3, |
b7905595 | 845 | IRQ_GC_BE_IO = 1 << 4, |
7d828062 TG |
846 | }; |
847 | ||
088f40b7 TG |
848 | /* |
849 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
850 | * @irqs_per_chip: Number of interrupts per chip | |
851 | * @num_chips: Number of chips | |
852 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
853 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
854 | * @gc_flags: Generic chip specific setup flags | |
855 | * @gc: Array of pointers to generic interrupt chips | |
856 | */ | |
857 | struct irq_domain_chip_generic { | |
858 | unsigned int irqs_per_chip; | |
859 | unsigned int num_chips; | |
860 | unsigned int irq_flags_to_clear; | |
861 | unsigned int irq_flags_to_set; | |
862 | enum irq_gc_flags gc_flags; | |
863 | struct irq_chip_generic *gc[0]; | |
864 | }; | |
865 | ||
7d828062 TG |
866 | /* Generic chip callback functions */ |
867 | void irq_gc_noop(struct irq_data *d); | |
868 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
869 | void irq_gc_mask_set_bit(struct irq_data *d); | |
870 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
871 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
872 | void irq_gc_ack_set_bit(struct irq_data *d); |
873 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
874 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
875 | void irq_gc_eoi(struct irq_data *d); | |
876 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
877 | ||
878 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
879 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
880 | irq_hw_number_t hw_irq); | |
7d828062 TG |
881 | struct irq_chip_generic * |
882 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
883 | void __iomem *reg_base, irq_flow_handler_t handler); | |
884 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
885 | enum irq_gc_flags flags, unsigned int clr, | |
886 | unsigned int set); | |
887 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
888 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
889 | unsigned int clr, unsigned int set); | |
7d828062 | 890 | |
088f40b7 TG |
891 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
892 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, | |
893 | int num_ct, const char *name, | |
894 | irq_flow_handler_t handler, | |
895 | unsigned int clr, unsigned int set, | |
896 | enum irq_gc_flags flags); | |
897 | ||
898 | ||
7d828062 TG |
899 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
900 | { | |
901 | return container_of(d->chip, struct irq_chip_type, chip); | |
902 | } | |
903 | ||
904 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
905 | ||
906 | #ifdef CONFIG_SMP | |
907 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
908 | { | |
909 | raw_spin_lock(&gc->lock); | |
910 | } | |
911 | ||
912 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
913 | { | |
914 | raw_spin_unlock(&gc->lock); | |
915 | } | |
916 | #else | |
917 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
918 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
919 | #endif | |
920 | ||
332fd7c4 KC |
921 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
922 | u32 val, int reg_offset) | |
923 | { | |
2b280376 KC |
924 | if (gc->reg_writel) |
925 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
926 | else | |
927 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
928 | } |
929 | ||
930 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
931 | int reg_offset) | |
932 | { | |
2b280376 KC |
933 | if (gc->reg_readl) |
934 | return gc->reg_readl(gc->reg_base + reg_offset); | |
935 | else | |
936 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
937 | } |
938 | ||
06fcb0c6 | 939 | #endif /* _LINUX_IRQ_H */ |