[deliverable/linux.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>

#include <asm/irq.h>
#include <asm/ptrace.h>

/*
 * IRQ line status.
 */
#define IRQ_INPROGRESS	1	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED	2	/* IRQ disabled - do not enter! */
#define IRQ_PENDING	4	/* IRQ pending - replay on enable */
#define IRQ_REPLAY	8	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT	16	/* IRQ is being autodetected */
#define IRQ_WAITING	32	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL	64	/* IRQ level triggered */
#define IRQ_MASKED	128	/* IRQ masked - shouldn't be seen again */
#ifdef CONFIG_IRQ_PER_CPU
# define IRQ_PER_CPU	256	/* IRQ is per CPU */
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
#else
# define CHECK_IRQ_PER_CPU(var) 0
#endif

#define IRQ_NOPROBE	512	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST	1024	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN	2048	/* IRQ will not be enabled on request irq */
#define IRQ_DELAYED_DISABLE \
			4096	/* IRQ disable (masking) happens delayed. */

/*
 * IRQ types, see also include/linux/interrupt.h
 */
#define IRQ_TYPE_NONE		0x0000		/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x0001		/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x0002		/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x0004		/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x0008		/* Level low type */
#define IRQ_TYPE_SIMPLE		0x0010		/* Simple type */
#define IRQ_TYPE_PERCPU		0x0020		/* Per CPU type */
#define IRQ_TYPE_PROBE		0x0040		/* Probing in progress */

struct proc_dir_entry;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @end:		end of interrupt
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq, cpumask_t dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

/**
 * struct irq_desc - interrupt descriptor
 *
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @irq_count:		stats field to detect stalled irqs
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @move_irq:		need to re-target IRQ destination
 * @dir:		/proc/irq/ procfs entry
 * @affinity_entry:	/proc/irq/smp_affinity procfs entry on SMP
 *
 * Pad this out to 32 bytes for cache and indexing reasons.
 */
struct irq_desc {
	void fastcall		(*handle_irq)(unsigned int irq,
					      struct irq_desc *desc,
					      struct pt_regs *regs);
	struct irq_chip		*chip;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_t		affinity;
	unsigned int		cpu;
#endif
#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
	cpumask_t		pending_mask;
	unsigned int		move_irq;	/* need to re-target IRQ dest */
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *dir;
#endif
} ____cacheline_aligned;

extern struct irq_desc irq_desc[NR_IRQS];

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
typedef struct irq_chip		hw_irq_controller;
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
	irq_desc[irq].affinity = mask;
}
#else
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_SMP

#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)

void set_pending_irq(unsigned int irq, cpumask_t mask);
void move_native_irq(int irq);

#ifdef CONFIG_PCI_MSI
/*
 * Wonder why these are dummies?
 * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
 * counter part after translating the vector to irq info. We need to perform
 * this operation on the real irq, when we dont use vector, i.e when
 * pci_use_vector() is false.
 */
static inline void move_irq(int irq)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
}

#else /* CONFIG_PCI_MSI */

static inline void move_irq(int irq)
{
	move_native_irq(irq);
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_PCI_MSI */

#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_irq(x)
#define move_native_irq(x)

#endif /* CONFIG_SMP */

#ifdef CONFIG_IRQBALANCE
extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
#else
static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_AUTO_IRQ_AFFINITY
extern int select_smp_affinity(unsigned int irq);
#else
static inline int select_smp_affinity(unsigned int irq)
{
	return 1;
}
#endif

extern int no_irq_affinity;

/* Handle irq action chains: */
extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
			    struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void fastcall
handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_fastack_irq(unsigned int irq, struct irq_desc *desc,
			 struct pt_regs *regs);
extern void fastcall
handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_simple_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_bad_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);

/*
 * Get a descriptive string for the highlevel handler, for
 * /proc/interrupts output:
 */
extern const char *
handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *));

/*
 * Monolithic do_IRQ implementation.
 * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
 */
extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
{
	struct irq_desc *desc = irq_desc + irq;

	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc, regs);
	else
		__do_IRQ(irq, regs);
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   int action_ret, struct pt_regs *regs);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Initialize /proc/irq/ */
extern void init_irq_proc(void);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementation: */
extern struct irq_chip no_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 void fastcall (*handle)(unsigned int,
						 struct irq_desc *,
						 struct pt_regs *));
extern void
__set_irq_handler(unsigned int irq,
		  void fastcall (*handle)(unsigned int, struct irq_desc *,
					  struct pt_regs *),
		  int is_chained);

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq,
		void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *))
{
	__set_irq_handler(irq, handle, 0);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			void fastcall (*handle)(unsigned int, struct irq_desc *,
						struct pt_regs *))
{
	__set_irq_handler(irq, handle, 1);
}

/* Set/get chip/data for an IRQ: */

extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);

#define get_irq_chip(irq)	(irq_desc[irq].chip)
#define get_irq_chip_data(irq)	(irq_desc[irq].chip_data)
#define get_irq_data(irq)	(irq_desc[irq].handler_data)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
1da177e4 LT	21
	22	#include <asm/irq.h>
	23	#include <asm/ptrace.h>
	24
	25	/*
	26	* IRQ line status.
	27	*/
	28	#define IRQ_INPROGRESS 1 /* IRQ handler active - do not enter! */
	29	#define IRQ_DISABLED 2 /* IRQ disabled - do not enter! */
	30	#define IRQ_PENDING 4 /* IRQ pending - replay on enable */
	31	#define IRQ_REPLAY 8 /* IRQ has been replayed but not acked yet */
	32	#define IRQ_AUTODETECT 16 /* IRQ is being autodetected */
	33	#define IRQ_WAITING 32 /* IRQ not yet seen - for autodetection */
	34	#define IRQ_LEVEL 64 /* IRQ level triggered */
	35	#define IRQ_MASKED 128 /* IRQ masked - shouldn't be seen again */
0d7012a9	36	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 KW	37	# define IRQ_PER_CPU 256 /* IRQ is per CPU */
	38	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
	39	#else
	40	# define CHECK_IRQ_PER_CPU(var) 0
	41	#endif
1da177e4	42
3418d724	43	#define IRQ_NOPROBE 512 /* IRQ is not valid for probing */
6550c775	44	#define IRQ_NOREQUEST 1024 /* IRQ cannot be requested */
94d39e1f	45	#define IRQ_NOAUTOEN 2048 /* IRQ will not be enabled on request irq */
6a6de9ef TG	46	#define IRQ_DELAYED_DISABLE \
	47	4096 /* IRQ disable (masking) happens delayed. */
	48
	49	/*
	50	* IRQ types, see also include/linux/interrupt.h
	51	*/
	52	#define IRQ_TYPE_NONE 0x0000 /* Default, unspecified type */
	53	#define IRQ_TYPE_EDGE_RISING 0x0001 /* Edge rising type */
	54	#define IRQ_TYPE_EDGE_FALLING 0x0002 /* Edge falling type */
	55	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	56	#define IRQ_TYPE_LEVEL_HIGH 0x0004 /* Level high type */
	57	#define IRQ_TYPE_LEVEL_LOW 0x0008 /* Level low type */
	58	#define IRQ_TYPE_SIMPLE 0x0010 /* Simple type */
	59	#define IRQ_TYPE_PERCPU 0x0020 /* Per CPU type */
	60	#define IRQ_TYPE_PROBE 0x0040 /* Probing in progress */
	61
	62	struct proc_dir_entry;
	63
8fee5c36	64	/**
6a6de9ef	65	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	66	*
	67	* @name: name for /proc/interrupts
	68	* @startup: start up the interrupt (defaults to ->enable if NULL)
	69	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	70	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	71	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	72	* @ack: start of a new interrupt
	73	* @mask: mask an interrupt source
	74	* @mask_ack: ack and mask an interrupt source
	75	* @unmask: unmask an interrupt source
8fee5c36 IM	76	* @end: end of interrupt
	77	* @set_affinity: set the CPU affinity on SMP machines
	78	* @retrigger: resend an IRQ to the CPU
	79	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	80	* @set_wake: enable/disable power-management wake-on of an IRQ
	81	*
	82	* @release: release function solely used by UML
6a6de9ef	83	* @typename: obsoleted by name, kept as migration helper
1da177e4	84	*/
6a6de9ef TG	85	struct irq_chip {
6a6de9ef TG	86	const char *name;
71d218b7 IM	87	unsigned int (*startup)(unsigned int irq);
	88	void (*shutdown)(unsigned int irq);
	89	void (*enable)(unsigned int irq);
	90	void (*disable)(unsigned int irq);
6a6de9ef	91
71d218b7	92	void (*ack)(unsigned int irq);
6a6de9ef TG	93	void (*mask)(unsigned int irq);
	94	void (*mask_ack)(unsigned int irq);
	95	void (*unmask)(unsigned int irq);
	96
71d218b7 IM	97	void (*end)(unsigned int irq);
71d218b7 IM	98	void (*set_affinity)(unsigned int irq, cpumask_t dest);
c0ad90a3	99	int (*retrigger)(unsigned int irq);
6a6de9ef TG	100	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	101	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	102
b77d6adc PBG	103	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	104	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	105	void (release)(unsigned int irq, void dev_id);
b77d6adc	106	#endif
6a6de9ef TG	107	/*
	108	* For compatibility, ->typename is copied into ->name.
	109	* Will disappear.
	110	*/
	111	const char *typename;
1da177e4 LT	112	};
1da177e4 LT	113
8fee5c36 IM	114	/**
	115	* struct irq_desc - interrupt descriptor
	116	*
6a6de9ef TG	117	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
	118	* @chip: low level interrupt hardware access
	119	* @handler_data: per-IRQ data for the irq_chip methods
	120	* @chip_data: platform-specific per-chip private data for the chip
	121	* methods, to allow shared chip implementations
8fee5c36 IM	122	* @action: the irq action chain
	123	* @status: status information
	124	* @depth: disable-depth, for nested irq_disable() calls
	125	* @irq_count: stats field to detect stalled irqs
	126	* @irqs_unhandled: stats field for spurious unhandled interrupts
	127	* @lock: locking for SMP
	128	* @affinity: IRQ affinity on SMP
6a6de9ef	129	* @cpu: cpu index useful for balancing
8fee5c36 IM	130	* @pending_mask: pending rebalanced interrupts
	131	* @move_irq: need to re-target IRQ destination
	132	* @dir: /proc/irq/ procfs entry
	133	* @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
1da177e4 LT	134	*
	135	* Pad this out to 32 bytes for cache and indexing reasons.
	136	*/
34ffdb72	137	struct irq_desc {
6a6de9ef TG	138	void fastcall (*handle_irq)(unsigned int irq,
	139	struct irq_desc *desc,
	140	struct pt_regs *regs);
	141	struct irq_chip *chip;
	142	void *handler_data;
71d218b7 IM	143	void *chip_data;
	144	struct irqaction action; / IRQ action list */
	145	unsigned int status; /* IRQ status */
6a6de9ef	146
71d218b7 IM	147	unsigned int depth; /* nested irq disables */
	148	unsigned int irq_count; /* For detecting broken IRQs */
	149	unsigned int irqs_unhandled;
	150	spinlock_t lock;
a53da52f	151	#ifdef CONFIG_SMP
71d218b7	152	cpumask_t affinity;
6a6de9ef	153	unsigned int cpu;
a53da52f	154	#endif
06fcb0c6	155	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
cd916d31	156	cpumask_t pending_mask;
71d218b7	157	unsigned int move_irq; /* need to re-target IRQ dest */
54d5d424	158	#endif
4a733ee1 IM	159	#ifdef CONFIG_PROC_FS
	160	struct proc_dir_entry *dir;
	161	#endif
34ffdb72	162	} ____cacheline_aligned;
1da177e4	163
34ffdb72	164	extern struct irq_desc irq_desc[NR_IRQS];
1da177e4	165
34ffdb72 IM	166	/*
	167	* Migration helpers for obsolete names, they will go away:
	168	*/
6a6de9ef TG	169	#define hw_interrupt_type irq_chip
	170	typedef struct irq_chip hw_irq_controller;
	171	#define no_irq_type no_irq_chip
34ffdb72 IM	172	typedef struct irq_desc irq_desc_t;
	173
	174	/*
	175	* Pick up the arch-dependent methods:
	176	*/
	177	#include <asm/hw_irq.h>
1da177e4	178
06fcb0c6	179	extern int setup_irq(unsigned int irq, struct irqaction *new);
1da177e4 LT	180
1da177e4 LT	181	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	182
54d5d424 AR	183	#ifdef CONFIG_SMP
	184	static inline void set_native_irq_info(int irq, cpumask_t mask)
	185	{
a53da52f	186	irq_desc[irq].affinity = mask;
54d5d424 AR	187	}
	188	#else
	189	static inline void set_native_irq_info(int irq, cpumask_t mask)
	190	{
	191	}
	192	#endif
	193
	194	#ifdef CONFIG_SMP
	195
06fcb0c6	196	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
54d5d424	197
c777ac55 AM	198	void set_pending_irq(unsigned int irq, cpumask_t mask);
c777ac55 AM	199	void move_native_irq(int irq);
54d5d424 AR	200
	201	#ifdef CONFIG_PCI_MSI
	202	/*
	203	* Wonder why these are dummies?
	204	* For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
	205	* counter part after translating the vector to irq info. We need to perform
	206	* this operation on the real irq, when we dont use vector, i.e when
	207	* pci_use_vector() is false.
	208	*/
	209	static inline void move_irq(int irq)
	210	{
	211	}
	212
	213	static inline void set_irq_info(int irq, cpumask_t mask)
	214	{
	215	}
	216
06fcb0c6	217	#else /* CONFIG_PCI_MSI */
54d5d424 AR	218
	219	static inline void move_irq(int irq)
	220	{
	221	move_native_irq(irq);
	222	}
	223
	224	static inline void set_irq_info(int irq, cpumask_t mask)
	225	{
	226	set_native_irq_info(irq, mask);
	227	}
54d5d424	228
06fcb0c6 IM	229	#endif /* CONFIG_PCI_MSI */
	230
	231	#else /* CONFIG_GENERIC_PENDING_IRQ \|\| CONFIG_IRQBALANCE */
	232
	233	static inline void move_irq(int irq)
	234	{
	235	}
	236
	237	static inline void move_native_irq(int irq)
	238	{
	239	}
	240
	241	static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
	242	{
	243	}
54d5d424	244
54d5d424 AR	245	static inline void set_irq_info(int irq, cpumask_t mask)
	246	{
	247	set_native_irq_info(irq, mask);
	248	}
	249
06fcb0c6	250	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	251
06fcb0c6	252	#else /* CONFIG_SMP */
54d5d424 AR	253
	254	#define move_irq(x)
	255	#define move_native_irq(x)
	256
06fcb0c6	257	#endif /* CONFIG_SMP */
54d5d424	258
1b61b910 ZY	259	#ifdef CONFIG_IRQBALANCE
	260	extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
	261	#else
	262	static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
	263	{
	264	}
	265	#endif
	266
71d218b7 IM	267	#ifdef CONFIG_AUTO_IRQ_AFFINITY
	268	extern int select_smp_affinity(unsigned int irq);
	269	#else
	270	static inline int select_smp_affinity(unsigned int irq)
	271	{
	272	return 1;
	273	}
	274	#endif
	275
1da177e4	276	extern int no_irq_affinity;
1da177e4	277
6a6de9ef TG	278	/* Handle irq action chains: */
	279	extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
	280	struct irqaction *action);
	281
	282	/*
	283	* Built-in IRQ handlers for various IRQ types,
	284	* callable via desc->chip->handle_irq()
	285	*/
	286	extern void fastcall
	287	handle_level_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	288	extern void fastcall
	289	handle_fastack_irq(unsigned int irq, struct irq_desc *desc,
	290	struct pt_regs *regs);
	291	extern void fastcall
	292	handle_edge_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	293	extern void fastcall
	294	handle_simple_irq(unsigned int irq, struct irq_desc *desc,
	295	struct pt_regs *regs);
	296	extern void fastcall
	297	handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
	298	struct pt_regs *regs);
	299	extern void fastcall
	300	handle_bad_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	301
	302	/*
	303	* Get a descriptive string for the highlevel handler, for
	304	* /proc/interrupts output:
	305	*/
	306	extern const char *
	307	handle_irq_name(void fastcall (handle)(unsigned int, struct irq_desc ,
	308	struct pt_regs *));
	309
2e60bbb6	310	/*
6a6de9ef TG	311	* Monolithic do_IRQ implementation.
6a6de9ef TG	312	* (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
2e60bbb6	313	*/
1da177e4	314	extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
2e60bbb6	315
dae86204 IM	316	/*
	317	* Architectures call this to let the generic IRQ layer
	318	* handle an interrupt. If the descriptor is attached to an
	319	* irqchip-style controller then we call the ->handle_irq() handler,
	320	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	321	*/
	322	static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
	323	{
	324	struct irq_desc *desc = irq_desc + irq;
	325
	326	if (likely(desc->handle_irq))
	327	desc->handle_irq(irq, desc, regs);
	328	else
	329	__do_IRQ(irq, regs);
	330	}
	331
6a6de9ef	332	/* Handling of unhandled and spurious interrupts: */
34ffdb72	333	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
2e60bbb6	334	int action_ret, struct pt_regs *regs);
1da177e4	335
a4633adc TG	336	/* Resending of interrupts :*/
	337	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	338
6a6de9ef	339	/* Initialize /proc/irq/ */
1da177e4	340	extern void init_irq_proc(void);
eee45269	341
6a6de9ef TG	342	/* Enable/disable irq debugging output: */
	343	extern int noirqdebug_setup(char *str);
	344
	345	/* Checks whether the interrupt can be requested by request_irq(): */
	346	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	347
	348	/* Dummy irq-chip implementation: */
	349	extern struct irq_chip no_irq_chip;
	350
	351	extern void
	352	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	353	void fastcall (*handle)(unsigned int,
	354	struct irq_desc *,
	355	struct pt_regs *));
	356	extern void
	357	__set_irq_handler(unsigned int irq,
	358	void fastcall (handle)(unsigned int, struct irq_desc ,
	359	struct pt_regs *),
	360	int is_chained);
1da177e4	361
6a6de9ef TG	362	/*
	363	* Set a highlevel flow handler for a given IRQ:
	364	*/
	365	static inline void
	366	set_irq_handler(unsigned int irq,
	367	void fastcall (handle)(unsigned int, struct irq_desc ,
	368	struct pt_regs *))
	369	{
	370	__set_irq_handler(irq, handle, 0);
	371	}
	372
	373	/*
	374	* Set a highlevel chained flow handler for a given IRQ.
	375	* (a chained handler is automatically enabled and set to
	376	* IRQ_NOREQUEST and IRQ_NOPROBE)
	377	*/
	378	static inline void
	379	set_irq_chained_handler(unsigned int irq,
	380	void fastcall (handle)(unsigned int, struct irq_desc ,
	381	struct pt_regs *))
	382	{
	383	__set_irq_handler(irq, handle, 1);
	384	}
	385
dd87eb3a TG	386	/* Set/get chip/data for an IRQ: */
	387
	388	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	389	extern int set_irq_data(unsigned int irq, void *data);
	390	extern int set_irq_chip_data(unsigned int irq, void *data);
	391	extern int set_irq_type(unsigned int irq, unsigned int type);
	392
	393	#define get_irq_chip(irq) (irq_desc[irq].chip)
	394	#define get_irq_chip_data(irq) (irq_desc[irq].chip_data)
	395	#define get_irq_data(irq) (irq_desc[irq].handler_data)
	396
6a6de9ef	397	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	398
06fcb0c6	399	#endif /* !CONFIG_S390 */
1da177e4	400
06fcb0c6	401	#endif /* _LINUX_IRQ_H */