[deliverable/linux.git] / include / linux / irqchip / arm-gic-v3.h

/*
 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
#define __LINUX_IRQCHIP_ARM_GIC_V3_H

#include <asm/sysreg.h>

/*
 * Distributor registers. We assume we're running non-secure, with ARE
 * being set. Secure-only and non-ARE registers are not described.
 */
#define GICD_CTLR			0x0000
#define GICD_TYPER			0x0004
#define GICD_IIDR			0x0008
#define GICD_STATUSR			0x0010
#define GICD_SETSPI_NSR			0x0040
#define GICD_CLRSPI_NSR			0x0048
#define GICD_SETSPI_SR			0x0050
#define GICD_CLRSPI_SR			0x0058
#define GICD_SEIR			0x0068
#define GICD_IGROUPR			0x0080
#define GICD_ISENABLER			0x0100
#define GICD_ICENABLER			0x0180
#define GICD_ISPENDR			0x0200
#define GICD_ICPENDR			0x0280
#define GICD_ISACTIVER			0x0300
#define GICD_ICACTIVER			0x0380
#define GICD_IPRIORITYR			0x0400
#define GICD_ICFGR			0x0C00
#define GICD_IGRPMODR			0x0D00
#define GICD_NSACR			0x0E00
#define GICD_IROUTER			0x6000
#define GICD_IDREGS			0xFFD0
#define GICD_PIDR2			0xFFE8

/*
 * Those registers are actually from GICv2, but the spec demands that they
 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
 */
#define GICD_ITARGETSR			0x0800
#define GICD_SGIR			0x0F00
#define GICD_CPENDSGIR			0x0F10
#define GICD_SPENDSGIR			0x0F20

#define GICD_CTLR_RWP			(1U << 31)
#define GICD_CTLR_DS			(1U << 6)
#define GICD_CTLR_ARE_NS		(1U << 4)
#define GICD_CTLR_ENABLE_G1A		(1U << 1)
#define GICD_CTLR_ENABLE_G1		(1U << 0)

/*
 * In systems with a single security state (what we emulate in KVM)
 * the meaning of the interrupt group enable bits is slightly different
 */
#define GICD_CTLR_ENABLE_SS_G1		(1U << 1)
#define GICD_CTLR_ENABLE_SS_G0		(1U << 0)

#define GICD_TYPER_LPIS			(1U << 17)
#define GICD_TYPER_MBIS			(1U << 16)

#define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)
#define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)
#define GICD_TYPER_LPIS			(1U << 17)

#define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
#define GICD_IROUTER_SPI_MODE_ANY	(1U << 31)

#define GIC_PIDR2_ARCH_MASK		0xf0
#define GIC_PIDR2_ARCH_GICv3		0x30
#define GIC_PIDR2_ARCH_GICv4		0x40

#define GIC_V3_DIST_SIZE		0x10000

/*
 * Re-Distributor registers, offsets from RD_base
 */
#define GICR_CTLR			GICD_CTLR
#define GICR_IIDR			0x0004
#define GICR_TYPER			0x0008
#define GICR_STATUSR			GICD_STATUSR
#define GICR_WAKER			0x0014
#define GICR_SETLPIR			0x0040
#define GICR_CLRLPIR			0x0048
#define GICR_SEIR			GICD_SEIR
#define GICR_PROPBASER			0x0070
#define GICR_PENDBASER			0x0078
#define GICR_INVLPIR			0x00A0
#define GICR_INVALLR			0x00B0
#define GICR_SYNCR			0x00C0
#define GICR_MOVLPIR			0x0100
#define GICR_MOVALLR			0x0110
#define GICR_ISACTIVER			GICD_ISACTIVER
#define GICR_ICACTIVER			GICD_ICACTIVER
#define GICR_IDREGS			GICD_IDREGS
#define GICR_PIDR2			GICD_PIDR2

#define GICR_CTLR_ENABLE_LPIS		(1UL << 0)

#define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)

#define GICR_WAKER_ProcessorSleep	(1U << 1)
#define GICR_WAKER_ChildrenAsleep	(1U << 2)

#define GICR_PROPBASER_NonShareable	(0U << 10)
#define GICR_PROPBASER_InnerShareable	(1U << 10)
#define GICR_PROPBASER_OuterShareable	(2U << 10)
#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
#define GICR_PROPBASER_nCnB		(0U << 7)
#define GICR_PROPBASER_nC		(1U << 7)
#define GICR_PROPBASER_RaWt		(2U << 7)
#define GICR_PROPBASER_RaWb		(3U << 7)
#define GICR_PROPBASER_WaWt		(4U << 7)
#define GICR_PROPBASER_WaWb		(5U << 7)
#define GICR_PROPBASER_RaWaWt		(6U << 7)
#define GICR_PROPBASER_RaWaWb		(7U << 7)
#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
#define GICR_PROPBASER_IDBITS_MASK	(0x1f)

#define GICR_PENDBASER_NonShareable	(0U << 10)
#define GICR_PENDBASER_InnerShareable	(1U << 10)
#define GICR_PENDBASER_OuterShareable	(2U << 10)
#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
#define GICR_PENDBASER_nCnB		(0U << 7)
#define GICR_PENDBASER_nC		(1U << 7)
#define GICR_PENDBASER_RaWt		(2U << 7)
#define GICR_PENDBASER_RaWb		(3U << 7)
#define GICR_PENDBASER_WaWt		(4U << 7)
#define GICR_PENDBASER_WaWb		(5U << 7)
#define GICR_PENDBASER_RaWaWt		(6U << 7)
#define GICR_PENDBASER_RaWaWb		(7U << 7)
#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)

/*
 * Re-Distributor registers, offsets from SGI_base
 */
#define GICR_IGROUPR0			GICD_IGROUPR
#define GICR_ISENABLER0			GICD_ISENABLER
#define GICR_ICENABLER0			GICD_ICENABLER
#define GICR_ISPENDR0			GICD_ISPENDR
#define GICR_ICPENDR0			GICD_ICPENDR
#define GICR_ISACTIVER0			GICD_ISACTIVER
#define GICR_ICACTIVER0			GICD_ICACTIVER
#define GICR_IPRIORITYR0		GICD_IPRIORITYR
#define GICR_ICFGR0			GICD_ICFGR
#define GICR_IGRPMODR0			GICD_IGRPMODR
#define GICR_NSACR			GICD_NSACR

#define GICR_TYPER_PLPIS		(1U << 0)
#define GICR_TYPER_VLPIS		(1U << 1)
#define GICR_TYPER_LAST			(1U << 4)

#define GIC_V3_REDIST_SIZE		0x20000

#define LPI_PROP_GROUP1			(1 << 1)
#define LPI_PROP_ENABLED		(1 << 0)

/*
 * ITS registers, offsets from ITS_base
 */
#define GITS_CTLR			0x0000
#define GITS_IIDR			0x0004
#define GITS_TYPER			0x0008
#define GITS_CBASER			0x0080
#define GITS_CWRITER			0x0088
#define GITS_CREADR			0x0090
#define GITS_BASER			0x0100
#define GITS_PIDR2			GICR_PIDR2

#define GITS_TRANSLATER			0x10040

#define GITS_CTLR_ENABLE		(1U << 0)
#define GITS_CTLR_QUIESCENT		(1U << 31)

#define GITS_TYPER_DEVBITS_SHIFT	13
#define GITS_TYPER_DEVBITS(r)		((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
#define GITS_TYPER_PTA			(1UL << 19)

#define GITS_CBASER_VALID		(1UL << 63)
#define GITS_CBASER_nCnB		(0UL << 59)
#define GITS_CBASER_nC			(1UL << 59)
#define GITS_CBASER_RaWt		(2UL << 59)
#define GITS_CBASER_RaWb		(3UL << 59)
#define GITS_CBASER_WaWt		(4UL << 59)
#define GITS_CBASER_WaWb		(5UL << 59)
#define GITS_CBASER_RaWaWt		(6UL << 59)
#define GITS_CBASER_RaWaWb		(7UL << 59)
#define GITS_CBASER_CACHEABILITY_MASK	(7UL << 59)
#define GITS_CBASER_NonShareable	(0UL << 10)
#define GITS_CBASER_InnerShareable	(1UL << 10)
#define GITS_CBASER_OuterShareable	(2UL << 10)
#define GITS_CBASER_SHAREABILITY_MASK	(3UL << 10)

#define GITS_BASER_NR_REGS		8

#define GITS_BASER_VALID		(1UL << 63)
#define GITS_BASER_nCnB			(0UL << 59)
#define GITS_BASER_nC			(1UL << 59)
#define GITS_BASER_RaWt			(2UL << 59)
#define GITS_BASER_RaWb			(3UL << 59)
#define GITS_BASER_WaWt			(4UL << 59)
#define GITS_BASER_WaWb			(5UL << 59)
#define GITS_BASER_RaWaWt		(6UL << 59)
#define GITS_BASER_RaWaWb		(7UL << 59)
#define GITS_BASER_CACHEABILITY_MASK	(7UL << 59)
#define GITS_BASER_TYPE_SHIFT		(56)
#define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
#define GITS_BASER_ENTRY_SIZE_SHIFT	(48)
#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
#define GITS_BASER_NonShareable		(0UL << 10)
#define GITS_BASER_InnerShareable	(1UL << 10)
#define GITS_BASER_OuterShareable	(2UL << 10)
#define GITS_BASER_SHAREABILITY_SHIFT	(10)
#define GITS_BASER_SHAREABILITY_MASK	(3UL << GITS_BASER_SHAREABILITY_SHIFT)
#define GITS_BASER_PAGE_SIZE_SHIFT	(8)
#define GITS_BASER_PAGE_SIZE_4K		(0UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_16K	(1UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_64K	(2UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_MASK	(3UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGES_MAX		256

#define GITS_BASER_TYPE_NONE		0
#define GITS_BASER_TYPE_DEVICE		1
#define GITS_BASER_TYPE_VCPU		2
#define GITS_BASER_TYPE_CPU		3
#define GITS_BASER_TYPE_COLLECTION	4
#define GITS_BASER_TYPE_RESERVED5	5
#define GITS_BASER_TYPE_RESERVED6	6
#define GITS_BASER_TYPE_RESERVED7	7

/*
 * ITS commands
 */
#define GITS_CMD_MAPD			0x08
#define GITS_CMD_MAPC			0x09
#define GITS_CMD_MAPVI			0x0a
#define GITS_CMD_MOVI			0x01
#define GITS_CMD_DISCARD		0x0f
#define GITS_CMD_INV			0x0c
#define GITS_CMD_MOVALL			0x0e
#define GITS_CMD_INVALL			0x0d
#define GITS_CMD_INT			0x03
#define GITS_CMD_CLEAR			0x04
#define GITS_CMD_SYNC			0x05

/*
 * CPU interface registers
 */
#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << 1)
#define ICC_CTLR_EL1_EOImode_drop	(1U << 1)
#define ICC_SRE_EL1_SRE			(1U << 0)

/*
 * Hypervisor interface registers (SRE only)
 */
#define ICH_LR_VIRTUAL_ID_MASK		((1UL << 32) - 1)

#define ICH_LR_EOI			(1UL << 41)
#define ICH_LR_GROUP			(1UL << 60)
#define ICH_LR_HW			(1UL << 61)
#define ICH_LR_STATE			(3UL << 62)
#define ICH_LR_PENDING_BIT		(1UL << 62)
#define ICH_LR_ACTIVE_BIT		(1UL << 63)
#define ICH_LR_PHYS_ID_SHIFT		32
#define ICH_LR_PHYS_ID_MASK		(0x3ffUL << ICH_LR_PHYS_ID_SHIFT)

#define ICH_MISR_EOI			(1 << 0)
#define ICH_MISR_U			(1 << 1)

#define ICH_HCR_EN			(1 << 0)
#define ICH_HCR_UIE			(1 << 1)

#define ICH_VMCR_CTLR_SHIFT		0
#define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
#define ICH_VMCR_BPR1_SHIFT		18
#define ICH_VMCR_BPR1_MASK		(7 << ICH_VMCR_BPR1_SHIFT)
#define ICH_VMCR_BPR0_SHIFT		21
#define ICH_VMCR_BPR0_MASK		(7 << ICH_VMCR_BPR0_SHIFT)
#define ICH_VMCR_PMR_SHIFT		24
#define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)

#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)

#define ICC_IAR1_EL1_SPURIOUS		0x3ff

#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

#define ICC_SRE_EL2_SRE			(1 << 0)
#define ICC_SRE_EL2_ENABLE		(1 << 3)

#define ICC_SGI1R_TARGET_LIST_SHIFT	0
#define ICC_SGI1R_TARGET_LIST_MASK	(0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
#define ICC_SGI1R_AFFINITY_1_SHIFT	16
#define ICC_SGI1R_AFFINITY_1_MASK	(0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
#define ICC_SGI1R_SGI_ID_SHIFT		24
#define ICC_SGI1R_SGI_ID_MASK		(0xff << ICC_SGI1R_SGI_ID_SHIFT)
#define ICC_SGI1R_AFFINITY_2_SHIFT	32
#define ICC_SGI1R_AFFINITY_2_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT	40
#define ICC_SGI1R_AFFINITY_3_SHIFT	48
#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)

/*
 * System register definitions
 */
#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)

#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)

#define ICH_LR0_EL2			__LR0_EL2(0)
#define ICH_LR1_EL2			__LR0_EL2(1)
#define ICH_LR2_EL2			__LR0_EL2(2)
#define ICH_LR3_EL2			__LR0_EL2(3)
#define ICH_LR4_EL2			__LR0_EL2(4)
#define ICH_LR5_EL2			__LR0_EL2(5)
#define ICH_LR6_EL2			__LR0_EL2(6)
#define ICH_LR7_EL2			__LR0_EL2(7)
#define ICH_LR8_EL2			__LR8_EL2(0)
#define ICH_LR9_EL2			__LR8_EL2(1)
#define ICH_LR10_EL2			__LR8_EL2(2)
#define ICH_LR11_EL2			__LR8_EL2(3)
#define ICH_LR12_EL2			__LR8_EL2(4)
#define ICH_LR13_EL2			__LR8_EL2(5)
#define ICH_LR14_EL2			__LR8_EL2(6)
#define ICH_LR15_EL2			__LR8_EL2(7)

#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)

#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)

#ifndef __ASSEMBLY__

#include <linux/stringify.h>
#include <asm/msi.h>

/*
 * We need a value to serve as a irq-type for LPIs. Choose one that will
 * hopefully pique the interest of the reviewer.
 */
#define GIC_IRQ_TYPE_LPI		0xa110c8ed

struct rdists {
	struct {
		void __iomem	*rd_base;
		struct page	*pend_page;
		phys_addr_t	phys_base;
	} __percpu		*rdist;
	struct page		*prop_page;
	int			id_bits;
	u64			flags;
};

static inline void gic_write_eoir(u64 irq)
{
	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
	isb();
}

static inline void gic_write_dir(u64 irq)
{
	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));
	isb();
}

static inline bool gic_enable_sre(void)
{
	u64 val;

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	if (val & ICC_SRE_EL1_SRE)
		return true;

	val |= ICC_SRE_EL1_SRE;
	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
	isb();
	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	return !!(val & ICC_SRE_EL1_SRE);
}

struct irq_domain;
int its_cpu_init(void);
int its_init(struct device_node *node, struct rdists *rdists,
	     struct irq_domain *domain);

#endif

#endif
Commit	Line	Data
021f6537 MZ	1	/*
	2	* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18	#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
	19	#define __LINUX_IRQCHIP_ARM_GIC_V3_H
	20
72c58395 CM	21	#include <asm/sysreg.h>
72c58395 CM	22
021f6537 MZ	23	/*
	24	* Distributor registers. We assume we're running non-secure, with ARE
	25	* being set. Secure-only and non-ARE registers are not described.
	26	*/
	27	#define GICD_CTLR 0x0000
	28	#define GICD_TYPER 0x0004
	29	#define GICD_IIDR 0x0008
	30	#define GICD_STATUSR 0x0010
	31	#define GICD_SETSPI_NSR 0x0040
	32	#define GICD_CLRSPI_NSR 0x0048
	33	#define GICD_SETSPI_SR 0x0050
	34	#define GICD_CLRSPI_SR 0x0058
	35	#define GICD_SEIR 0x0068
a0675c25	36	#define GICD_IGROUPR 0x0080
021f6537 MZ	37	#define GICD_ISENABLER 0x0100
	38	#define GICD_ICENABLER 0x0180
	39	#define GICD_ISPENDR 0x0200
	40	#define GICD_ICPENDR 0x0280
	41	#define GICD_ISACTIVER 0x0300
	42	#define GICD_ICACTIVER 0x0380
	43	#define GICD_IPRIORITYR 0x0400
	44	#define GICD_ICFGR 0x0C00
a0675c25 AP	45	#define GICD_IGRPMODR 0x0D00
a0675c25 AP	46	#define GICD_NSACR 0x0E00
021f6537	47	#define GICD_IROUTER 0x6000
a0675c25	48	#define GICD_IDREGS 0xFFD0
021f6537 MZ	49	#define GICD_PIDR2 0xFFE8
021f6537 MZ	50
a0675c25 AP	51	/*
	52	* Those registers are actually from GICv2, but the spec demands that they
	53	* are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
	54	*/
	55	#define GICD_ITARGETSR 0x0800
	56	#define GICD_SGIR 0x0F00
	57	#define GICD_CPENDSGIR 0x0F10
	58	#define GICD_SPENDSGIR 0x0F20
	59
021f6537	60	#define GICD_CTLR_RWP (1U << 31)
a0675c25	61	#define GICD_CTLR_DS (1U << 6)
021f6537 MZ	62	#define GICD_CTLR_ARE_NS (1U << 4)
	63	#define GICD_CTLR_ENABLE_G1A (1U << 1)
	64	#define GICD_CTLR_ENABLE_G1 (1U << 0)
	65
a0675c25 AP	66	/*
	67	* In systems with a single security state (what we emulate in KVM)
	68	* the meaning of the interrupt group enable bits is slightly different
	69	*/
	70	#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
	71	#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
	72
	73	#define GICD_TYPER_LPIS (1U << 17)
	74	#define GICD_TYPER_MBIS (1U << 16)
	75
f5c1434c MZ	76	#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
	77	#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
	78	#define GICD_TYPER_LPIS (1U << 17)
	79
021f6537 MZ	80	#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
	81	#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
	82
	83	#define GIC_PIDR2_ARCH_MASK 0xf0
	84	#define GIC_PIDR2_ARCH_GICv3 0x30
	85	#define GIC_PIDR2_ARCH_GICv4 0x40
	86
a0675c25 AP	87	#define GIC_V3_DIST_SIZE 0x10000
a0675c25 AP	88
021f6537 MZ	89	/*
	90	* Re-Distributor registers, offsets from RD_base
	91	*/
	92	#define GICR_CTLR GICD_CTLR
	93	#define GICR_IIDR 0x0004
	94	#define GICR_TYPER 0x0008
	95	#define GICR_STATUSR GICD_STATUSR
	96	#define GICR_WAKER 0x0014
	97	#define GICR_SETLPIR 0x0040
	98	#define GICR_CLRLPIR 0x0048
	99	#define GICR_SEIR GICD_SEIR
	100	#define GICR_PROPBASER 0x0070
	101	#define GICR_PENDBASER 0x0078
	102	#define GICR_INVLPIR 0x00A0
	103	#define GICR_INVALLR 0x00B0
	104	#define GICR_SYNCR 0x00C0
	105	#define GICR_MOVLPIR 0x0100
	106	#define GICR_MOVALLR 0x0110
0b6a3da9 MZ	107	#define GICR_ISACTIVER GICD_ISACTIVER
0b6a3da9 MZ	108	#define GICR_ICACTIVER GICD_ICACTIVER
a0675c25	109	#define GICR_IDREGS GICD_IDREGS
021f6537 MZ	110	#define GICR_PIDR2 GICD_PIDR2
021f6537 MZ	111
cc2d3216 MZ	112	#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
	113
	114	#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
	115
021f6537 MZ	116	#define GICR_WAKER_ProcessorSleep (1U << 1)
	117	#define GICR_WAKER_ChildrenAsleep (1U << 2)
	118
cc2d3216 MZ	119	#define GICR_PROPBASER_NonShareable (0U << 10)
	120	#define GICR_PROPBASER_InnerShareable (1U << 10)
	121	#define GICR_PROPBASER_OuterShareable (2U << 10)
	122	#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
	123	#define GICR_PROPBASER_nCnB (0U << 7)
	124	#define GICR_PROPBASER_nC (1U << 7)
	125	#define GICR_PROPBASER_RaWt (2U << 7)
	126	#define GICR_PROPBASER_RaWb (3U << 7)
	127	#define GICR_PROPBASER_WaWt (4U << 7)
	128	#define GICR_PROPBASER_WaWb (5U << 7)
	129	#define GICR_PROPBASER_RaWaWt (6U << 7)
	130	#define GICR_PROPBASER_RaWaWb (7U << 7)
241a386c	131	#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
cc2d3216 MZ	132	#define GICR_PROPBASER_IDBITS_MASK (0x1f)
cc2d3216 MZ	133
4ad3e363 MZ	134	#define GICR_PENDBASER_NonShareable (0U << 10)
	135	#define GICR_PENDBASER_InnerShareable (1U << 10)
	136	#define GICR_PENDBASER_OuterShareable (2U << 10)
	137	#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
	138	#define GICR_PENDBASER_nCnB (0U << 7)
	139	#define GICR_PENDBASER_nC (1U << 7)
	140	#define GICR_PENDBASER_RaWt (2U << 7)
	141	#define GICR_PENDBASER_RaWb (3U << 7)
	142	#define GICR_PENDBASER_WaWt (4U << 7)
	143	#define GICR_PENDBASER_WaWb (5U << 7)
	144	#define GICR_PENDBASER_RaWaWt (6U << 7)
	145	#define GICR_PENDBASER_RaWaWb (7U << 7)
241a386c	146	#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
4ad3e363	147
021f6537 MZ	148	/*
	149	* Re-Distributor registers, offsets from SGI_base
	150	*/
a0675c25	151	#define GICR_IGROUPR0 GICD_IGROUPR
021f6537 MZ	152	#define GICR_ISENABLER0 GICD_ISENABLER
	153	#define GICR_ICENABLER0 GICD_ICENABLER
	154	#define GICR_ISPENDR0 GICD_ISPENDR
	155	#define GICR_ICPENDR0 GICD_ICPENDR
	156	#define GICR_ISACTIVER0 GICD_ISACTIVER
	157	#define GICR_ICACTIVER0 GICD_ICACTIVER
	158	#define GICR_IPRIORITYR0 GICD_IPRIORITYR
	159	#define GICR_ICFGR0 GICD_ICFGR
a0675c25 AP	160	#define GICR_IGRPMODR0 GICD_IGRPMODR
a0675c25 AP	161	#define GICR_NSACR GICD_NSACR
021f6537	162
cc2d3216	163	#define GICR_TYPER_PLPIS (1U << 0)
021f6537 MZ	164	#define GICR_TYPER_VLPIS (1U << 1)
	165	#define GICR_TYPER_LAST (1U << 4)
	166
a0675c25 AP	167	#define GIC_V3_REDIST_SIZE 0x20000
a0675c25 AP	168
cc2d3216 MZ	169	#define LPI_PROP_GROUP1 (1 << 1)
	170	#define LPI_PROP_ENABLED (1 << 0)
	171
	172	/*
	173	* ITS registers, offsets from ITS_base
	174	*/
	175	#define GITS_CTLR 0x0000
	176	#define GITS_IIDR 0x0004
	177	#define GITS_TYPER 0x0008
	178	#define GITS_CBASER 0x0080
	179	#define GITS_CWRITER 0x0088
	180	#define GITS_CREADR 0x0090
	181	#define GITS_BASER 0x0100
	182	#define GITS_PIDR2 GICR_PIDR2
	183
	184	#define GITS_TRANSLATER 0x10040
	185
7cb99116 YW	186	#define GITS_CTLR_ENABLE (1U << 0)
	187	#define GITS_CTLR_QUIESCENT (1U << 31)
	188
f54b97ed MZ	189	#define GITS_TYPER_DEVBITS_SHIFT 13
f54b97ed MZ	190	#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
cc2d3216 MZ	191	#define GITS_TYPER_PTA (1UL << 19)
	192
	193	#define GITS_CBASER_VALID (1UL << 63)
	194	#define GITS_CBASER_nCnB (0UL << 59)
	195	#define GITS_CBASER_nC (1UL << 59)
	196	#define GITS_CBASER_RaWt (2UL << 59)
	197	#define GITS_CBASER_RaWb (3UL << 59)
	198	#define GITS_CBASER_WaWt (4UL << 59)
	199	#define GITS_CBASER_WaWb (5UL << 59)
	200	#define GITS_CBASER_RaWaWt (6UL << 59)
	201	#define GITS_CBASER_RaWaWb (7UL << 59)
241a386c	202	#define GITS_CBASER_CACHEABILITY_MASK (7UL << 59)
cc2d3216 MZ	203	#define GITS_CBASER_NonShareable (0UL << 10)
	204	#define GITS_CBASER_InnerShareable (1UL << 10)
	205	#define GITS_CBASER_OuterShareable (2UL << 10)
	206	#define GITS_CBASER_SHAREABILITY_MASK (3UL << 10)
	207
	208	#define GITS_BASER_NR_REGS 8
	209
	210	#define GITS_BASER_VALID (1UL << 63)
	211	#define GITS_BASER_nCnB (0UL << 59)
	212	#define GITS_BASER_nC (1UL << 59)
	213	#define GITS_BASER_RaWt (2UL << 59)
	214	#define GITS_BASER_RaWb (3UL << 59)
	215	#define GITS_BASER_WaWt (4UL << 59)
	216	#define GITS_BASER_WaWb (5UL << 59)
	217	#define GITS_BASER_RaWaWt (6UL << 59)
	218	#define GITS_BASER_RaWaWb (7UL << 59)
241a386c	219	#define GITS_BASER_CACHEABILITY_MASK (7UL << 59)
cc2d3216 MZ	220	#define GITS_BASER_TYPE_SHIFT (56)
	221	#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
	222	#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
	223	#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
	224	#define GITS_BASER_NonShareable (0UL << 10)
	225	#define GITS_BASER_InnerShareable (1UL << 10)
	226	#define GITS_BASER_OuterShareable (2UL << 10)
	227	#define GITS_BASER_SHAREABILITY_SHIFT (10)
	228	#define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT)
	229	#define GITS_BASER_PAGE_SIZE_SHIFT (8)
	230	#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
	231	#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
	232	#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
	233	#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
30f21363	234	#define GITS_BASER_PAGES_MAX 256
cc2d3216 MZ	235
	236	#define GITS_BASER_TYPE_NONE 0
	237	#define GITS_BASER_TYPE_DEVICE 1
	238	#define GITS_BASER_TYPE_VCPU 2
	239	#define GITS_BASER_TYPE_CPU 3
	240	#define GITS_BASER_TYPE_COLLECTION 4
	241	#define GITS_BASER_TYPE_RESERVED5 5
	242	#define GITS_BASER_TYPE_RESERVED6 6
	243	#define GITS_BASER_TYPE_RESERVED7 7
	244
	245	/*
	246	* ITS commands
	247	*/
	248	#define GITS_CMD_MAPD 0x08
	249	#define GITS_CMD_MAPC 0x09
	250	#define GITS_CMD_MAPVI 0x0a
	251	#define GITS_CMD_MOVI 0x01
	252	#define GITS_CMD_DISCARD 0x0f
	253	#define GITS_CMD_INV 0x0c
	254	#define GITS_CMD_MOVALL 0x0e
	255	#define GITS_CMD_INVALL 0x0d
	256	#define GITS_CMD_INT 0x03
	257	#define GITS_CMD_CLEAR 0x04
	258	#define GITS_CMD_SYNC 0x05
	259
021f6537 MZ	260	/*
	261	* CPU interface registers
	262	*/
	263	#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
	264	#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
	265	#define ICC_SRE_EL1_SRE (1U << 0)
	266
	267	/*
	268	* Hypervisor interface registers (SRE only)
	269	*/
	270	#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1)
	271
	272	#define ICH_LR_EOI (1UL << 41)
	273	#define ICH_LR_GROUP (1UL << 60)
fb182cf8	274	#define ICH_LR_HW (1UL << 61)
021f6537 MZ	275	#define ICH_LR_STATE (3UL << 62)
	276	#define ICH_LR_PENDING_BIT (1UL << 62)
	277	#define ICH_LR_ACTIVE_BIT (1UL << 63)
fb182cf8 MZ	278	#define ICH_LR_PHYS_ID_SHIFT 32
fb182cf8 MZ	279	#define ICH_LR_PHYS_ID_MASK (0x3ffUL << ICH_LR_PHYS_ID_SHIFT)
021f6537 MZ	280
	281	#define ICH_MISR_EOI (1 << 0)
	282	#define ICH_MISR_U (1 << 1)
	283
	284	#define ICH_HCR_EN (1 << 0)
	285	#define ICH_HCR_UIE (1 << 1)
	286
	287	#define ICH_VMCR_CTLR_SHIFT 0
	288	#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
	289	#define ICH_VMCR_BPR1_SHIFT 18
	290	#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
	291	#define ICH_VMCR_BPR0_SHIFT 21
	292	#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
	293	#define ICH_VMCR_PMR_SHIFT 24
	294	#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
	295
72c58395	296	#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
0b6a3da9	297	#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
72c58395 CM	298	#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
	299	#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
	300	#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
	301	#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
	302	#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
	303	#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
021f6537 MZ	304
	305	#define ICC_IAR1_EL1_SPURIOUS 0x3ff
	306
72c58395	307	#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
021f6537 MZ	308
	309	#define ICC_SRE_EL2_SRE (1 << 0)
	310	#define ICC_SRE_EL2_ENABLE (1 << 3)
	311
7e580278 AP	312	#define ICC_SGI1R_TARGET_LIST_SHIFT 0
	313	#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
	314	#define ICC_SGI1R_AFFINITY_1_SHIFT 16
	315	#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
	316	#define ICC_SGI1R_SGI_ID_SHIFT 24
	317	#define ICC_SGI1R_SGI_ID_MASK (0xff << ICC_SGI1R_SGI_ID_SHIFT)
	318	#define ICC_SGI1R_AFFINITY_2_SHIFT 32
	319	#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
	320	#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
	321	#define ICC_SGI1R_AFFINITY_3_SHIFT 48
	322	#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
	323
021f6537 MZ	324	/*
	325	* System register definitions
	326	*/
72c58395 CM	327	#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
	328	#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
	329	#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
	330	#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
	331	#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
	332	#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
	333	#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
021f6537	334
72c58395 CM	335	#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
72c58395 CM	336	#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
021f6537 MZ	337
	338	#define ICH_LR0_EL2 __LR0_EL2(0)
	339	#define ICH_LR1_EL2 __LR0_EL2(1)
	340	#define ICH_LR2_EL2 __LR0_EL2(2)
	341	#define ICH_LR3_EL2 __LR0_EL2(3)
	342	#define ICH_LR4_EL2 __LR0_EL2(4)
	343	#define ICH_LR5_EL2 __LR0_EL2(5)
	344	#define ICH_LR6_EL2 __LR0_EL2(6)
	345	#define ICH_LR7_EL2 __LR0_EL2(7)
	346	#define ICH_LR8_EL2 __LR8_EL2(0)
	347	#define ICH_LR9_EL2 __LR8_EL2(1)
	348	#define ICH_LR10_EL2 __LR8_EL2(2)
	349	#define ICH_LR11_EL2 __LR8_EL2(3)
	350	#define ICH_LR12_EL2 __LR8_EL2(4)
	351	#define ICH_LR13_EL2 __LR8_EL2(5)
	352	#define ICH_LR14_EL2 __LR8_EL2(6)
	353	#define ICH_LR15_EL2 __LR8_EL2(7)
	354
72c58395	355	#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
021f6537 MZ	356	#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
	357	#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
	358	#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
	359	#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
	360
72c58395	361	#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
021f6537 MZ	362	#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
	363	#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
	364	#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
	365	#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
	366
	367	#ifndef __ASSEMBLY__
	368
	369	#include <linux/stringify.h>
f130420e	370	#include <asm/msi.h>
021f6537	371
b48ac83d MZ	372	/*
	373	* We need a value to serve as a irq-type for LPIs. Choose one that will
	374	* hopefully pique the interest of the reviewer.
	375	*/
	376	#define GIC_IRQ_TYPE_LPI 0xa110c8ed
	377
f5c1434c MZ	378	struct rdists {
	379	struct {
	380	void __iomem *rd_base;
	381	struct page *pend_page;
	382	phys_addr_t phys_base;
	383	} __percpu *rdist;
	384	struct page *prop_page;
	385	int id_bits;
	386	u64 flags;
	387	};
	388
021f6537 MZ	389	static inline void gic_write_eoir(u64 irq)
021f6537 MZ	390	{
72c58395	391	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
021f6537 MZ	392	isb();
	393	}
	394
0b6a3da9 MZ	395	static inline void gic_write_dir(u64 irq)
	396	{
	397	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));
	398	isb();
	399	}
	400
7cabd008 MZ	401	static inline bool gic_enable_sre(void)
	402	{
	403	u64 val;
	404
	405	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	406	if (val & ICC_SRE_EL1_SRE)
	407	return true;
	408
	409	val \|= ICC_SRE_EL1_SRE;
	410	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
	411	isb();
	412	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	413
	414	return !!(val & ICC_SRE_EL1_SRE);
	415	}
	416
da33f31d MZ	417	struct irq_domain;
	418	int its_cpu_init(void);
	419	int its_init(struct device_node node, struct rdists rdists,
	420	struct irq_domain *domain);
	421
021f6537 MZ	422	#endif
	423
	424	#endif