[deliverable/linux.git] / include / linux / irqchip / mips-gic.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 */
#ifndef __LINUX_IRQCHIP_MIPS_GIC_H
#define __LINUX_IRQCHIP_MIPS_GIC_H

#include <linux/clocksource.h>

#define GIC_MAX_INTRS			256

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0
#define GIC_TRIG_DUAL_ENABLE		1
#define GIC_TRIG_DUAL_DISABLE		0

#define MSK(n) ((1 << (n)) - 1)

/* Accessors */
#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)

/* GIC Address Space */
#define SHARED_SECTION_OFS		0x0000
#define SHARED_SECTION_SIZE		0x8000
#define VPE_LOCAL_SECTION_OFS		0x8000
#define VPE_LOCAL_SECTION_SIZE		0x4000
#define VPE_OTHER_SECTION_OFS		0xc000
#define VPE_OTHER_SECTION_SIZE		0x4000
#define USM_VISIBLE_SECTION_OFS		0x10000
#define USM_VISIBLE_SECTION_SIZE	0x10000

/* Register Map for Shared Section */

#define GIC_SH_CONFIG_OFS		0x0000

/* Shared Global Counter */
#define GIC_SH_COUNTER_31_00_OFS	0x0010
#define GIC_SH_COUNTER_63_32_OFS	0x0014
#define GIC_SH_REVISIONID_OFS		0x0020

/* Convert an interrupt number to a byte offset/bit for multi-word registers */
#define GIC_INTR_OFS(intr)		(((intr) / 32) * 4)
#define GIC_INTR_BIT(intr)		((intr) % 32)

/* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS		0x0100

/* Triggering : Reset Value is always 0 */
#define GIC_SH_SET_TRIGGER_OFS		0x0180

/* Dual edge triggering : Reset Value is always 0 */
#define GIC_SH_SET_DUAL_OFS		0x0200

/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS		0x0280

/* Mask manipulation */
#define GIC_SH_RMASK_OFS		0x0300
#define GIC_SH_SMASK_OFS		0x0380

/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
#define GIC_SH_MASK_OFS			0x0400

/* Pending Global Interrupts (RO) */
#define GIC_SH_PEND_OFS			0x0480

/* Maps Interrupt X to a Pin */
#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
#define GIC_SH_MAP_TO_PIN(intr)		(4 * (intr))

/* Maps Interrupt X to a VPE */
#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	((32 * (intr)) + (((vpe) / 32) * 4))
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))

/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS			0x0000
#define GIC_VPE_PEND_OFS		0x0004
#define GIC_VPE_MASK_OFS		0x0008
#define GIC_VPE_RMASK_OFS		0x000c
#define GIC_VPE_SMASK_OFS		0x0010
#define GIC_VPE_WD_MAP_OFS		0x0040
#define GIC_VPE_COMPARE_MAP_OFS		0x0044
#define GIC_VPE_TIMER_MAP_OFS		0x0048
#define GIC_VPE_FDC_MAP_OFS		0x004c
#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
#define GIC_VPE_SWINT0_MAP_OFS		0x0054
#define GIC_VPE_SWINT1_MAP_OFS		0x0058
#define GIC_VPE_OTHER_ADDR_OFS		0x0080
#define GIC_VPE_WD_CONFIG0_OFS		0x0090
#define GIC_VPE_WD_COUNT0_OFS		0x0094
#define GIC_VPE_WD_INITIAL0_OFS		0x0098
#define GIC_VPE_COMPARE_LO_OFS		0x00a0
#define GIC_VPE_COMPARE_HI_OFS		0x00a4

#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS	0x0100
#define GIC_VPE_EIC_SS(intr)		(4 * (intr))

#define GIC_VPE_EIC_VEC_BASE_OFS	0x0800
#define GIC_VPE_EIC_VEC(intr)		(4 * (intr))

#define GIC_VPE_TENABLE_NMI_OFS		0x1000
#define GIC_VPE_TENABLE_YQ_OFS		0x1004
#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084

/* User Mode Visible Section Register Map */
#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004

/* Masks */
#define GIC_SH_CONFIG_COUNTSTOP_SHF	28
#define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)

#define GIC_SH_CONFIG_COUNTBITS_SHF	24
#define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)

#define GIC_SH_CONFIG_NUMINTRS_SHF	16
#define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)

#define GIC_SH_CONFIG_NUMVPES_SHF	0
#define GIC_SH_CONFIG_NUMVPES_MSK	(MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)

#define GIC_SH_WEDGE_SET(intr)		((intr) | (0x1 << 31))
#define GIC_SH_WEDGE_CLR(intr)		((intr) & ~(0x1 << 31))

#define GIC_MAP_TO_PIN_SHF		31
#define GIC_MAP_TO_PIN_MSK		(MSK(1) << GIC_MAP_TO_PIN_SHF)
#define GIC_MAP_TO_NMI_SHF		30
#define GIC_MAP_TO_NMI_MSK		(MSK(1) << GIC_MAP_TO_NMI_SHF)
#define GIC_MAP_TO_YQ_SHF		29
#define GIC_MAP_TO_YQ_MSK		(MSK(1) << GIC_MAP_TO_YQ_SHF)
#define GIC_MAP_SHF			0
#define GIC_MAP_MSK			(MSK(6) << GIC_MAP_SHF)

/* GIC_VPE_CTL Masks */
#define GIC_VPE_CTL_FDC_RTBL_SHF	4
#define GIC_VPE_CTL_FDC_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
#define GIC_VPE_CTL_SWINT_RTBL_SHF	3
#define GIC_VPE_CTL_SWINT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF	2
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
#define GIC_VPE_CTL_TIMER_RTBL_SHF	1
#define GIC_VPE_CTL_TIMER_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
#define GIC_VPE_CTL_EIC_MODE_SHF	0
#define GIC_VPE_CTL_EIC_MODE_MSK	(MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)

/* GIC_VPE_PEND Masks */
#define GIC_VPE_PEND_WD_SHF		0
#define GIC_VPE_PEND_WD_MSK		(MSK(1) << GIC_VPE_PEND_WD_SHF)
#define GIC_VPE_PEND_CMP_SHF		1
#define GIC_VPE_PEND_CMP_MSK		(MSK(1) << GIC_VPE_PEND_CMP_SHF)
#define GIC_VPE_PEND_TIMER_SHF		2
#define GIC_VPE_PEND_TIMER_MSK		(MSK(1) << GIC_VPE_PEND_TIMER_SHF)
#define GIC_VPE_PEND_PERFCOUNT_SHF	3
#define GIC_VPE_PEND_PERFCOUNT_MSK	(MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
#define GIC_VPE_PEND_SWINT0_SHF		4
#define GIC_VPE_PEND_SWINT0_MSK		(MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
#define GIC_VPE_PEND_SWINT1_SHF		5
#define GIC_VPE_PEND_SWINT1_MSK		(MSK(1) << GIC_VPE_PEND_SWINT1_SHF)

/* GIC_VPE_RMASK Masks */
#define GIC_VPE_RMASK_WD_SHF		0
#define GIC_VPE_RMASK_WD_MSK		(MSK(1) << GIC_VPE_RMASK_WD_SHF)
#define GIC_VPE_RMASK_CMP_SHF		1
#define GIC_VPE_RMASK_CMP_MSK		(MSK(1) << GIC_VPE_RMASK_CMP_SHF)
#define GIC_VPE_RMASK_TIMER_SHF		2
#define GIC_VPE_RMASK_TIMER_MSK		(MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
#define GIC_VPE_RMASK_PERFCNT_SHF	3
#define GIC_VPE_RMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
#define GIC_VPE_RMASK_SWINT0_SHF	4
#define GIC_VPE_RMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
#define GIC_VPE_RMASK_SWINT1_SHF	5
#define GIC_VPE_RMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)

/* GIC_VPE_SMASK Masks */
#define GIC_VPE_SMASK_WD_SHF		0
#define GIC_VPE_SMASK_WD_MSK		(MSK(1) << GIC_VPE_SMASK_WD_SHF)
#define GIC_VPE_SMASK_CMP_SHF		1
#define GIC_VPE_SMASK_CMP_MSK		(MSK(1) << GIC_VPE_SMASK_CMP_SHF)
#define GIC_VPE_SMASK_TIMER_SHF		2
#define GIC_VPE_SMASK_TIMER_MSK		(MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
#define GIC_VPE_SMASK_PERFCNT_SHF	3
#define GIC_VPE_SMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
#define GIC_VPE_SMASK_SWINT0_SHF	4
#define GIC_VPE_SMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
#define GIC_VPE_SMASK_SWINT1_SHF	5
#define GIC_VPE_SMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)

/* GIC nomenclature for Core Interrupt Pins. */
#define GIC_CPU_INT0		0 /* Core Interrupt 2 */
#define GIC_CPU_INT1		1 /* .		      */
#define GIC_CPU_INT2		2 /* .		      */
#define GIC_CPU_INT3		3 /* .		      */
#define GIC_CPU_INT4		4 /* .		      */
#define GIC_CPU_INT5		5 /* Core Interrupt 7 */

/* Add 2 to convert GIC CPU pin to core interrupt */
#define GIC_CPU_PIN_OFFSET	2

/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
#define GIC_CPU_TO_VEC_OFFSET	2

/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET	1

/* Local GIC interrupts. */
#define GIC_LOCAL_INT_WD	0 /* GIC watchdog */
#define GIC_LOCAL_INT_COMPARE	1 /* GIC count and compare timer */
#define GIC_LOCAL_INT_TIMER	2 /* CPU timer interrupt */
#define GIC_LOCAL_INT_PERFCTR	3 /* CPU performance counter */
#define GIC_LOCAL_INT_SWINT0	4 /* CPU software interrupt 0 */
#define GIC_LOCAL_INT_SWINT1	5 /* CPU software interrupt 1 */
#define GIC_LOCAL_INT_FDC	6 /* CPU fast debug channel */
#define GIC_NUM_LOCAL_INTRS	7

/* Convert between local/shared IRQ number and GIC HW IRQ number. */
#define GIC_LOCAL_HWIRQ_BASE	0
#define GIC_LOCAL_TO_HWIRQ(x)	(GIC_LOCAL_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_LOCAL(x)	((x) - GIC_LOCAL_HWIRQ_BASE)
#define GIC_SHARED_HWIRQ_BASE	GIC_NUM_LOCAL_INTRS
#define GIC_SHARED_TO_HWIRQ(x)	(GIC_SHARED_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_SHARED(x)	((x) - GIC_SHARED_HWIRQ_BASE)

extern unsigned int gic_present;
extern unsigned int gic_frequency;

extern void gic_init(unsigned long gic_base_addr,
	unsigned long gic_addrspace_size, unsigned int cpu_vec,
	unsigned int irqbase);
extern void gic_clocksource_init(unsigned int);
extern cycle_t gic_read_count(void);
extern unsigned int gic_get_count_width(void);
extern cycle_t gic_read_compare(void);
extern void gic_write_compare(cycle_t cnt);
extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
extern unsigned int gic_get_timer_pending(void);
extern int gic_get_c0_compare_int(void);
extern int gic_get_c0_perfcount_int(void);
#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
Commit	Line	Data
39b8d525 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000, 07 MIPS Technologies, Inc.
39b8d525	7	*/
824f3f7f AB	8	#ifndef __LINUX_IRQCHIP_MIPS_GIC_H
824f3f7f AB	9	#define __LINUX_IRQCHIP_MIPS_GIC_H
6d9727a7	10
824f3f7f	11	#include <linux/clocksource.h>
c9750481	12
fbd55241 AB	13	#define GIC_MAX_INTRS 256
fbd55241 AB	14
39b8d525 RB	15	/* Constants */
	16	#define GIC_POL_POS 1
	17	#define GIC_POL_NEG 0
	18	#define GIC_TRIG_EDGE 1
	19	#define GIC_TRIG_LEVEL 0
95150ae8 AB	20	#define GIC_TRIG_DUAL_ENABLE 1
95150ae8 AB	21	#define GIC_TRIG_DUAL_DISABLE 0
39b8d525	22
39b8d525	23	#define MSK(n) ((1 << (n)) - 1)
39b8d525 RB	24
39b8d525 RB	25	/* Accessors */
5f68fea0	26	#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
39b8d525 RB	27
	28	/* GIC Address Space */
	29	#define SHARED_SECTION_OFS 0x0000
	30	#define SHARED_SECTION_SIZE 0x8000
	31	#define VPE_LOCAL_SECTION_OFS 0x8000
	32	#define VPE_LOCAL_SECTION_SIZE 0x4000
	33	#define VPE_OTHER_SECTION_OFS 0xc000
	34	#define VPE_OTHER_SECTION_SIZE 0x4000
	35	#define USM_VISIBLE_SECTION_OFS 0x10000
	36	#define USM_VISIBLE_SECTION_SIZE 0x10000
	37
	38	/* Register Map for Shared Section */
39b8d525	39
70342287	40	#define GIC_SH_CONFIG_OFS 0x0000
39b8d525 RB	41
	42	/* Shared Global Counter */
	43	#define GIC_SH_COUNTER_31_00_OFS 0x0010
	44	#define GIC_SH_COUNTER_63_32_OFS 0x0014
7098f748	45	#define GIC_SH_REVISIONID_OFS 0x0020
39b8d525	46
824f3f7f AB	47	/* Convert an interrupt number to a byte offset/bit for multi-word registers */
	48	#define GIC_INTR_OFS(intr) (((intr) / 32) * 4)
	49	#define GIC_INTR_BIT(intr) ((intr) % 32)
	50
	51	/* Polarity : Reset Value is always 0 */
	52	#define GIC_SH_SET_POLARITY_OFS 0x0100
	53
	54	/* Triggering : Reset Value is always 0 */
	55	#define GIC_SH_SET_TRIGGER_OFS 0x0180
	56
	57	/* Dual edge triggering : Reset Value is always 0 */
	58	#define GIC_SH_SET_DUAL_OFS 0x0200
39b8d525 RB	59
	60	/* Set/Clear corresponding bit in Edge Detect Register */
	61	#define GIC_SH_WEDGE_OFS 0x0280
	62
824f3f7f AB	63	/* Mask manipulation */
	64	#define GIC_SH_RMASK_OFS 0x0300
	65	#define GIC_SH_SMASK_OFS 0x0380
39b8d525 RB	66
39b8d525 RB	67	/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
824f3f7f	68	#define GIC_SH_MASK_OFS 0x0400
39b8d525 RB	69
39b8d525 RB	70	/* Pending Global Interrupts (RO) */
824f3f7f	71	#define GIC_SH_PEND_OFS 0x0480
39b8d525 RB	72
39b8d525 RB	73	/* Maps Interrupt X to a Pin */
824f3f7f	74	#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
5f68fea0	75	#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
39b8d525	76
39b8d525	77	/* Maps Interrupt X to a VPE */
824f3f7f	78	#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
39b8d525	79	#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
5f68fea0	80	((32 * (intr)) + (((vpe) / 32) * 4))
39b8d525 RB	81	#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
39b8d525 RB	82
39b8d525 RB	83	/* Register Map for Local Section */
	84	#define GIC_VPE_CTL_OFS 0x0000
	85	#define GIC_VPE_PEND_OFS 0x0004
	86	#define GIC_VPE_MASK_OFS 0x0008
	87	#define GIC_VPE_RMASK_OFS 0x000c
	88	#define GIC_VPE_SMASK_OFS 0x0010
	89	#define GIC_VPE_WD_MAP_OFS 0x0040
	90	#define GIC_VPE_COMPARE_MAP_OFS 0x0044
	91	#define GIC_VPE_TIMER_MAP_OFS 0x0048
e9de688d	92	#define GIC_VPE_FDC_MAP_OFS 0x004c
39b8d525 RB	93	#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
	94	#define GIC_VPE_SWINT0_MAP_OFS 0x0054
	95	#define GIC_VPE_SWINT1_MAP_OFS 0x0058
	96	#define GIC_VPE_OTHER_ADDR_OFS 0x0080
	97	#define GIC_VPE_WD_CONFIG0_OFS 0x0090
	98	#define GIC_VPE_WD_COUNT0_OFS 0x0094
	99	#define GIC_VPE_WD_INITIAL0_OFS 0x0098
	100	#define GIC_VPE_COMPARE_LO_OFS 0x00a0
0ab2b7d0	101	#define GIC_VPE_COMPARE_HI_OFS 0x00a4
39b8d525	102
5f68fea0 AB	103	#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
5f68fea0 AB	104	#define GIC_VPE_EIC_SS(intr) (4 * (intr))
39b8d525	105
5f68fea0 AB	106	#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800
5f68fea0 AB	107	#define GIC_VPE_EIC_VEC(intr) (4 * (intr))
39b8d525 RB	108
	109	#define GIC_VPE_TENABLE_NMI_OFS 0x1000
	110	#define GIC_VPE_TENABLE_YQ_OFS 0x1004
	111	#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
	112	#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
	113
	114	/* User Mode Visible Section Register Map */
	115	#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
	116	#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
	117
39b8d525 RB	118	/* Masks */
	119	#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
	120	#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
	121
	122	#define GIC_SH_CONFIG_COUNTBITS_SHF 24
	123	#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
	124
	125	#define GIC_SH_CONFIG_NUMINTRS_SHF 16
	126	#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
	127
	128	#define GIC_SH_CONFIG_NUMVPES_SHF 0
	129	#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
	130
824f3f7f AB	131	#define GIC_SH_WEDGE_SET(intr) ((intr) \| (0x1 << 31))
824f3f7f AB	132	#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31))
39b8d525 RB	133
	134	#define GIC_MAP_TO_PIN_SHF 31
	135	#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
	136	#define GIC_MAP_TO_NMI_SHF 30
	137	#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
	138	#define GIC_MAP_TO_YQ_SHF 29
	139	#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
	140	#define GIC_MAP_SHF 0
	141	#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
	142
	143	/* GIC_VPE_CTL Masks */
e9de688d AB	144	#define GIC_VPE_CTL_FDC_RTBL_SHF 4
	145	#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
	146	#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
	147	#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
39b8d525 RB	148	#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
	149	#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
	150	#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
	151	#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
	152	#define GIC_VPE_CTL_EIC_MODE_SHF 0
	153	#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
	154
	155	/* GIC_VPE_PEND Masks */
	156	#define GIC_VPE_PEND_WD_SHF 0
	157	#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
	158	#define GIC_VPE_PEND_CMP_SHF 1
	159	#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
	160	#define GIC_VPE_PEND_TIMER_SHF 2
	161	#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
	162	#define GIC_VPE_PEND_PERFCOUNT_SHF 3
	163	#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
	164	#define GIC_VPE_PEND_SWINT0_SHF 4
	165	#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
	166	#define GIC_VPE_PEND_SWINT1_SHF 5
	167	#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
	168
	169	/* GIC_VPE_RMASK Masks */
	170	#define GIC_VPE_RMASK_WD_SHF 0
	171	#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
	172	#define GIC_VPE_RMASK_CMP_SHF 1
	173	#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
	174	#define GIC_VPE_RMASK_TIMER_SHF 2
	175	#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
	176	#define GIC_VPE_RMASK_PERFCNT_SHF 3
	177	#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
	178	#define GIC_VPE_RMASK_SWINT0_SHF 4
	179	#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
	180	#define GIC_VPE_RMASK_SWINT1_SHF 5
	181	#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
	182
	183	/* GIC_VPE_SMASK Masks */
	184	#define GIC_VPE_SMASK_WD_SHF 0
	185	#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
	186	#define GIC_VPE_SMASK_CMP_SHF 1
	187	#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
	188	#define GIC_VPE_SMASK_TIMER_SHF 2
	189	#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
	190	#define GIC_VPE_SMASK_PERFCNT_SHF 3
	191	#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
	192	#define GIC_VPE_SMASK_SWINT0_SHF 4
	193	#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
	194	#define GIC_VPE_SMASK_SWINT1_SHF 5
	195	#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
	196
0b271f56 SH	197	/* GIC nomenclature for Core Interrupt Pins. */
0b271f56 SH	198	#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
70342287 RB	199	#define GIC_CPU_INT1 1 /* . */
	200	#define GIC_CPU_INT2 2 /* . */
	201	#define GIC_CPU_INT3 3 /* . */
	202	#define GIC_CPU_INT4 4 /* . */
42a11179	203	#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
0b271f56	204
18743d27 AB	205	/* Add 2 to convert GIC CPU pin to core interrupt */
	206	#define GIC_CPU_PIN_OFFSET 2
	207
0b271f56	208	/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
824f3f7f	209	#define GIC_CPU_TO_VEC_OFFSET 2
0b271f56 SH	210
0b271f56 SH	211	/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
824f3f7f	212	#define GIC_PIN_TO_VEC_OFFSET 1
0b271f56	213
e9de688d AB	214	/* Local GIC interrupts. */
	215	#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
	216	#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
	217	#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
	218	#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
	219	#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
	220	#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
	221	#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
	222	#define GIC_NUM_LOCAL_INTRS 7
	223
	224	/* Convert between local/shared IRQ number and GIC HW IRQ number. */
	225	#define GIC_LOCAL_HWIRQ_BASE 0
	226	#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
	227	#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
	228	#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
	229	#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
	230	#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
	231
ff86714f	232	extern unsigned int gic_present;
28ea2151	233	extern unsigned int gic_frequency;
0b271f56	234
39b8d525	235	extern void gic_init(unsigned long gic_base_addr,
18743d27 AB	236	unsigned long gic_addrspace_size, unsigned int cpu_vec,
18743d27 AB	237	unsigned int irqbase);
0b271f56	238	extern void gic_clocksource_init(unsigned int);
dfa762e1	239	extern cycle_t gic_read_count(void);
387904ff	240	extern unsigned int gic_get_count_width(void);
0ab2b7d0 RG	241	extern cycle_t gic_read_compare(void);
0ab2b7d0 RG	242	extern void gic_write_compare(cycle_t cnt);
414408d0	243	extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
39b8d525	244	extern void gic_send_ipi(unsigned int intr);
0365070f TA	245	extern unsigned int plat_ipi_call_int_xlate(unsigned int);
0365070f TA	246	extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
f0b77f2c	247	extern unsigned int gic_get_timer_pending(void);
e9de688d AB	248	extern int gic_get_c0_compare_int(void);
e9de688d AB	249	extern int gic_get_c0_perfcount_int(void);
824f3f7f	250	#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */