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1b2b03f8 KK |
1 | /* |
2 | * | |
3 | * Author Karsten Keil <kkeil@novell.com> | |
4 | * | |
5 | * Basic declarations for the mISDN HW channels | |
6 | * | |
7 | * Copyright 2008 by Karsten Keil <kkeil@novell.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #ifndef MISDNHW_H | |
21 | #define MISDNHW_H | |
22 | #include <linux/mISDNif.h> | |
23 | #include <linux/timer.h> | |
24 | ||
25 | /* | |
26 | * HW DEBUG 0xHHHHGGGG | |
27 | * H - hardware driver specific bits | |
28 | * G - for all drivers | |
29 | */ | |
30 | ||
31 | #define DEBUG_HW 0x00000001 | |
32 | #define DEBUG_HW_OPEN 0x00000002 | |
33 | #define DEBUG_HW_DCHANNEL 0x00000100 | |
34 | #define DEBUG_HW_DFIFO 0x00000200 | |
35 | #define DEBUG_HW_BCHANNEL 0x00001000 | |
36 | #define DEBUG_HW_BFIFO 0x00002000 | |
37 | ||
38 | #define MAX_DFRAME_LEN_L1 300 | |
39 | #define MAX_MON_FRAME 32 | |
40 | #define MAX_LOG_SPACE 2048 | |
41 | #define MISDN_COPY_SIZE 32 | |
42 | ||
43 | /* channel->Flags bit field */ | |
44 | #define FLG_TX_BUSY 0 /* tx_buf in use */ | |
45 | #define FLG_TX_NEXT 1 /* next_skb in use */ | |
46 | #define FLG_L1_BUSY 2 /* L1 is permanent busy */ | |
47 | #define FLG_L2_ACTIVATED 3 /* activated from L2 */ | |
48 | #define FLG_OPEN 5 /* channel is in use */ | |
49 | #define FLG_ACTIVE 6 /* channel is activated */ | |
50 | #define FLG_BUSY_TIMER 7 | |
51 | /* channel type */ | |
52 | #define FLG_DCHANNEL 8 /* channel is D-channel */ | |
53 | #define FLG_BCHANNEL 9 /* channel is B-channel */ | |
54 | #define FLG_ECHANNEL 10 /* channel is E-channel */ | |
55 | #define FLG_TRANSPARENT 12 /* channel use transparent data */ | |
56 | #define FLG_HDLC 13 /* channel use hdlc data */ | |
57 | #define FLG_L2DATA 14 /* channel use L2 DATA primitivs */ | |
58 | #define FLG_ORIGIN 15 /* channel is on origin site */ | |
59 | /* channel specific stuff */ | |
8dd2f36f | 60 | #define FLG_FILLEMPTY 16 /* fill fifo on first frame (empty) */ |
1b2b03f8 | 61 | /* arcofi specific */ |
8dd2f36f AE |
62 | #define FLG_ARCOFI_TIMER 17 |
63 | #define FLG_ARCOFI_ERROR 18 | |
1b2b03f8 | 64 | /* isar specific */ |
8dd2f36f AE |
65 | #define FLG_INITIALIZED 17 |
66 | #define FLG_DLEETX 18 | |
67 | #define FLG_LASTDLE 19 | |
68 | #define FLG_FIRST 20 | |
69 | #define FLG_LASTDATA 21 | |
70 | #define FLG_NMD_DATA 22 | |
71 | #define FLG_FTI_RUN 23 | |
72 | #define FLG_LL_OK 24 | |
73 | #define FLG_LL_CONN 25 | |
74 | #define FLG_DTMFSEND 26 | |
6d1ee48f | 75 | #define FLG_TX_EMPTY 27 |
c27b46e7 KK |
76 | /* stop sending received data upstream */ |
77 | #define FLG_RX_OFF 28 | |
1b2b03f8 KK |
78 | /* workq events */ |
79 | #define FLG_RECVQUEUE 30 | |
80 | #define FLG_PHCHANGE 31 | |
81 | ||
82 | #define schedule_event(s, ev) do { \ | |
83 | test_and_set_bit(ev, &((s)->Flags)); \ | |
84 | schedule_work(&((s)->workq)); \ | |
85 | } while (0) | |
86 | ||
87 | struct dchannel { | |
88 | struct mISDNdevice dev; | |
89 | u_long Flags; | |
90 | struct work_struct workq; | |
91 | void (*phfunc) (struct dchannel *); | |
92 | u_int state; | |
93 | void *l1; | |
1b2b03f8 KK |
94 | void *hw; |
95 | int slot; /* multiport card channel slot */ | |
96 | struct timer_list timer; | |
97 | /* receive data */ | |
98 | struct sk_buff *rx_skb; | |
99 | int maxlen; | |
100 | /* send data */ | |
101 | struct sk_buff_head squeue; | |
102 | struct sk_buff_head rqueue; | |
103 | struct sk_buff *tx_skb; | |
104 | int tx_idx; | |
105 | int debug; | |
106 | /* statistics */ | |
107 | int err_crc; | |
108 | int err_tx; | |
109 | int err_rx; | |
110 | }; | |
111 | ||
112 | typedef int (dchannel_l1callback)(struct dchannel *, u_int); | |
113 | extern int create_l1(struct dchannel *, dchannel_l1callback *); | |
114 | ||
115 | /* private L1 commands */ | |
116 | #define INFO0 0x8002 | |
117 | #define INFO1 0x8102 | |
118 | #define INFO2 0x8202 | |
119 | #define INFO3_P8 0x8302 | |
120 | #define INFO3_P10 0x8402 | |
121 | #define INFO4_P8 0x8502 | |
122 | #define INFO4_P10 0x8602 | |
123 | #define LOSTFRAMING 0x8702 | |
124 | #define ANYSIGNAL 0x8802 | |
125 | #define HW_POWERDOWN 0x8902 | |
126 | #define HW_RESET_REQ 0x8a02 | |
127 | #define HW_POWERUP_REQ 0x8b02 | |
128 | #define HW_DEACT_REQ 0x8c02 | |
129 | #define HW_ACTIVATE_REQ 0x8e02 | |
130 | #define HW_D_NOBLOCKED 0x8f02 | |
131 | #define HW_RESET_IND 0x9002 | |
132 | #define HW_POWERUP_IND 0x9102 | |
133 | #define HW_DEACT_IND 0x9202 | |
134 | #define HW_ACTIVATE_IND 0x9302 | |
135 | #define HW_DEACT_CNF 0x9402 | |
136 | #define HW_TESTLOOP 0x9502 | |
137 | #define HW_TESTRX_RAW 0x9602 | |
138 | #define HW_TESTRX_HDLC 0x9702 | |
139 | #define HW_TESTRX_OFF 0x9802 | |
c626c127 KK |
140 | #define HW_TIMER3_IND 0x9902 |
141 | #define HW_TIMER3_VALUE 0x9a00 | |
142 | #define HW_TIMER3_VMASK 0x00FF | |
1b2b03f8 KK |
143 | |
144 | struct layer1; | |
145 | extern int l1_event(struct layer1 *, u_int); | |
146 | ||
6d1ee48f | 147 | #define MISDN_BCH_FILL_SIZE 4 |
1b2b03f8 KK |
148 | |
149 | struct bchannel { | |
150 | struct mISDNchannel ch; | |
151 | int nr; | |
152 | u_long Flags; | |
153 | struct work_struct workq; | |
154 | u_int state; | |
1b2b03f8 KK |
155 | void *hw; |
156 | int slot; /* multiport card channel slot */ | |
157 | struct timer_list timer; | |
158 | /* receive data */ | |
6d1ee48f | 159 | u8 fill[MISDN_BCH_FILL_SIZE]; |
1b2b03f8 | 160 | struct sk_buff *rx_skb; |
034005a0 KK |
161 | unsigned short maxlen; |
162 | unsigned short init_maxlen; /* initial value */ | |
163 | unsigned short next_maxlen; /* pending value */ | |
164 | unsigned short minlen; /* for transparent data */ | |
165 | unsigned short init_minlen; /* initial value */ | |
166 | unsigned short next_minlen; /* pending value */ | |
1b2b03f8 KK |
167 | /* send data */ |
168 | struct sk_buff *next_skb; | |
169 | struct sk_buff *tx_skb; | |
170 | struct sk_buff_head rqueue; | |
171 | int rcount; | |
172 | int tx_idx; | |
173 | int debug; | |
174 | /* statistics */ | |
175 | int err_crc; | |
176 | int err_tx; | |
177 | int err_rx; | |
c27b46e7 | 178 | int dropcnt; |
1b2b03f8 KK |
179 | }; |
180 | ||
181 | extern int mISDN_initdchannel(struct dchannel *, int, void *); | |
034005a0 KK |
182 | extern int mISDN_initbchannel(struct bchannel *, unsigned short, |
183 | unsigned short); | |
1b2b03f8 | 184 | extern int mISDN_freedchannel(struct dchannel *); |
fb286f04 | 185 | extern void mISDN_clear_bchannel(struct bchannel *); |
4b921eda | 186 | extern void mISDN_freebchannel(struct bchannel *); |
034005a0 | 187 | extern int mISDN_ctrl_bchannel(struct bchannel *, struct mISDN_ctrl_req *); |
1b2b03f8 KK |
188 | extern void queue_ch_frame(struct mISDNchannel *, u_int, |
189 | int, struct sk_buff *); | |
190 | extern int dchannel_senddata(struct dchannel *, struct sk_buff *); | |
191 | extern int bchannel_senddata(struct bchannel *, struct sk_buff *); | |
7206e659 | 192 | extern int bchannel_get_rxbuf(struct bchannel *, int); |
1b2b03f8 | 193 | extern void recv_Dchannel(struct dchannel *); |
1f28fa19 | 194 | extern void recv_Echannel(struct dchannel *, struct dchannel *); |
034005a0 | 195 | extern void recv_Bchannel(struct bchannel *, unsigned int, bool); |
1b2b03f8 KK |
196 | extern void recv_Dchannel_skb(struct dchannel *, struct sk_buff *); |
197 | extern void recv_Bchannel_skb(struct bchannel *, struct sk_buff *); | |
1b2b03f8 KK |
198 | extern int get_next_bframe(struct bchannel *); |
199 | extern int get_next_dframe(struct dchannel *); | |
200 | ||
201 | #endif |