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650c2a21 LW |
1 | /* |
2 | * Copyright (C) STMicroelectronics 2009 | |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
650c2a21 | 5 | * License Terms: GNU General Public License v2 |
3df57bcf | 6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
650c2a21 | 7 | * |
3df57bcf | 8 | * PRCMU f/w APIs |
650c2a21 | 9 | */ |
3df57bcf MN |
10 | #ifndef __MFD_DB8500_PRCMU_H |
11 | #define __MFD_DB8500_PRCMU_H | |
12 | ||
13 | #include <linux/interrupt.h> | |
b4a6dbd5 MN |
14 | #include <linux/bitops.h> |
15 | ||
16 | /* | |
17 | * Registers | |
18 | */ | |
b4a6dbd5 MN |
19 | #define DB8500_PRCM_LINE_VALUE 0x170 |
20 | #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3) | |
21 | ||
22 | #define DB8500_PRCM_DSI_SW_RESET 0x324 | |
23 | #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) | |
24 | #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) | |
25 | #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) | |
650c2a21 | 26 | |
3df57bcf | 27 | /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ |
650c2a21 | 28 | |
3df57bcf MN |
29 | /** |
30 | * enum state - ON/OFF state definition | |
31 | * @OFF: State is ON | |
32 | * @ON: State is OFF | |
33 | * | |
34 | */ | |
35 | enum state { | |
36 | OFF = 0x0, | |
37 | ON = 0x1, | |
650c2a21 | 38 | }; |
3df57bcf MN |
39 | |
40 | /** | |
41 | * enum ret_state - general purpose On/Off/Retention states | |
42 | * | |
43 | */ | |
44 | enum ret_state { | |
45 | OFFST = 0, | |
46 | ONST = 1, | |
47 | RETST = 2 | |
650c2a21 LW |
48 | }; |
49 | ||
3df57bcf MN |
50 | /** |
51 | * enum clk_arm - ARM Cortex A9 clock schemes | |
52 | * @A9_OFF: | |
53 | * @A9_BOOT: | |
54 | * @A9_OPPT1: | |
55 | * @A9_OPPT2: | |
56 | * @A9_EXTCLK: | |
57 | */ | |
58 | enum clk_arm { | |
59 | A9_OFF, | |
60 | A9_BOOT, | |
61 | A9_OPPT1, | |
62 | A9_OPPT2, | |
63 | A9_EXTCLK | |
64 | }; | |
650c2a21 | 65 | |
3df57bcf MN |
66 | /** |
67 | * enum clk_gen - GEN#0/GEN#1 clock schemes | |
68 | * @GEN_OFF: | |
69 | * @GEN_BOOT: | |
70 | * @GEN_OPPT1: | |
71 | */ | |
72 | enum clk_gen { | |
73 | GEN_OFF, | |
74 | GEN_BOOT, | |
75 | GEN_OPPT1, | |
76 | }; | |
77 | ||
78 | /* some information between arm and xp70 */ | |
79 | ||
80 | /** | |
81 | * enum romcode_write - Romcode message written by A9 AND read by XP70 | |
82 | * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 | |
83 | * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the | |
84 | * romcode. The xp70 will go into self-reset | |
85 | */ | |
86 | enum romcode_write { | |
87 | RDY_2_DS = 0x09, | |
88 | RDY_2_XP70_RST = 0x10 | |
89 | }; | |
90 | ||
91 | /** | |
92 | * enum romcode_read - Romcode message written by XP70 and read by A9 | |
93 | * @INIT: Init value when romcode field is not used | |
94 | * @FS_2_DS: Value set when power state is going from ApExecute to | |
95 | * ApDeepSleep | |
96 | * @END_DS: Value set when ApDeepSleep power state is reached coming from | |
97 | * ApExecute state | |
98 | * @DS_TO_FS: Value set when power state is going from ApDeepSleep to | |
99 | * ApExecute | |
100 | * @END_FS: Value set when ApExecute power state is reached coming from | |
101 | * ApDeepSleep state | |
102 | * @SWR: Value set when power state is going to ApReset | |
103 | * @END_SWR: Value set when the xp70 finished executing ApReset actions and | |
104 | * waits for romcode acknowledgment to go to self-reset | |
105 | */ | |
106 | enum romcode_read { | |
107 | INIT = 0x00, | |
108 | FS_2_DS = 0x0A, | |
109 | END_DS = 0x0B, | |
110 | DS_TO_FS = 0x0C, | |
111 | END_FS = 0x0D, | |
112 | SWR = 0x0E, | |
113 | END_SWR = 0x0F | |
114 | }; | |
115 | ||
116 | /** | |
117 | * enum ap_pwrst - current power states defined in PRCMU firmware | |
118 | * @NO_PWRST: Current power state init | |
119 | * @AP_BOOT: Current power state is apBoot | |
120 | * @AP_EXECUTE: Current power state is apExecute | |
121 | * @AP_DEEP_SLEEP: Current power state is apDeepSleep | |
122 | * @AP_SLEEP: Current power state is apSleep | |
123 | * @AP_IDLE: Current power state is apIdle | |
124 | * @AP_RESET: Current power state is apReset | |
125 | */ | |
126 | enum ap_pwrst { | |
127 | NO_PWRST = 0x00, | |
128 | AP_BOOT = 0x01, | |
129 | AP_EXECUTE = 0x02, | |
130 | AP_DEEP_SLEEP = 0x03, | |
131 | AP_SLEEP = 0x04, | |
132 | AP_IDLE = 0x05, | |
133 | AP_RESET = 0x06 | |
134 | }; | |
135 | ||
136 | /** | |
137 | * enum ap_pwrst_trans - Transition states defined in PRCMU firmware | |
138 | * @NO_TRANSITION: No power state transition | |
139 | * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep | |
140 | * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep | |
141 | * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute | |
142 | * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to | |
143 | * ApDeepSleep | |
144 | * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle | |
145 | */ | |
146 | enum ap_pwrst_trans { | |
73180f85 | 147 | PRCMU_AP_NO_CHANGE = 0x00, |
3df57bcf MN |
148 | APEXECUTE_TO_APSLEEP = 0x01, |
149 | APIDLE_TO_APSLEEP = 0x02, /* To be removed */ | |
150 | PRCMU_AP_SLEEP = 0x01, | |
151 | APBOOT_TO_APEXECUTE = 0x03, | |
152 | APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */ | |
153 | PRCMU_AP_DEEP_SLEEP = 0x04, | |
154 | APEXECUTE_TO_APIDLE = 0x05, /* To be removed */ | |
155 | PRCMU_AP_IDLE = 0x05, | |
156 | PRCMU_AP_DEEP_IDLE = 0x07, | |
157 | }; | |
158 | ||
3df57bcf MN |
159 | /** |
160 | * enum hw_acc_state - State definition for hardware accelerator | |
161 | * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged | |
162 | * @HW_OFF: The hardware accelerator must be switched off | |
163 | * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its | |
164 | * internal RAM in retention | |
165 | * @HW_ON: The hwa hardware accelerator hwa must be switched on | |
e3726fcf | 166 | * |
3df57bcf MN |
167 | * NOTE! Deprecated, to be removed when all users switched over to use the |
168 | * regulator API. | |
169 | */ | |
170 | enum hw_acc_state { | |
171 | HW_NO_CHANGE = 0x00, | |
172 | HW_OFF = 0x01, | |
173 | HW_OFF_RAMRET = 0x02, | |
174 | HW_ON = 0x04 | |
175 | }; | |
176 | ||
177 | /** | |
178 | * enum mbox_2_arm_stat - Status messages definition for mbox_arm | |
179 | * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been | |
180 | * completed | |
181 | * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been | |
182 | * completed | |
183 | * @SLEEPOK: The apExecute to apSleep state transition has been completed | |
184 | * @IDLEOK: The apExecute to apIdle state transition has been completed | |
185 | * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed | |
186 | * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going | |
187 | * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going | |
188 | * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on | |
189 | * going | |
190 | * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on | |
191 | * going | |
192 | * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has | |
193 | * been completed | |
194 | * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going | |
195 | * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going | |
196 | * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been | |
197 | * completed | |
198 | * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going | |
199 | * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going | |
200 | * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been | |
201 | * completed | |
202 | * @INIT_STATUS: Status init | |
203 | */ | |
204 | enum ap_pwrsttr_status { | |
205 | BOOT_TO_EXECUTEOK = 0xFF, | |
206 | DEEPSLEEPOK = 0xFE, | |
207 | SLEEPOK = 0xFD, | |
208 | IDLEOK = 0xFC, | |
209 | SOFTRESETOK = 0xFB, | |
210 | SOFTRESETGO = 0xFA, | |
211 | BOOT_TO_EXECUTE = 0xF9, | |
212 | EXECUTE_TO_DEEPSLEEP = 0xF8, | |
213 | DEEPSLEEP_TO_EXECUTE = 0xF7, | |
214 | DEEPSLEEP_TO_EXECUTEOK = 0xF6, | |
215 | EXECUTE_TO_SLEEP = 0xF5, | |
216 | SLEEP_TO_EXECUTE = 0xF4, | |
217 | SLEEP_TO_EXECUTEOK = 0xF3, | |
218 | EXECUTE_TO_IDLE = 0xF2, | |
219 | IDLE_TO_EXECUTE = 0xF1, | |
220 | IDLE_TO_EXECUTEOK = 0xF0, | |
221 | RDYTODS_RETURNTOEXE = 0xEF, | |
222 | NORDYTODS_RETURNTOEXE = 0xEE, | |
223 | EXETOSLEEP_RETURNTOEXE = 0xED, | |
224 | EXETOIDLE_RETURNTOEXE = 0xEC, | |
225 | INIT_STATUS = 0xEB, | |
226 | ||
227 | /*error messages */ | |
228 | INITERROR = 0x00, | |
229 | PLLARMLOCKP_ER = 0x01, | |
230 | PLLDDRLOCKP_ER = 0x02, | |
231 | PLLSOCLOCKP_ER = 0x03, | |
232 | PLLSOCK1LOCKP_ER = 0x04, | |
233 | ARMWFI_ER = 0x05, | |
234 | SYSCLKOK_ER = 0x06, | |
235 | I2C_NACK_DATA_ER = 0x07, | |
236 | BOOT_ER = 0x08, | |
237 | I2C_STATUS_ALWAYS_1 = 0x0A, | |
238 | I2C_NACK_REG_ADDR_ER = 0x0B, | |
239 | I2C_NACK_DATA0123_ER = 0x1B, | |
240 | I2C_NACK_ADDR_ER = 0x1F, | |
241 | CURAPPWRSTISNOT_BOOT = 0x20, | |
242 | CURAPPWRSTISNOT_EXECUTE = 0x21, | |
243 | CURAPPWRSTISNOT_SLEEPMODE = 0x22, | |
244 | CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, | |
245 | FIFO4500WUISNOT_WUPEVENT = 0x24, | |
246 | PLL32KLOCKP_ER = 0x29, | |
247 | DDRDEEPSLEEPOK_ER = 0x2A, | |
248 | ROMCODEREADY_ER = 0x50, | |
249 | WUPBEFOREDS = 0x51, | |
250 | DDRCONFIG_ER = 0x52, | |
251 | WUPBEFORESLEEP = 0x53, | |
252 | WUPBEFOREIDLE = 0x54 | |
253 | }; /* earlier called as mbox_2_arm_stat */ | |
254 | ||
255 | /** | |
256 | * enum dvfs_stat - DVFS status messages definition | |
257 | * @DVFS_GO: A state transition DVFS is on going | |
258 | * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP | |
259 | * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP | |
260 | * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK | |
261 | * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for | |
262 | * NOCHGCLK | |
263 | * @DVFS_INITSTATUS: Value init | |
264 | */ | |
265 | enum dvfs_stat { | |
266 | DVFS_GO = 0xFF, | |
267 | DVFS_ARM100OPPOK = 0xFE, | |
268 | DVFS_ARM50OPPOK = 0xFD, | |
269 | DVFS_ARMEXTCLKOK = 0xFC, | |
270 | DVFS_NOCHGTCLKOK = 0xFB, | |
271 | DVFS_INITSTATUS = 0x00 | |
272 | }; | |
273 | ||
274 | /** | |
275 | * enum sva_mmdsp_stat - SVA MMDSP status messages | |
276 | * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened | |
277 | * @SVA_MMDSP_INIT: Status init | |
278 | */ | |
279 | enum sva_mmdsp_stat { | |
280 | SVA_MMDSP_GO = 0xFF, | |
281 | SVA_MMDSP_INIT = 0x00 | |
282 | }; | |
283 | ||
284 | /** | |
285 | * enum sia_mmdsp_stat - SIA MMDSP status messages | |
286 | * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened | |
287 | * @SIA_MMDSP_INIT: Status init | |
288 | */ | |
289 | enum sia_mmdsp_stat { | |
290 | SIA_MMDSP_GO = 0xFF, | |
291 | SIA_MMDSP_INIT = 0x00 | |
292 | }; | |
293 | ||
294 | /** | |
295 | * enum mbox_to_arm_err - Error messages definition | |
296 | * @INIT_ERR: Init value | |
297 | * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time | |
298 | * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time | |
299 | * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time | |
300 | * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time | |
301 | * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time | |
302 | * @SYSCLKOK_ERR: The SYSCLK is not available in the given time | |
303 | * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time | |
304 | * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context | |
305 | * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered | |
306 | * through I2C has not been correctly executed in the given time | |
307 | * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered | |
308 | * through I2C has not been correctly executed in the given time | |
309 | * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through | |
310 | * I2C has not been correctly executed in the given time | |
311 | * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered | |
312 | * through I2C has not been correctly executed in the given time | |
313 | * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through | |
314 | * I2C has not been correctly executed in the given time | |
315 | * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered | |
316 | * through I2C has not been correctly executed in the given time | |
317 | * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through | |
318 | * I2C has not been correctly executed in the given time | |
319 | * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C | |
320 | * has not been correctly executed in the given time | |
321 | * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has | |
322 | * not been correctly executed in the given time | |
323 | * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has | |
324 | * not been correctly executed in the given time | |
325 | * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through | |
326 | * I2C has not been correctly executed in the given time | |
327 | * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through | |
328 | * I2C has not been correctly executed in the given time | |
329 | * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered | |
330 | * through I2C has not been correctly executed in the given time | |
331 | * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition | |
332 | * ApBoot to ApExecute but the power current state is not Apboot | |
333 | * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state | |
334 | * transition from ApExecute to others power state but the | |
335 | * power current state is not ApExecute | |
336 | * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted | |
337 | * but the power current state is not ApDeepSleep/ApSleep/ApIdle | |
338 | * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted | |
339 | * but the power current state is not correct | |
340 | * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not | |
341 | * been correctly executed in the given time | |
342 | * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not | |
343 | * been correctly executed in the given time | |
344 | * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not | |
345 | * been correctly executed in the given time | |
346 | * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not | |
347 | * been correctly executed in the given time | |
348 | * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not | |
349 | * been correctly executed in the given time | |
350 | */ | |
351 | enum mbox_to_arm_err { | |
352 | INIT_ERR = 0x00, | |
353 | PLLARMLOCKP_ERR = 0x01, | |
354 | PLLDDRLOCKP_ERR = 0x02, | |
355 | PLLSOC0LOCKP_ERR = 0x03, | |
356 | PLLSOC1LOCKP_ERR = 0x04, | |
357 | ARMWFI_ERR = 0x05, | |
358 | SYSCLKOK_ERR = 0x06, | |
359 | BOOT_ERR = 0x07, | |
360 | ROMCODESAVECONTEXT = 0x08, | |
361 | VARMHIGHSPEEDVALTO_ERR = 0x10, | |
362 | VARMHIGHSPEEDACCESS_ERR = 0x11, | |
363 | VARMLOWSPEEDVALTO_ERR = 0x12, | |
364 | VARMLOWSPEEDACCESS_ERR = 0x13, | |
365 | VARMRETENTIONVALTO_ERR = 0x14, | |
366 | VARMRETENTIONACCESS_ERR = 0x15, | |
367 | VAPEHIGHSPEEDVALTO_ERR = 0x16, | |
368 | VSAFEHPVALTO_ERR = 0x17, | |
369 | VMODSEL1VALTO_ERR = 0x18, | |
370 | VMODSEL2VALTO_ERR = 0x19, | |
371 | VARMOFFACCESS_ERR = 0x1A, | |
372 | VAPEOFFACCESS_ERR = 0x1B, | |
373 | VARMRETACCES_ERR = 0x1C, | |
374 | CURAPPWRSTISNOTBOOT = 0x20, | |
375 | CURAPPWRSTISNOTEXECUTE = 0x21, | |
376 | CURAPPWRSTISNOTSLEEPMODE = 0x22, | |
377 | CURAPPWRSTISNOTCORRECTDBG = 0x23, | |
378 | ARMREGU1VALTO_ERR = 0x24, | |
379 | ARMREGU2VALTO_ERR = 0x25, | |
380 | VAPEREGUVALTO_ERR = 0x26, | |
381 | VSMPS3REGUVALTO_ERR = 0x27, | |
382 | VMODREGUVALTO_ERR = 0x28 | |
383 | }; | |
384 | ||
385 | enum hw_acc { | |
386 | SVAMMDSP = 0, | |
387 | SVAPIPE = 1, | |
388 | SIAMMDSP = 2, | |
389 | SIAPIPE = 3, | |
390 | SGA = 4, | |
391 | B2R2MCDE = 5, | |
392 | ESRAM12 = 6, | |
393 | ESRAM34 = 7, | |
394 | }; | |
395 | ||
396 | enum cs_pwrmgt { | |
397 | PWRDNCS0 = 0, | |
398 | WKUPCS0 = 1, | |
399 | PWRDNCS1 = 2, | |
400 | WKUPCS1 = 3 | |
401 | }; | |
402 | ||
403 | /* Defs related to autonomous power management */ | |
404 | ||
405 | /** | |
406 | * enum sia_sva_pwr_policy - Power policy | |
407 | * @NO_CHGT: No change | |
408 | * @DSPOFF_HWPOFF: | |
409 | * @DSPOFFRAMRET_HWPOFF: | |
410 | * @DSPCLKOFF_HWPOFF: | |
411 | * @DSPCLKOFF_HWPCLKOFF: | |
e0befb23 | 412 | * |
3df57bcf MN |
413 | */ |
414 | enum sia_sva_pwr_policy { | |
415 | NO_CHGT = 0x0, | |
416 | DSPOFF_HWPOFF = 0x1, | |
417 | DSPOFFRAMRET_HWPOFF = 0x2, | |
418 | DSPCLKOFF_HWPOFF = 0x3, | |
419 | DSPCLKOFF_HWPCLKOFF = 0x4, | |
420 | }; | |
421 | ||
422 | /** | |
423 | * enum auto_enable - Auto Power enable | |
424 | * @AUTO_OFF: | |
425 | * @AUTO_ON: | |
426 | * | |
427 | */ | |
428 | enum auto_enable { | |
429 | AUTO_OFF = 0x0, | |
430 | AUTO_ON = 0x1, | |
431 | }; | |
432 | ||
433 | /* End of file previously known as prcmu-fw-defs_v1.h */ | |
434 | ||
4d64d2e3 MN |
435 | /** |
436 | * enum prcmu_power_status - results from set_power_state | |
437 | * @PRCMU_SLEEP_OK: Sleep went ok | |
438 | * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok | |
439 | * @PRCMU_IDLE_OK: Idle went ok | |
440 | * @PRCMU_DEEPIDLE_OK: DeepIdle went ok | |
441 | * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected | |
442 | * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected | |
443 | * | |
444 | */ | |
445 | enum prcmu_power_status { | |
446 | PRCMU_SLEEP_OK = 0xf3, | |
447 | PRCMU_DEEP_SLEEP_OK = 0xf6, | |
448 | PRCMU_IDLE_OK = 0xf0, | |
449 | PRCMU_DEEPIDLE_OK = 0xe3, | |
450 | PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91, | |
451 | PRCMU_ARMPENDINGIT_ER = 0x93, | |
452 | }; | |
453 | ||
3df57bcf MN |
454 | /* |
455 | * Definitions for autonomous power management configuration. | |
456 | */ | |
457 | ||
458 | #define PRCMU_AUTO_PM_OFF 0 | |
459 | #define PRCMU_AUTO_PM_ON 1 | |
460 | ||
461 | #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0) | |
462 | #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1) | |
463 | ||
464 | enum prcmu_auto_pm_policy { | |
465 | PRCMU_AUTO_PM_POLICY_NO_CHANGE, | |
466 | PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF, | |
467 | PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF, | |
468 | PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF, | |
469 | PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF, | |
470 | }; | |
471 | ||
472 | /** | |
473 | * struct prcmu_auto_pm_config - Autonomous power management configuration. | |
474 | * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON}) | |
475 | * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask) | |
476 | * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy) | |
477 | * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON}) | |
478 | * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask) | |
479 | * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy) | |
480 | */ | |
481 | struct prcmu_auto_pm_config { | |
482 | u8 sia_auto_pm_enable; | |
483 | u8 sia_power_on; | |
484 | u8 sia_policy; | |
485 | u8 sva_auto_pm_enable; | |
486 | u8 sva_power_on; | |
487 | u8 sva_policy; | |
488 | }; | |
489 | ||
3df57bcf MN |
490 | #ifdef CONFIG_MFD_DB8500_PRCMU |
491 | ||
9a47a8dc | 492 | void db8500_prcmu_early_init(u32 phy_base, u32 size); |
3df57bcf MN |
493 | int prcmu_set_rc_a2p(enum romcode_write); |
494 | enum romcode_read prcmu_get_rc_p2a(void); | |
495 | enum ap_pwrst prcmu_get_xp70_current_state(void); | |
3df57bcf | 496 | bool prcmu_has_arm_maxopp(void); |
b58d12fe | 497 | struct prcmu_fw_version *prcmu_get_fw_version(void); |
3df57bcf | 498 | int prcmu_release_usb_wakeup_state(void); |
3df57bcf MN |
499 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, |
500 | struct prcmu_auto_pm_config *idle); | |
501 | bool prcmu_is_auto_pm_enabled(void); | |
502 | ||
503 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div); | |
3df57bcf | 504 | int prcmu_set_clock_divider(u8 clock, u8 divider); |
0508901c MN |
505 | int db8500_prcmu_config_hotdog(u8 threshold); |
506 | int db8500_prcmu_config_hotmon(u8 low, u8 high); | |
507 | int db8500_prcmu_start_temp_sense(u16 cycles32k); | |
508 | int db8500_prcmu_stop_temp_sense(void); | |
e3726fcf LW |
509 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); |
510 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | |
511 | ||
5261e101 | 512 | int prcmu_ac_wake_req(void); |
3df57bcf | 513 | void prcmu_ac_sleep_req(void); |
0508901c | 514 | void db8500_prcmu_modem_reset(void); |
3df57bcf | 515 | |
0508901c MN |
516 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off); |
517 | int db8500_prcmu_enable_a9wdog(u8 id); | |
518 | int db8500_prcmu_disable_a9wdog(u8 id); | |
519 | int db8500_prcmu_kick_a9wdog(u8 id); | |
520 | int db8500_prcmu_load_a9wdog(u8 id, u32 val); | |
73180f85 MN |
521 | |
522 | void db8500_prcmu_system_reset(u16 reset_code); | |
523 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); | |
4d64d2e3 | 524 | u8 db8500_prcmu_get_power_state_result(void); |
73180f85 MN |
525 | void db8500_prcmu_enable_wakeups(u32 wakeups); |
526 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); | |
527 | int db8500_prcmu_request_clock(u8 clock, bool enable); | |
528 | int db8500_prcmu_set_display_clocks(void); | |
529 | int db8500_prcmu_disable_dsipll(void); | |
530 | int db8500_prcmu_enable_dsipll(void); | |
531 | void db8500_prcmu_config_abb_event_readout(u32 abb_events); | |
532 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf); | |
533 | int db8500_prcmu_config_esram0_deep_sleep(u8 state); | |
534 | u16 db8500_prcmu_get_reset_code(void); | |
535 | bool db8500_prcmu_is_ac_wake_requested(void); | |
536 | int db8500_prcmu_set_arm_opp(u8 opp); | |
537 | int db8500_prcmu_get_arm_opp(void); | |
0508901c MN |
538 | int db8500_prcmu_set_ape_opp(u8 opp); |
539 | int db8500_prcmu_get_ape_opp(void); | |
686f871b | 540 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable); |
0508901c MN |
541 | int db8500_prcmu_set_ddr_opp(u8 opp); |
542 | int db8500_prcmu_get_ddr_opp(void); | |
73180f85 | 543 | |
b4a6dbd5 MN |
544 | u32 db8500_prcmu_read(unsigned int reg); |
545 | void db8500_prcmu_write(unsigned int reg, u32 value); | |
546 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); | |
547 | ||
3df57bcf MN |
548 | #else /* !CONFIG_MFD_DB8500_PRCMU */ |
549 | ||
9a47a8dc | 550 | static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {} |
73180f85 | 551 | |
3df57bcf MN |
552 | static inline int prcmu_set_rc_a2p(enum romcode_write code) |
553 | { | |
554 | return 0; | |
555 | } | |
556 | ||
557 | static inline enum romcode_read prcmu_get_rc_p2a(void) | |
558 | { | |
559 | return INIT; | |
560 | } | |
561 | ||
562 | static inline enum ap_pwrst prcmu_get_xp70_current_state(void) | |
563 | { | |
564 | return AP_EXECUTE; | |
565 | } | |
566 | ||
73180f85 | 567 | static inline bool prcmu_has_arm_maxopp(void) |
3df57bcf MN |
568 | { |
569 | return false; | |
570 | } | |
571 | ||
b58d12fe MN |
572 | static inline struct prcmu_fw_version *prcmu_get_fw_version(void) |
573 | { | |
574 | return NULL; | |
575 | } | |
576 | ||
0508901c | 577 | static inline int db8500_prcmu_set_ape_opp(u8 opp) |
3df57bcf MN |
578 | { |
579 | return 0; | |
580 | } | |
581 | ||
0508901c | 582 | static inline int db8500_prcmu_get_ape_opp(void) |
3df57bcf MN |
583 | { |
584 | return APE_100_OPP; | |
585 | } | |
586 | ||
686f871b | 587 | static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
3df57bcf MN |
588 | { |
589 | return 0; | |
590 | } | |
591 | ||
592 | static inline int prcmu_release_usb_wakeup_state(void) | |
593 | { | |
594 | return 0; | |
595 | } | |
596 | ||
0508901c | 597 | static inline int db8500_prcmu_set_ddr_opp(u8 opp) |
3df57bcf MN |
598 | { |
599 | return 0; | |
600 | } | |
601 | ||
0508901c | 602 | static inline int db8500_prcmu_get_ddr_opp(void) |
3df57bcf MN |
603 | { |
604 | return DDR_100_OPP; | |
605 | } | |
606 | ||
3df57bcf MN |
607 | static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, |
608 | struct prcmu_auto_pm_config *idle) | |
609 | { | |
610 | } | |
611 | ||
612 | static inline bool prcmu_is_auto_pm_enabled(void) | |
613 | { | |
614 | return false; | |
615 | } | |
616 | ||
617 | static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
618 | { | |
619 | return 0; | |
620 | } | |
621 | ||
3df57bcf MN |
622 | static inline int prcmu_set_clock_divider(u8 clock, u8 divider) |
623 | { | |
624 | return 0; | |
625 | } | |
626 | ||
0508901c | 627 | static inline int db8500_prcmu_config_hotdog(u8 threshold) |
3df57bcf MN |
628 | { |
629 | return 0; | |
630 | } | |
631 | ||
0508901c | 632 | static inline int db8500_prcmu_config_hotmon(u8 low, u8 high) |
3df57bcf MN |
633 | { |
634 | return 0; | |
635 | } | |
636 | ||
0508901c | 637 | static inline int db8500_prcmu_start_temp_sense(u16 cycles32k) |
3df57bcf MN |
638 | { |
639 | return 0; | |
640 | } | |
641 | ||
0508901c | 642 | static inline int db8500_prcmu_stop_temp_sense(void) |
3df57bcf MN |
643 | { |
644 | return 0; | |
645 | } | |
646 | ||
647 | static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
648 | { | |
649 | return -ENOSYS; | |
650 | } | |
651 | ||
652 | static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
653 | { | |
654 | return -ENOSYS; | |
655 | } | |
656 | ||
5261e101 AM |
657 | static inline int prcmu_ac_wake_req(void) |
658 | { | |
659 | return 0; | |
660 | } | |
3df57bcf MN |
661 | |
662 | static inline void prcmu_ac_sleep_req(void) {} | |
663 | ||
0508901c MN |
664 | static inline void db8500_prcmu_modem_reset(void) {} |
665 | ||
666 | static inline void db8500_prcmu_system_reset(u16 reset_code) {} | |
3df57bcf | 667 | |
73180f85 MN |
668 | static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, |
669 | bool keep_ap_pll) | |
3df57bcf MN |
670 | { |
671 | return 0; | |
672 | } | |
673 | ||
4d64d2e3 MN |
674 | static inline u8 db8500_prcmu_get_power_state_result(void) |
675 | { | |
676 | return 0; | |
677 | } | |
678 | ||
73180f85 MN |
679 | static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {} |
680 | ||
681 | static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) | |
3df57bcf MN |
682 | { |
683 | return 0; | |
684 | } | |
3df57bcf | 685 | |
73180f85 | 686 | static inline int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf MN |
687 | { |
688 | return 0; | |
689 | } | |
690 | ||
73180f85 | 691 | static inline int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
692 | { |
693 | return 0; | |
694 | } | |
695 | ||
73180f85 MN |
696 | static inline int db8500_prcmu_disable_dsipll(void) |
697 | { | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static inline int db8500_prcmu_enable_dsipll(void) | |
702 | { | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state) | |
707 | { | |
708 | return 0; | |
709 | } | |
710 | ||
711 | static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {} | |
3df57bcf | 712 | |
73180f85 MN |
713 | static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {} |
714 | ||
715 | static inline u16 db8500_prcmu_get_reset_code(void) | |
3df57bcf MN |
716 | { |
717 | return 0; | |
718 | } | |
719 | ||
0508901c | 720 | static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
3df57bcf MN |
721 | { |
722 | return 0; | |
723 | } | |
724 | ||
0508901c | 725 | static inline int db8500_prcmu_enable_a9wdog(u8 id) |
3df57bcf MN |
726 | { |
727 | return 0; | |
728 | } | |
729 | ||
0508901c | 730 | static inline int db8500_prcmu_disable_a9wdog(u8 id) |
3df57bcf | 731 | { |
73180f85 | 732 | return 0; |
3df57bcf MN |
733 | } |
734 | ||
0508901c | 735 | static inline int db8500_prcmu_kick_a9wdog(u8 id) |
3df57bcf MN |
736 | { |
737 | return 0; | |
738 | } | |
73180f85 | 739 | |
0508901c | 740 | static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val) |
3df57bcf MN |
741 | { |
742 | return 0; | |
743 | } | |
744 | ||
73180f85 MN |
745 | static inline bool db8500_prcmu_is_ac_wake_requested(void) |
746 | { | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static inline int db8500_prcmu_set_arm_opp(u8 opp) | |
751 | { | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static inline int db8500_prcmu_get_arm_opp(void) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | ||
b4a6dbd5 MN |
760 | static inline u32 db8500_prcmu_read(unsigned int reg) |
761 | { | |
762 | return 0; | |
763 | } | |
764 | ||
765 | static inline void db8500_prcmu_write(unsigned int reg, u32 value) {} | |
766 | ||
767 | static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask, | |
768 | u32 value) {} | |
769 | ||
73180f85 | 770 | #endif /* !CONFIG_MFD_DB8500_PRCMU */ |
3df57bcf MN |
771 | |
772 | #endif /* __MFD_DB8500_PRCMU_H */ |