Commit | Line | Data |
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fea799e3 MN |
1 | /* |
2 | * Copyright (C) ST Ericsson SA 2011 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * | |
6 | * STE Ux500 PRCMU API | |
7 | */ | |
8 | #ifndef __MACH_PRCMU_H | |
9 | #define __MACH_PRCMU_H | |
10 | ||
11 | #include <linux/interrupt.h> | |
12 | #include <linux/notifier.h> | |
0508901c | 13 | #include <linux/err.h> |
fea799e3 | 14 | |
67f13daa LJ |
15 | #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */ |
16 | ||
05ec260e LW |
17 | /* Offset for the firmware version within the TCPM */ |
18 | #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 | |
19 | #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 | |
20 | ||
fea799e3 MN |
21 | /* PRCMU Wakeup defines */ |
22 | enum prcmu_wakeup_index { | |
23 | PRCMU_WAKEUP_INDEX_RTC, | |
24 | PRCMU_WAKEUP_INDEX_RTT0, | |
25 | PRCMU_WAKEUP_INDEX_RTT1, | |
26 | PRCMU_WAKEUP_INDEX_HSI0, | |
27 | PRCMU_WAKEUP_INDEX_HSI1, | |
28 | PRCMU_WAKEUP_INDEX_USB, | |
29 | PRCMU_WAKEUP_INDEX_ABB, | |
30 | PRCMU_WAKEUP_INDEX_ABB_FIFO, | |
31 | PRCMU_WAKEUP_INDEX_ARM, | |
32 | PRCMU_WAKEUP_INDEX_CD_IRQ, | |
33 | NUM_PRCMU_WAKEUP_INDICES | |
34 | }; | |
35 | #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) | |
36 | ||
37 | /* EPOD (power domain) IDs */ | |
38 | ||
39 | /* | |
40 | * DB8500 EPODs | |
41 | * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP | |
42 | * - EPOD_ID_SVAPIPE: power domain for SVA pipe | |
43 | * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP | |
44 | * - EPOD_ID_SIAPIPE: power domain for SIA pipe | |
45 | * - EPOD_ID_SGA: power domain for SGA | |
46 | * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE | |
47 | * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 | |
48 | * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 | |
49 | * - NUM_EPOD_ID: number of power domains | |
50 | * | |
51 | * TODO: These should be prefixed. | |
52 | */ | |
53 | #define EPOD_ID_SVAMMDSP 0 | |
54 | #define EPOD_ID_SVAPIPE 1 | |
55 | #define EPOD_ID_SIAMMDSP 2 | |
56 | #define EPOD_ID_SIAPIPE 3 | |
57 | #define EPOD_ID_SGA 4 | |
58 | #define EPOD_ID_B2R2_MCDE 5 | |
59 | #define EPOD_ID_ESRAM12 6 | |
60 | #define EPOD_ID_ESRAM34 7 | |
61 | #define NUM_EPOD_ID 8 | |
62 | ||
fea799e3 MN |
63 | /* |
64 | * state definition for EPOD (power domain) | |
65 | * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged | |
66 | * - EPOD_STATE_OFF: The EPOD is switched off | |
67 | * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in | |
68 | * retention | |
69 | * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off | |
70 | * - EPOD_STATE_ON: Same as above, but with clock enabled | |
71 | */ | |
72 | #define EPOD_STATE_NO_CHANGE 0x00 | |
73 | #define EPOD_STATE_OFF 0x01 | |
74 | #define EPOD_STATE_RAMRET 0x02 | |
75 | #define EPOD_STATE_ON_CLK_OFF 0x03 | |
76 | #define EPOD_STATE_ON 0x04 | |
77 | ||
78 | /* | |
79 | * CLKOUT sources | |
80 | */ | |
81 | #define PRCMU_CLKSRC_CLK38M 0x00 | |
82 | #define PRCMU_CLKSRC_ACLK 0x01 | |
83 | #define PRCMU_CLKSRC_SYSCLK 0x02 | |
84 | #define PRCMU_CLKSRC_LCDCLK 0x03 | |
85 | #define PRCMU_CLKSRC_SDMMCCLK 0x04 | |
86 | #define PRCMU_CLKSRC_TVCLK 0x05 | |
87 | #define PRCMU_CLKSRC_TIMCLK 0x06 | |
88 | #define PRCMU_CLKSRC_CLK009 0x07 | |
89 | /* These are only valid for CLKOUT1: */ | |
90 | #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 | |
91 | #define PRCMU_CLKSRC_I2CCLK 0x41 | |
92 | #define PRCMU_CLKSRC_MSP02CLK 0x42 | |
93 | #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 | |
94 | #define PRCMU_CLKSRC_HSIRXCLK 0x44 | |
95 | #define PRCMU_CLKSRC_HSITXCLK 0x45 | |
96 | #define PRCMU_CLKSRC_ARMCLKFIX 0x46 | |
97 | #define PRCMU_CLKSRC_HDMICLK 0x47 | |
98 | ||
98c60a0d FB |
99 | /** |
100 | * enum prcmu_wdog_id - PRCMU watchdog IDs | |
101 | * @PRCMU_WDOG_ALL: use all timers | |
102 | * @PRCMU_WDOG_CPU1: use first CPU timer only | |
103 | * @PRCMU_WDOG_CPU2: use second CPU timer conly | |
104 | */ | |
105 | enum prcmu_wdog_id { | |
106 | PRCMU_WDOG_ALL = 0x00, | |
107 | PRCMU_WDOG_CPU1 = 0x01, | |
108 | PRCMU_WDOG_CPU2 = 0x02, | |
109 | }; | |
110 | ||
fea799e3 MN |
111 | /** |
112 | * enum ape_opp - APE OPP states definition | |
113 | * @APE_OPP_INIT: | |
114 | * @APE_NO_CHANGE: The APE operating point is unchanged | |
115 | * @APE_100_OPP: The new APE operating point is ape100opp | |
116 | * @APE_50_OPP: 50% | |
4d64d2e3 | 117 | * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. |
fea799e3 MN |
118 | */ |
119 | enum ape_opp { | |
120 | APE_OPP_INIT = 0x00, | |
121 | APE_NO_CHANGE = 0x01, | |
122 | APE_100_OPP = 0x02, | |
4d64d2e3 MN |
123 | APE_50_OPP = 0x03, |
124 | APE_50_PARTLY_25_OPP = 0xFF, | |
fea799e3 MN |
125 | }; |
126 | ||
127 | /** | |
128 | * enum arm_opp - ARM OPP states definition | |
129 | * @ARM_OPP_INIT: | |
130 | * @ARM_NO_CHANGE: The ARM operating point is unchanged | |
131 | * @ARM_100_OPP: The new ARM operating point is arm100opp | |
132 | * @ARM_50_OPP: The new ARM operating point is arm50opp | |
133 | * @ARM_MAX_OPP: Operating point is "max" (more than 100) | |
134 | * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 | |
135 | * @ARM_EXTCLK: The new ARM operating point is armExtClk | |
136 | */ | |
137 | enum arm_opp { | |
138 | ARM_OPP_INIT = 0x00, | |
139 | ARM_NO_CHANGE = 0x01, | |
140 | ARM_100_OPP = 0x02, | |
141 | ARM_50_OPP = 0x03, | |
142 | ARM_MAX_OPP = 0x04, | |
143 | ARM_MAX_FREQ100OPP = 0x05, | |
144 | ARM_EXTCLK = 0x07 | |
145 | }; | |
146 | ||
147 | /** | |
148 | * enum ddr_opp - DDR OPP states definition | |
149 | * @DDR_100_OPP: The new DDR operating point is ddr100opp | |
150 | * @DDR_50_OPP: The new DDR operating point is ddr50opp | |
151 | * @DDR_25_OPP: The new DDR operating point is ddr25opp | |
152 | */ | |
153 | enum ddr_opp { | |
154 | DDR_100_OPP = 0x00, | |
155 | DDR_50_OPP = 0x01, | |
156 | DDR_25_OPP = 0x02, | |
157 | }; | |
158 | ||
159 | /* | |
160 | * Definitions for controlling ESRAM0 in deep sleep. | |
161 | */ | |
162 | #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 | |
163 | #define ESRAM0_DEEP_SLEEP_STATE_RET 2 | |
164 | ||
165 | /** | |
166 | * enum ddr_pwrst - DDR power states definition | |
167 | * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged | |
168 | * @DDR_PWR_STATE_ON: | |
169 | * @DDR_PWR_STATE_OFFLOWLAT: | |
170 | * @DDR_PWR_STATE_OFFHIGHLAT: | |
171 | */ | |
172 | enum ddr_pwrst { | |
173 | DDR_PWR_STATE_UNCHANGED = 0x00, | |
174 | DDR_PWR_STATE_ON = 0x01, | |
175 | DDR_PWR_STATE_OFFLOWLAT = 0x02, | |
176 | DDR_PWR_STATE_OFFHIGHLAT = 0x03 | |
177 | }; | |
178 | ||
05ec260e LW |
179 | #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 |
180 | ||
05ec260e LW |
181 | #define PRCMU_FW_PROJECT_U8500 2 |
182 | #define PRCMU_FW_PROJECT_U8400 3 | |
183 | #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ | |
184 | #define PRCMU_FW_PROJECT_U8500_MBB 5 | |
185 | #define PRCMU_FW_PROJECT_U8500_C1 6 | |
186 | #define PRCMU_FW_PROJECT_U8500_C2 7 | |
187 | #define PRCMU_FW_PROJECT_U8500_C3 8 | |
188 | #define PRCMU_FW_PROJECT_U8500_C4 9 | |
189 | #define PRCMU_FW_PROJECT_U9500_MBL 10 | |
190 | #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ | |
191 | #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ | |
192 | #define PRCMU_FW_PROJECT_U8520 13 | |
193 | #define PRCMU_FW_PROJECT_U8420 14 | |
194 | #define PRCMU_FW_PROJECT_A9420 20 | |
195 | /* [32..63] 9540 and derivatives */ | |
196 | #define PRCMU_FW_PROJECT_U9540 32 | |
197 | /* [64..95] 8540 and derivatives */ | |
198 | #define PRCMU_FW_PROJECT_L8540 64 | |
199 | /* [96..126] 8580 and derivatives */ | |
200 | #define PRCMU_FW_PROJECT_L8580 96 | |
201 | ||
202 | #define PRCMU_FW_PROJECT_NAME_LEN 20 | |
203 | struct prcmu_fw_version { | |
204 | u32 project; /* Notice, project shifted with 8 on ux540 */ | |
205 | u8 api_version; | |
206 | u8 func_version; | |
207 | u8 errata; | |
208 | char project_name[PRCMU_FW_PROJECT_NAME_LEN]; | |
209 | }; | |
210 | ||
fea799e3 | 211 | #include <linux/mfd/db8500-prcmu.h> |
fea799e3 | 212 | |
dece3709 | 213 | #if defined(CONFIG_UX500_SOC_DB8500) |
fea799e3 | 214 | |
9a47a8dc | 215 | static inline void prcmu_early_init(u32 phy_base, u32 size) |
fea799e3 | 216 | { |
9a47a8dc | 217 | return db8500_prcmu_early_init(phy_base, size); |
fea799e3 MN |
218 | } |
219 | ||
220 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
221 | bool keep_ap_pll) | |
222 | { | |
dece3709 LW |
223 | return db8500_prcmu_set_power_state(state, keep_ulp_clk, |
224 | keep_ap_pll); | |
fea799e3 MN |
225 | } |
226 | ||
4d64d2e3 MN |
227 | static inline u8 prcmu_get_power_state_result(void) |
228 | { | |
dece3709 | 229 | return db8500_prcmu_get_power_state_result(); |
4d64d2e3 MN |
230 | } |
231 | ||
fea799e3 MN |
232 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) |
233 | { | |
dece3709 | 234 | return db8500_prcmu_set_epod(epod_id, epod_state); |
fea799e3 MN |
235 | } |
236 | ||
237 | static inline void prcmu_enable_wakeups(u32 wakeups) | |
238 | { | |
dece3709 | 239 | db8500_prcmu_enable_wakeups(wakeups); |
fea799e3 MN |
240 | } |
241 | ||
242 | static inline void prcmu_disable_wakeups(void) | |
243 | { | |
244 | prcmu_enable_wakeups(0); | |
245 | } | |
246 | ||
247 | static inline void prcmu_config_abb_event_readout(u32 abb_events) | |
248 | { | |
dece3709 | 249 | db8500_prcmu_config_abb_event_readout(abb_events); |
fea799e3 MN |
250 | } |
251 | ||
252 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
253 | { | |
dece3709 | 254 | db8500_prcmu_get_abb_event_buffer(buf); |
fea799e3 MN |
255 | } |
256 | ||
257 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); | |
258 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | |
3c3e4898 | 259 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); |
fea799e3 MN |
260 | |
261 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div); | |
262 | ||
263 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
264 | { | |
dece3709 | 265 | return db8500_prcmu_request_clock(clock, enable); |
fea799e3 MN |
266 | } |
267 | ||
0508901c MN |
268 | unsigned long prcmu_clock_rate(u8 clock); |
269 | long prcmu_round_clock_rate(u8 clock, unsigned long rate); | |
270 | int prcmu_set_clock_rate(u8 clock, unsigned long rate); | |
271 | ||
272 | static inline int prcmu_set_ddr_opp(u8 opp) | |
273 | { | |
dece3709 | 274 | return db8500_prcmu_set_ddr_opp(opp); |
0508901c MN |
275 | } |
276 | static inline int prcmu_get_ddr_opp(void) | |
277 | { | |
dece3709 | 278 | return db8500_prcmu_get_ddr_opp(); |
0508901c | 279 | } |
fea799e3 MN |
280 | |
281 | static inline int prcmu_set_arm_opp(u8 opp) | |
282 | { | |
dece3709 | 283 | return db8500_prcmu_set_arm_opp(opp); |
fea799e3 MN |
284 | } |
285 | ||
286 | static inline int prcmu_get_arm_opp(void) | |
287 | { | |
dece3709 | 288 | return db8500_prcmu_get_arm_opp(); |
fea799e3 MN |
289 | } |
290 | ||
0508901c MN |
291 | static inline int prcmu_set_ape_opp(u8 opp) |
292 | { | |
dece3709 | 293 | return db8500_prcmu_set_ape_opp(opp); |
0508901c MN |
294 | } |
295 | ||
296 | static inline int prcmu_get_ape_opp(void) | |
297 | { | |
dece3709 | 298 | return db8500_prcmu_get_ape_opp(); |
0508901c MN |
299 | } |
300 | ||
686f871b UH |
301 | static inline int prcmu_request_ape_opp_100_voltage(bool enable) |
302 | { | |
303 | return db8500_prcmu_request_ape_opp_100_voltage(enable); | |
304 | } | |
305 | ||
fea799e3 MN |
306 | static inline void prcmu_system_reset(u16 reset_code) |
307 | { | |
dece3709 | 308 | return db8500_prcmu_system_reset(reset_code); |
fea799e3 MN |
309 | } |
310 | ||
311 | static inline u16 prcmu_get_reset_code(void) | |
312 | { | |
dece3709 | 313 | return db8500_prcmu_get_reset_code(); |
fea799e3 MN |
314 | } |
315 | ||
5261e101 | 316 | int prcmu_ac_wake_req(void); |
fea799e3 | 317 | void prcmu_ac_sleep_req(void); |
0508901c MN |
318 | static inline void prcmu_modem_reset(void) |
319 | { | |
dece3709 | 320 | return db8500_prcmu_modem_reset(); |
0508901c MN |
321 | } |
322 | ||
fea799e3 MN |
323 | static inline bool prcmu_is_ac_wake_requested(void) |
324 | { | |
dece3709 | 325 | return db8500_prcmu_is_ac_wake_requested(); |
fea799e3 MN |
326 | } |
327 | ||
328 | static inline int prcmu_set_display_clocks(void) | |
329 | { | |
dece3709 | 330 | return db8500_prcmu_set_display_clocks(); |
fea799e3 MN |
331 | } |
332 | ||
333 | static inline int prcmu_disable_dsipll(void) | |
334 | { | |
dece3709 | 335 | return db8500_prcmu_disable_dsipll(); |
fea799e3 MN |
336 | } |
337 | ||
338 | static inline int prcmu_enable_dsipll(void) | |
339 | { | |
dece3709 | 340 | return db8500_prcmu_enable_dsipll(); |
fea799e3 MN |
341 | } |
342 | ||
343 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
344 | { | |
dece3709 | 345 | return db8500_prcmu_config_esram0_deep_sleep(state); |
fea799e3 | 346 | } |
0508901c MN |
347 | |
348 | static inline int prcmu_config_hotdog(u8 threshold) | |
349 | { | |
dece3709 | 350 | return db8500_prcmu_config_hotdog(threshold); |
0508901c MN |
351 | } |
352 | ||
353 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
354 | { | |
dece3709 | 355 | return db8500_prcmu_config_hotmon(low, high); |
0508901c MN |
356 | } |
357 | ||
358 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
359 | { | |
dece3709 | 360 | return db8500_prcmu_start_temp_sense(cycles32k); |
0508901c MN |
361 | } |
362 | ||
363 | static inline int prcmu_stop_temp_sense(void) | |
364 | { | |
dece3709 | 365 | return db8500_prcmu_stop_temp_sense(); |
0508901c MN |
366 | } |
367 | ||
b4a6dbd5 MN |
368 | static inline u32 prcmu_read(unsigned int reg) |
369 | { | |
dece3709 | 370 | return db8500_prcmu_read(reg); |
b4a6dbd5 MN |
371 | } |
372 | ||
373 | static inline void prcmu_write(unsigned int reg, u32 value) | |
374 | { | |
dece3709 | 375 | db8500_prcmu_write(reg, value); |
b4a6dbd5 MN |
376 | } |
377 | ||
378 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) | |
379 | { | |
dece3709 | 380 | db8500_prcmu_write_masked(reg, mask, value); |
b4a6dbd5 MN |
381 | } |
382 | ||
0508901c MN |
383 | static inline int prcmu_enable_a9wdog(u8 id) |
384 | { | |
dece3709 | 385 | return db8500_prcmu_enable_a9wdog(id); |
0508901c MN |
386 | } |
387 | ||
388 | static inline int prcmu_disable_a9wdog(u8 id) | |
389 | { | |
dece3709 | 390 | return db8500_prcmu_disable_a9wdog(id); |
0508901c MN |
391 | } |
392 | ||
393 | static inline int prcmu_kick_a9wdog(u8 id) | |
394 | { | |
dece3709 | 395 | return db8500_prcmu_kick_a9wdog(id); |
0508901c MN |
396 | } |
397 | ||
398 | static inline int prcmu_load_a9wdog(u8 id, u32 timeout) | |
399 | { | |
dece3709 | 400 | return db8500_prcmu_load_a9wdog(id, timeout); |
0508901c MN |
401 | } |
402 | ||
403 | static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) | |
404 | { | |
dece3709 | 405 | return db8500_prcmu_config_a9wdog(num, sleep_auto_off); |
0508901c | 406 | } |
fea799e3 MN |
407 | #else |
408 | ||
9a47a8dc | 409 | static inline void prcmu_early_init(u32 phy_base, u32 size) {} |
fea799e3 MN |
410 | |
411 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
412 | bool keep_ap_pll) | |
413 | { | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) | |
418 | { | |
419 | return 0; | |
420 | } | |
421 | ||
422 | static inline void prcmu_enable_wakeups(u32 wakeups) {} | |
423 | ||
424 | static inline void prcmu_disable_wakeups(void) {} | |
425 | ||
426 | static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
427 | { | |
428 | return -ENOSYS; | |
429 | } | |
430 | ||
431 | static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
432 | { | |
433 | return -ENOSYS; | |
434 | } | |
435 | ||
3c3e4898 MN |
436 | static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, |
437 | u8 size) | |
438 | { | |
439 | return -ENOSYS; | |
440 | } | |
441 | ||
fea799e3 MN |
442 | static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) |
443 | { | |
444 | return 0; | |
445 | } | |
446 | ||
447 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
448 | { | |
449 | return 0; | |
6b6fae2b MN |
450 | } |
451 | ||
452 | static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
453 | { | |
454 | return 0; | |
455 | } | |
456 | ||
457 | static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
458 | { | |
459 | return 0; | |
460 | } | |
461 | ||
462 | static inline unsigned long prcmu_clock_rate(u8 clock) | |
463 | { | |
464 | return 0; | |
fea799e3 MN |
465 | } |
466 | ||
467 | static inline int prcmu_set_ape_opp(u8 opp) | |
468 | { | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static inline int prcmu_get_ape_opp(void) | |
473 | { | |
474 | return APE_100_OPP; | |
475 | } | |
476 | ||
686f871b UH |
477 | static inline int prcmu_request_ape_opp_100_voltage(bool enable) |
478 | { | |
479 | return 0; | |
480 | } | |
481 | ||
fea799e3 MN |
482 | static inline int prcmu_set_arm_opp(u8 opp) |
483 | { | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static inline int prcmu_get_arm_opp(void) | |
488 | { | |
489 | return ARM_100_OPP; | |
490 | } | |
491 | ||
492 | static inline int prcmu_set_ddr_opp(u8 opp) | |
493 | { | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static inline int prcmu_get_ddr_opp(void) | |
498 | { | |
499 | return DDR_100_OPP; | |
500 | } | |
501 | ||
502 | static inline void prcmu_system_reset(u16 reset_code) {} | |
503 | ||
504 | static inline u16 prcmu_get_reset_code(void) | |
505 | { | |
506 | return 0; | |
507 | } | |
508 | ||
5261e101 AM |
509 | static inline int prcmu_ac_wake_req(void) |
510 | { | |
511 | return 0; | |
512 | } | |
fea799e3 MN |
513 | |
514 | static inline void prcmu_ac_sleep_req(void) {} | |
515 | ||
516 | static inline void prcmu_modem_reset(void) {} | |
517 | ||
518 | static inline bool prcmu_is_ac_wake_requested(void) | |
519 | { | |
520 | return false; | |
521 | } | |
522 | ||
523 | static inline int prcmu_set_display_clocks(void) | |
524 | { | |
525 | return 0; | |
526 | } | |
527 | ||
528 | static inline int prcmu_disable_dsipll(void) | |
529 | { | |
530 | return 0; | |
531 | } | |
532 | ||
533 | static inline int prcmu_enable_dsipll(void) | |
534 | { | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
539 | { | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static inline void prcmu_config_abb_event_readout(u32 abb_events) {} | |
544 | ||
545 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
546 | { | |
547 | *buf = NULL; | |
548 | } | |
549 | ||
0508901c MN |
550 | static inline int prcmu_config_hotdog(u8 threshold) |
551 | { | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
556 | { | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
561 | { | |
562 | return 0; | |
563 | } | |
564 | ||
565 | static inline int prcmu_stop_temp_sense(void) | |
566 | { | |
567 | return 0; | |
568 | } | |
569 | ||
b4a6dbd5 MN |
570 | static inline u32 prcmu_read(unsigned int reg) |
571 | { | |
572 | return 0; | |
573 | } | |
574 | ||
575 | static inline void prcmu_write(unsigned int reg, u32 value) {} | |
576 | ||
577 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} | |
578 | ||
579 | #endif | |
580 | ||
581 | static inline void prcmu_set(unsigned int reg, u32 bits) | |
582 | { | |
583 | prcmu_write_masked(reg, bits, bits); | |
584 | } | |
585 | ||
586 | static inline void prcmu_clear(unsigned int reg, u32 bits) | |
587 | { | |
588 | prcmu_write_masked(reg, bits, 0); | |
589 | } | |
590 | ||
fea799e3 MN |
591 | /* PRCMU QoS APE OPP class */ |
592 | #define PRCMU_QOS_APE_OPP 1 | |
593 | #define PRCMU_QOS_DDR_OPP 2 | |
4d64d2e3 | 594 | #define PRCMU_QOS_ARM_OPP 3 |
fea799e3 MN |
595 | #define PRCMU_QOS_DEFAULT_VALUE -1 |
596 | ||
4d64d2e3 | 597 | #ifdef CONFIG_DBX500_PRCMU_QOS_POWER |
fea799e3 MN |
598 | |
599 | unsigned long prcmu_qos_get_cpufreq_opp_delay(void); | |
600 | void prcmu_qos_set_cpufreq_opp_delay(unsigned long); | |
601 | void prcmu_qos_force_opp(int, s32); | |
602 | int prcmu_qos_requirement(int pm_qos_class); | |
603 | int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); | |
604 | int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); | |
605 | void prcmu_qos_remove_requirement(int pm_qos_class, char *name); | |
606 | int prcmu_qos_add_notifier(int prcmu_qos_class, | |
607 | struct notifier_block *notifier); | |
608 | int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
609 | struct notifier_block *notifier); | |
610 | ||
611 | #else | |
612 | ||
613 | static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) | |
614 | { | |
615 | return 0; | |
616 | } | |
617 | ||
618 | static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} | |
619 | ||
620 | static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} | |
621 | ||
622 | static inline int prcmu_qos_requirement(int prcmu_qos_class) | |
623 | { | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static inline int prcmu_qos_add_requirement(int prcmu_qos_class, | |
628 | char *name, s32 value) | |
629 | { | |
630 | return 0; | |
631 | } | |
632 | ||
633 | static inline int prcmu_qos_update_requirement(int prcmu_qos_class, | |
634 | char *name, s32 new_value) | |
635 | { | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) | |
640 | { | |
641 | } | |
642 | ||
643 | static inline int prcmu_qos_add_notifier(int prcmu_qos_class, | |
644 | struct notifier_block *notifier) | |
645 | { | |
646 | return 0; | |
647 | } | |
648 | static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
649 | struct notifier_block *notifier) | |
650 | { | |
651 | return 0; | |
652 | } | |
653 | ||
654 | #endif | |
655 | ||
656 | #endif /* __MACH_PRCMU_H */ |