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527e7e9a MH |
1 | /* |
2 | * max8997.h - Voltage regulator driver for the Maxim 8997 | |
3 | * | |
4 | * Copyright (C) 2010 Samsung Electrnoics | |
5 | * MyungJoo Ham <myungjoo.ham@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __LINUX_MFD_MAX8997_PRIV_H | |
23 | #define __LINUX_MFD_MAX8997_PRIV_H | |
24 | ||
25 | #include <linux/i2c.h> | |
26 | ||
8de6bc7f MH |
27 | #define MAX8997_REG_INVALID (0xff) |
28 | ||
527e7e9a MH |
29 | enum max8997_pmic_reg { |
30 | MAX8997_REG_PMIC_ID0 = 0x00, | |
31 | MAX8997_REG_PMIC_ID1 = 0x01, | |
32 | MAX8997_REG_INTSRC = 0x02, | |
33 | MAX8997_REG_INT1 = 0x03, | |
34 | MAX8997_REG_INT2 = 0x04, | |
35 | MAX8997_REG_INT3 = 0x05, | |
36 | MAX8997_REG_INT4 = 0x06, | |
37 | ||
38 | MAX8997_REG_INT1MSK = 0x08, | |
39 | MAX8997_REG_INT2MSK = 0x09, | |
40 | MAX8997_REG_INT3MSK = 0x0a, | |
41 | MAX8997_REG_INT4MSK = 0x0b, | |
42 | ||
43 | MAX8997_REG_STATUS1 = 0x0d, | |
44 | MAX8997_REG_STATUS2 = 0x0e, | |
45 | MAX8997_REG_STATUS3 = 0x0f, | |
46 | MAX8997_REG_STATUS4 = 0x10, | |
47 | ||
48 | MAX8997_REG_MAINCON1 = 0x13, | |
49 | MAX8997_REG_MAINCON2 = 0x14, | |
50 | MAX8997_REG_BUCKRAMP = 0x15, | |
51 | ||
52 | MAX8997_REG_BUCK1CTRL = 0x18, | |
53 | MAX8997_REG_BUCK1DVS1 = 0x19, | |
54 | MAX8997_REG_BUCK1DVS2 = 0x1a, | |
55 | MAX8997_REG_BUCK1DVS3 = 0x1b, | |
56 | MAX8997_REG_BUCK1DVS4 = 0x1c, | |
57 | MAX8997_REG_BUCK1DVS5 = 0x1d, | |
58 | MAX8997_REG_BUCK1DVS6 = 0x1e, | |
59 | MAX8997_REG_BUCK1DVS7 = 0x1f, | |
60 | MAX8997_REG_BUCK1DVS8 = 0x20, | |
61 | MAX8997_REG_BUCK2CTRL = 0x21, | |
62 | MAX8997_REG_BUCK2DVS1 = 0x22, | |
63 | MAX8997_REG_BUCK2DVS2 = 0x23, | |
64 | MAX8997_REG_BUCK2DVS3 = 0x24, | |
65 | MAX8997_REG_BUCK2DVS4 = 0x25, | |
66 | MAX8997_REG_BUCK2DVS5 = 0x26, | |
67 | MAX8997_REG_BUCK2DVS6 = 0x27, | |
68 | MAX8997_REG_BUCK2DVS7 = 0x28, | |
69 | MAX8997_REG_BUCK2DVS8 = 0x29, | |
70 | MAX8997_REG_BUCK3CTRL = 0x2a, | |
71 | MAX8997_REG_BUCK3DVS = 0x2b, | |
72 | MAX8997_REG_BUCK4CTRL = 0x2c, | |
73 | MAX8997_REG_BUCK4DVS = 0x2d, | |
74 | MAX8997_REG_BUCK5CTRL = 0x2e, | |
75 | MAX8997_REG_BUCK5DVS1 = 0x2f, | |
76 | MAX8997_REG_BUCK5DVS2 = 0x30, | |
77 | MAX8997_REG_BUCK5DVS3 = 0x31, | |
78 | MAX8997_REG_BUCK5DVS4 = 0x32, | |
79 | MAX8997_REG_BUCK5DVS5 = 0x33, | |
80 | MAX8997_REG_BUCK5DVS6 = 0x34, | |
81 | MAX8997_REG_BUCK5DVS7 = 0x35, | |
82 | MAX8997_REG_BUCK5DVS8 = 0x36, | |
83 | MAX8997_REG_BUCK6CTRL = 0x37, | |
84 | MAX8997_REG_BUCK6BPSKIPCTRL = 0x38, | |
85 | MAX8997_REG_BUCK7CTRL = 0x39, | |
86 | MAX8997_REG_BUCK7DVS = 0x3a, | |
87 | MAX8997_REG_LDO1CTRL = 0x3b, | |
88 | MAX8997_REG_LDO2CTRL = 0x3c, | |
89 | MAX8997_REG_LDO3CTRL = 0x3d, | |
90 | MAX8997_REG_LDO4CTRL = 0x3e, | |
91 | MAX8997_REG_LDO5CTRL = 0x3f, | |
92 | MAX8997_REG_LDO6CTRL = 0x40, | |
93 | MAX8997_REG_LDO7CTRL = 0x41, | |
94 | MAX8997_REG_LDO8CTRL = 0x42, | |
95 | MAX8997_REG_LDO9CTRL = 0x43, | |
96 | MAX8997_REG_LDO10CTRL = 0x44, | |
97 | MAX8997_REG_LDO11CTRL = 0x45, | |
98 | MAX8997_REG_LDO12CTRL = 0x46, | |
99 | MAX8997_REG_LDO13CTRL = 0x47, | |
100 | MAX8997_REG_LDO14CTRL = 0x48, | |
101 | MAX8997_REG_LDO15CTRL = 0x49, | |
102 | MAX8997_REG_LDO16CTRL = 0x4a, | |
103 | MAX8997_REG_LDO17CTRL = 0x4b, | |
104 | MAX8997_REG_LDO18CTRL = 0x4c, | |
105 | MAX8997_REG_LDO21CTRL = 0x4d, | |
106 | ||
107 | MAX8997_REG_MBCCTRL1 = 0x50, | |
108 | MAX8997_REG_MBCCTRL2 = 0x51, | |
109 | MAX8997_REG_MBCCTRL3 = 0x52, | |
110 | MAX8997_REG_MBCCTRL4 = 0x53, | |
111 | MAX8997_REG_MBCCTRL5 = 0x54, | |
112 | MAX8997_REG_MBCCTRL6 = 0x55, | |
113 | MAX8997_REG_OTPCGHCVS = 0x56, | |
114 | ||
115 | MAX8997_REG_SAFEOUTCTRL = 0x5a, | |
116 | ||
117 | MAX8997_REG_LBCNFG1 = 0x5e, | |
118 | MAX8997_REG_LBCNFG2 = 0x5f, | |
119 | MAX8997_REG_BBCCTRL = 0x60, | |
120 | ||
121 | MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */ | |
122 | MAX8997_REG_FLASH2_CUR = 0x64, | |
123 | MAX8997_REG_MOVIE_CUR = 0x65, | |
124 | MAX8997_REG_GSMB_CUR = 0x66, | |
125 | MAX8997_REG_BOOST_CNTL = 0x67, | |
126 | MAX8997_REG_LEN_CNTL = 0x68, | |
127 | MAX8997_REG_FLASH_CNTL = 0x69, | |
128 | MAX8997_REG_WDT_CNTL = 0x6a, | |
129 | MAX8997_REG_MAXFLASH1 = 0x6b, | |
130 | MAX8997_REG_MAXFLASH2 = 0x6c, | |
131 | MAX8997_REG_FLASHSTATUS = 0x6d, | |
132 | MAX8997_REG_FLASHSTATUSMASK = 0x6e, | |
133 | ||
134 | MAX8997_REG_GPIOCNTL1 = 0x70, | |
135 | MAX8997_REG_GPIOCNTL2 = 0x71, | |
136 | MAX8997_REG_GPIOCNTL3 = 0x72, | |
137 | MAX8997_REG_GPIOCNTL4 = 0x73, | |
138 | MAX8997_REG_GPIOCNTL5 = 0x74, | |
139 | MAX8997_REG_GPIOCNTL6 = 0x75, | |
140 | MAX8997_REG_GPIOCNTL7 = 0x76, | |
141 | MAX8997_REG_GPIOCNTL8 = 0x77, | |
142 | MAX8997_REG_GPIOCNTL9 = 0x78, | |
143 | MAX8997_REG_GPIOCNTL10 = 0x79, | |
144 | MAX8997_REG_GPIOCNTL11 = 0x7a, | |
145 | MAX8997_REG_GPIOCNTL12 = 0x7b, | |
146 | ||
147 | MAX8997_REG_LDO1CONFIG = 0x80, | |
148 | MAX8997_REG_LDO2CONFIG = 0x81, | |
149 | MAX8997_REG_LDO3CONFIG = 0x82, | |
150 | MAX8997_REG_LDO4CONFIG = 0x83, | |
151 | MAX8997_REG_LDO5CONFIG = 0x84, | |
152 | MAX8997_REG_LDO6CONFIG = 0x85, | |
153 | MAX8997_REG_LDO7CONFIG = 0x86, | |
154 | MAX8997_REG_LDO8CONFIG = 0x87, | |
155 | MAX8997_REG_LDO9CONFIG = 0x88, | |
156 | MAX8997_REG_LDO10CONFIG = 0x89, | |
157 | MAX8997_REG_LDO11CONFIG = 0x8a, | |
158 | MAX8997_REG_LDO12CONFIG = 0x8b, | |
159 | MAX8997_REG_LDO13CONFIG = 0x8c, | |
160 | MAX8997_REG_LDO14CONFIG = 0x8d, | |
161 | MAX8997_REG_LDO15CONFIG = 0x8e, | |
162 | MAX8997_REG_LDO16CONFIG = 0x8f, | |
163 | MAX8997_REG_LDO17CONFIG = 0x90, | |
164 | MAX8997_REG_LDO18CONFIG = 0x91, | |
165 | MAX8997_REG_LDO21CONFIG = 0x92, | |
166 | ||
167 | MAX8997_REG_DVSOKTIMER1 = 0x97, | |
168 | MAX8997_REG_DVSOKTIMER2 = 0x98, | |
169 | MAX8997_REG_DVSOKTIMER4 = 0x99, | |
170 | MAX8997_REG_DVSOKTIMER5 = 0x9a, | |
171 | ||
172 | MAX8997_REG_PMIC_END = 0x9b, | |
173 | }; | |
174 | ||
175 | enum max8997_muic_reg { | |
176 | MAX8997_MUIC_REG_ID = 0x0, | |
177 | MAX8997_MUIC_REG_INT1 = 0x1, | |
178 | MAX8997_MUIC_REG_INT2 = 0x2, | |
179 | MAX8997_MUIC_REG_INT3 = 0x3, | |
180 | MAX8997_MUIC_REG_STATUS1 = 0x4, | |
181 | MAX8997_MUIC_REG_STATUS2 = 0x5, | |
182 | MAX8997_MUIC_REG_STATUS3 = 0x6, | |
183 | MAX8997_MUIC_REG_INTMASK1 = 0x7, | |
184 | MAX8997_MUIC_REG_INTMASK2 = 0x8, | |
185 | MAX8997_MUIC_REG_INTMASK3 = 0x9, | |
186 | MAX8997_MUIC_REG_CDETCTRL = 0xa, | |
187 | ||
188 | MAX8997_MUIC_REG_CONTROL1 = 0xc, | |
189 | MAX8997_MUIC_REG_CONTROL2 = 0xd, | |
190 | MAX8997_MUIC_REG_CONTROL3 = 0xe, | |
191 | ||
192 | MAX8997_MUIC_REG_END = 0xf, | |
193 | }; | |
194 | ||
195 | enum max8997_haptic_reg { | |
196 | MAX8997_HAPTIC_REG_GENERAL = 0x00, | |
197 | MAX8997_HAPTIC_REG_CONF1 = 0x01, | |
198 | MAX8997_HAPTIC_REG_CONF2 = 0x02, | |
199 | MAX8997_HAPTIC_REG_DRVCONF = 0x03, | |
200 | MAX8997_HAPTIC_REG_CYCLECONF1 = 0x04, | |
201 | MAX8997_HAPTIC_REG_CYCLECONF2 = 0x05, | |
202 | MAX8997_HAPTIC_REG_SIGCONF1 = 0x06, | |
203 | MAX8997_HAPTIC_REG_SIGCONF2 = 0x07, | |
204 | MAX8997_HAPTIC_REG_SIGCONF3 = 0x08, | |
205 | MAX8997_HAPTIC_REG_SIGCONF4 = 0x09, | |
206 | MAX8997_HAPTIC_REG_SIGDC1 = 0x0a, | |
207 | MAX8997_HAPTIC_REG_SIGDC2 = 0x0b, | |
208 | MAX8997_HAPTIC_REG_SIGPWMDC1 = 0x0c, | |
209 | MAX8997_HAPTIC_REG_SIGPWMDC2 = 0x0d, | |
210 | MAX8997_HAPTIC_REG_SIGPWMDC3 = 0x0e, | |
211 | MAX8997_HAPTIC_REG_SIGPWMDC4 = 0x0f, | |
212 | MAX8997_HAPTIC_REG_MTR_REV = 0x10, | |
213 | ||
214 | MAX8997_HAPTIC_REG_END = 0x11, | |
215 | }; | |
216 | ||
217 | /* slave addr = 0x0c: using "2nd part" of rev4 datasheet */ | |
218 | enum max8997_rtc_reg { | |
219 | MAX8997_RTC_CTRLMASK = 0x02, | |
220 | MAX8997_RTC_CTRL = 0x03, | |
221 | MAX8997_RTC_UPDATE1 = 0x04, | |
222 | MAX8997_RTC_UPDATE2 = 0x05, | |
223 | MAX8997_RTC_WTSR_SMPL = 0x06, | |
224 | ||
225 | MAX8997_RTC_SEC = 0x10, | |
226 | MAX8997_RTC_MIN = 0x11, | |
227 | MAX8997_RTC_HOUR = 0x12, | |
228 | MAX8997_RTC_DAY_OF_WEEK = 0x13, | |
229 | MAX8997_RTC_MONTH = 0x14, | |
230 | MAX8997_RTC_YEAR = 0x15, | |
231 | MAX8997_RTC_DAY_OF_MONTH = 0x16, | |
232 | MAX8997_RTC_ALARM1_SEC = 0x17, | |
233 | MAX8997_RTC_ALARM1_MIN = 0x18, | |
234 | MAX8997_RTC_ALARM1_HOUR = 0x19, | |
235 | MAX8997_RTC_ALARM1_DAY_OF_WEEK = 0x1a, | |
236 | MAX8997_RTC_ALARM1_MONTH = 0x1b, | |
237 | MAX8997_RTC_ALARM1_YEAR = 0x1c, | |
238 | MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d, | |
239 | MAX8997_RTC_ALARM2_SEC = 0x1e, | |
240 | MAX8997_RTC_ALARM2_MIN = 0x1f, | |
241 | MAX8997_RTC_ALARM2_HOUR = 0x20, | |
242 | MAX8997_RTC_ALARM2_DAY_OF_WEEK = 0x21, | |
243 | MAX8997_RTC_ALARM2_MONTH = 0x22, | |
244 | MAX8997_RTC_ALARM2_YEAR = 0x23, | |
245 | MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24, | |
246 | }; | |
247 | ||
248 | enum max8997_irq_source { | |
249 | PMIC_INT1 = 0, | |
250 | PMIC_INT2, | |
251 | PMIC_INT3, | |
252 | PMIC_INT4, | |
253 | ||
254 | FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */ | |
255 | ||
256 | MUIC_INT1, | |
257 | MUIC_INT2, | |
258 | MUIC_INT3, | |
259 | ||
260 | GPIO_LOW, /* Not implemented */ | |
261 | GPIO_HI, /* Not implemented */ | |
262 | ||
263 | FLASH_STATUS, /* Not implemented */ | |
264 | ||
265 | MAX8997_IRQ_GROUP_NR, | |
266 | }; | |
267 | ||
268 | enum max8997_irq { | |
269 | MAX8997_PMICIRQ_PWRONR, | |
270 | MAX8997_PMICIRQ_PWRONF, | |
271 | MAX8997_PMICIRQ_PWRON1SEC, | |
272 | MAX8997_PMICIRQ_JIGONR, | |
273 | MAX8997_PMICIRQ_JIGONF, | |
274 | MAX8997_PMICIRQ_LOWBAT2, | |
275 | MAX8997_PMICIRQ_LOWBAT1, | |
276 | ||
277 | MAX8997_PMICIRQ_JIGR, | |
278 | MAX8997_PMICIRQ_JIGF, | |
279 | MAX8997_PMICIRQ_MR, | |
280 | MAX8997_PMICIRQ_DVS1OK, | |
281 | MAX8997_PMICIRQ_DVS2OK, | |
282 | MAX8997_PMICIRQ_DVS3OK, | |
283 | MAX8997_PMICIRQ_DVS4OK, | |
284 | ||
285 | MAX8997_PMICIRQ_CHGINS, | |
286 | MAX8997_PMICIRQ_CHGRM, | |
287 | MAX8997_PMICIRQ_DCINOVP, | |
288 | MAX8997_PMICIRQ_TOPOFFR, | |
289 | MAX8997_PMICIRQ_CHGRSTF, | |
290 | MAX8997_PMICIRQ_MBCHGTMEXPD, | |
291 | ||
292 | MAX8997_PMICIRQ_RTC60S, | |
293 | MAX8997_PMICIRQ_RTCA1, | |
294 | MAX8997_PMICIRQ_RTCA2, | |
295 | MAX8997_PMICIRQ_SMPL_INT, | |
296 | MAX8997_PMICIRQ_RTC1S, | |
297 | MAX8997_PMICIRQ_WTSR, | |
298 | ||
299 | MAX8997_MUICIRQ_ADCError, | |
300 | MAX8997_MUICIRQ_ADCLow, | |
301 | MAX8997_MUICIRQ_ADC, | |
302 | ||
303 | MAX8997_MUICIRQ_VBVolt, | |
304 | MAX8997_MUICIRQ_DBChg, | |
305 | MAX8997_MUICIRQ_DCDTmr, | |
306 | MAX8997_MUICIRQ_ChgDetRun, | |
307 | MAX8997_MUICIRQ_ChgTyp, | |
308 | ||
309 | MAX8997_MUICIRQ_OVP, | |
310 | ||
311 | MAX8997_IRQ_NR, | |
312 | }; | |
313 | ||
314 | #define MAX8997_REG_BUCK1DVS(x) (MAX8997_REG_BUCK1DVS1 + (x) - 1) | |
315 | #define MAX8997_REG_BUCK2DVS(x) (MAX8997_REG_BUCK2DVS1 + (x) - 1) | |
316 | #define MAX8997_REG_BUCK5DVS(x) (MAX8997_REG_BUCK5DVS1 + (x) - 1) | |
317 | ||
8de6bc7f | 318 | #define MAX8997_NUM_GPIO 12 |
527e7e9a MH |
319 | struct max8997_dev { |
320 | struct device *dev; | |
321 | struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */ | |
322 | struct i2c_client *rtc; /* slave addr 0x0c */ | |
323 | struct i2c_client *haptic; /* slave addr 0x90 */ | |
324 | struct i2c_client *muic; /* slave addr 0x4a */ | |
325 | struct mutex iolock; | |
326 | ||
327 | int type; | |
328 | struct platform_device *battery; /* battery control (not fuel gauge) */ | |
329 | ||
8de6bc7f MH |
330 | int irq; |
331 | int ono; | |
332 | int irq_base; | |
527e7e9a | 333 | bool wakeup; |
8de6bc7f MH |
334 | struct mutex irqlock; |
335 | int irq_masks_cur[MAX8997_IRQ_GROUP_NR]; | |
336 | int irq_masks_cache[MAX8997_IRQ_GROUP_NR]; | |
527e7e9a MH |
337 | |
338 | /* For hibernation */ | |
339 | u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END + | |
340 | MAX8997_HAPTIC_REG_END]; | |
8de6bc7f MH |
341 | |
342 | bool gpio_status[MAX8997_NUM_GPIO]; | |
527e7e9a MH |
343 | }; |
344 | ||
345 | enum max8997_types { | |
346 | TYPE_MAX8997, | |
347 | TYPE_MAX8966, | |
348 | }; | |
349 | ||
8de6bc7f MH |
350 | extern int max8997_irq_init(struct max8997_dev *max8997); |
351 | extern void max8997_irq_exit(struct max8997_dev *max8997); | |
352 | extern int max8997_irq_resume(struct max8997_dev *max8997); | |
353 | ||
527e7e9a MH |
354 | extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); |
355 | extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count, | |
356 | u8 *buf); | |
357 | extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value); | |
358 | extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count, | |
359 | u8 *buf); | |
360 | extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); | |
361 | ||
8de6bc7f MH |
362 | #define MAX8997_GPIO_INT_BOTH (0x3 << 4) |
363 | #define MAX8997_GPIO_INT_RISE (0x2 << 4) | |
364 | #define MAX8997_GPIO_INT_FALL (0x1 << 4) | |
365 | ||
366 | #define MAX8997_GPIO_INT_MASK (0x3 << 4) | |
367 | #define MAX8997_GPIO_DATA_MASK (0x1 << 2) | |
527e7e9a | 368 | #endif /* __LINUX_MFD_MAX8997_PRIV_H */ |