[deliverable/linux.git] / include / linux / mfd / mc13783.h

/*
 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
 * Copyright 2009-2010 Pengutronix
 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */
#ifndef __LINUX_MFD_MC13783_H
#define __LINUX_MFD_MC13783_H

#include <linux/mfd/mc13xxx.h>

struct mc13783;

struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);

static inline void mc13783_lock(struct mc13783 *mc13783)
{
	mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
}

static inline void mc13783_unlock(struct mc13783 *mc13783)
{
	mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
}

static inline int mc13783_reg_read(struct mc13783 *mc13783,
		unsigned int offset, u32 *val)
{
	return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
}

static inline int mc13783_reg_write(struct mc13783 *mc13783,
		unsigned int offset, u32 val)
{
	return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
}

static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
		unsigned int offset, u32 mask, u32 val)
{
	return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
}

static inline int mc13783_get_flags(struct mc13783 *mc13783)
{
	return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
}

static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
		irq_handler_t handler, const char *name, void *dev)
{
	return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
			handler, name, dev);
}

static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
		irq_handler_t handler, const char *name, void *dev)
{
	return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
			handler, name, dev);
}

static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
{
	return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
}

static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
{
	return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
}

static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
{
	return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
}
static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
		int *enabled, int *pending)
{
	return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
			irq, enabled, pending);
}

static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
{
	return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
}

#define MC13783_ADC0		43
#define MC13783_ADC0_ADREFEN		(1 << 10)
#define MC13783_ADC0_ADREFMODE		(1 << 11)
#define MC13783_ADC0_TSMOD0		(1 << 12)
#define MC13783_ADC0_TSMOD1		(1 << 13)
#define MC13783_ADC0_TSMOD2		(1 << 14)
#define MC13783_ADC0_ADINC1		(1 << 16)
#define MC13783_ADC0_ADINC2		(1 << 17)

#define MC13783_ADC0_TSMOD_MASK		(MC13783_ADC0_TSMOD0 | \
					MC13783_ADC0_TSMOD1 | \
					MC13783_ADC0_TSMOD2)

#define mc13783_regulator_init_data mc13xxx_regulator_init_data
#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
#define mc13783_led_platform_data mc13xxx_led_platform_data
#define mc13783_leds_platform_data mc13xxx_leds_platform_data

#define mc13783_platform_data mc13xxx_platform_data
#define MC13783_USE_TOUCHSCREEN	MC13XXX_USE_TOUCHSCREEN
#define MC13783_USE_CODEC	MC13XXX_USE_CODEC
#define MC13783_USE_ADC		MC13XXX_USE_ADC
#define MC13783_USE_RTC		MC13XXX_USE_RTC
#define MC13783_USE_REGULATOR	MC13XXX_USE_REGULATOR
#define MC13783_USE_LED		MC13XXX_USE_LED

#define MC13783_ADC_MODE_TS		1
#define MC13783_ADC_MODE_SINGLE_CHAN	2
#define MC13783_ADC_MODE_MULT_CHAN	3

int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
		unsigned int channel, unsigned int *sample);


#define	MC13783_REG_SW1A		0
#define	MC13783_REG_SW1B		1
#define	MC13783_REG_SW2A		2
#define	MC13783_REG_SW2B		3
#define	MC13783_REG_SW3		4
#define	MC13783_REG_PLL		5
#define	MC13783_REG_VAUDIO	6
#define	MC13783_REG_VIOHI	7
#define	MC13783_REG_VIOLO	8
#define	MC13783_REG_VDIG	9
#define	MC13783_REG_VGEN	10
#define	MC13783_REG_VRFDIG	11
#define	MC13783_REG_VRFREF	12
#define	MC13783_REG_VRFCP	13
#define	MC13783_REG_VSIM	14
#define	MC13783_REG_VESIM	15
#define	MC13783_REG_VCAM	16
#define	MC13783_REG_VRFBG	17
#define	MC13783_REG_VVIB	18
#define	MC13783_REG_VRF1	19
#define	MC13783_REG_VRF2	20
#define	MC13783_REG_VMMC1	21
#define	MC13783_REG_VMMC2	22
#define	MC13783_REG_GPO1	23
#define	MC13783_REG_GPO2	24
#define	MC13783_REG_GPO3	25
#define	MC13783_REG_GPO4	26
#define	MC13783_REG_V1		27
#define	MC13783_REG_V2		28
#define	MC13783_REG_V3		29
#define	MC13783_REG_V4		30
#define	MC13783_REG_PWGT1SPI	31
#define	MC13783_REG_PWGT2SPI	32

#define MC13783_IRQ_ADCDONE	MC13XXX_IRQ_ADCDONE
#define MC13783_IRQ_ADCBISDONE	MC13XXX_IRQ_ADCBISDONE
#define MC13783_IRQ_TS		MC13XXX_IRQ_TS
#define MC13783_IRQ_WHIGH	3
#define MC13783_IRQ_WLOW	4
#define MC13783_IRQ_CHGDET	MC13XXX_IRQ_CHGDET
#define MC13783_IRQ_CHGOV	7
#define MC13783_IRQ_CHGREV	MC13XXX_IRQ_CHGREV
#define MC13783_IRQ_CHGSHORT	MC13XXX_IRQ_CHGSHORT
#define MC13783_IRQ_CCCV	MC13XXX_IRQ_CCCV
#define MC13783_IRQ_CHGCURR	MC13XXX_IRQ_CHGCURR
#define MC13783_IRQ_BPON	MC13XXX_IRQ_BPON
#define MC13783_IRQ_LOBATL	MC13XXX_IRQ_LOBATL
#define MC13783_IRQ_LOBATH	MC13XXX_IRQ_LOBATH
#define MC13783_IRQ_UDP		15
#define MC13783_IRQ_USB		16
#define MC13783_IRQ_ID		19
#define MC13783_IRQ_SE1		21
#define MC13783_IRQ_CKDET	22
#define MC13783_IRQ_UDM		23
#define MC13783_IRQ_1HZ		MC13XXX_IRQ_1HZ
#define MC13783_IRQ_TODA	MC13XXX_IRQ_TODA
#define MC13783_IRQ_ONOFD1	27
#define MC13783_IRQ_ONOFD2	28
#define MC13783_IRQ_ONOFD3	29
#define MC13783_IRQ_SYSRST	MC13XXX_IRQ_SYSRST
#define MC13783_IRQ_RTCRST	MC13XXX_IRQ_RTCRST
#define MC13783_IRQ_PC		MC13XXX_IRQ_PC
#define MC13783_IRQ_WARM	MC13XXX_IRQ_WARM
#define MC13783_IRQ_MEMHLD	MC13XXX_IRQ_MEMHLD
#define MC13783_IRQ_PWRRDY	35
#define MC13783_IRQ_THWARNL	MC13XXX_IRQ_THWARNL
#define MC13783_IRQ_THWARNH	MC13XXX_IRQ_THWARNH
#define MC13783_IRQ_CLK		MC13XXX_IRQ_CLK
#define MC13783_IRQ_SEMAF	39
#define MC13783_IRQ_MC2B	41
#define MC13783_IRQ_HSDET	42
#define MC13783_IRQ_HSL		43
#define MC13783_IRQ_ALSPTH	44
#define MC13783_IRQ_AHSSHORT	45
#define MC13783_NUM_IRQ		MC13XXX_NUM_IRQ

#endif /* ifndef __LINUX_MFD_MC13783_H */
Commit	Line	Data
8238addc	1	/*
57c78e35	2	* Copyright 2010 Yong Shen <yong.shen@linaro.org>
8e005935	3	* Copyright 2009-2010 Pengutronix
9e272677	4	* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
8238addc	5	*
9e272677 UKK	6	* This program is free software; you can redistribute it and/or modify it under
	7	* the terms of the GNU General Public License version 2 as published by the
	8	* Free Software Foundation.
8238addc	9	*/
9e272677 UKK	10	#ifndef __LINUX_MFD_MC13783_H
9e272677 UKK	11	#define __LINUX_MFD_MC13783_H
8238addc	12
8e005935	13	#include <linux/mfd/mc13xxx.h>
8238addc SH	14
8238addc SH	15	struct mc13783;
9e272677	16
8e005935 UKK	17	struct mc13xxx mc13783_to_mc13xxx(struct mc13783 mc13783);
	18
	19	static inline void mc13783_lock(struct mc13783 *mc13783)
	20	{
	21	mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
	22	}
	23
	24	static inline void mc13783_unlock(struct mc13783 *mc13783)
	25	{
	26	mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
	27	}
	28
	29	static inline int mc13783_reg_read(struct mc13783 *mc13783,
	30	unsigned int offset, u32 *val)
	31	{
	32	return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
	33	}
	34
	35	static inline int mc13783_reg_write(struct mc13783 *mc13783,
	36	unsigned int offset, u32 val)
	37	{
	38	return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
	39	}
	40
	41	static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
	42	unsigned int offset, u32 mask, u32 val)
	43	{
	44	return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
	45	}
	46
	47	static inline int mc13783_get_flags(struct mc13783 *mc13783)
	48	{
	49	return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
	50	}
	51
	52	static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
	53	irq_handler_t handler, const char name, void dev)
	54	{
	55	return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
	56	handler, name, dev);
	57	}
	58
	59	static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
	60	irq_handler_t handler, const char name, void dev)
	61	{
	62	return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
	63	handler, name, dev);
	64	}
	65
	66	static inline int mc13783_irq_free(struct mc13783 mc13783, int irq, void dev)
	67	{
	68	return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
	69	}
	70
	71	static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
	72	{
	73	return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
	74	}
	75
	76	static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
	77	{
	78	return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
	79	}
	80	static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
81	int enabled, int pending)
82	{
83	return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
84	irq, enabled, pending);
85	}
86
87	static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
88	{
89	return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
90	}
57205026	91
9e272677 UKK	92	#define MC13783_ADC0 43
	93	#define MC13783_ADC0_ADREFEN (1 << 10)
	94	#define MC13783_ADC0_ADREFMODE (1 << 11)
	95	#define MC13783_ADC0_TSMOD0 (1 << 12)
	96	#define MC13783_ADC0_TSMOD1 (1 << 13)
	97	#define MC13783_ADC0_TSMOD2 (1 << 14)
	98	#define MC13783_ADC0_ADINC1 (1 << 16)
	99	#define MC13783_ADC0_ADINC2 (1 << 17)
	100
	101	#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 \| \
	102	MC13783_ADC0_TSMOD1 \| \
	103	MC13783_ADC0_TSMOD2)
	104
8e005935 UKK	105	#define mc13783_regulator_init_data mc13xxx_regulator_init_data
	106	#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
	107	#define mc13783_led_platform_data mc13xxx_led_platform_data
	108	#define mc13783_leds_platform_data mc13xxx_leds_platform_data
	109
	110	#define mc13783_platform_data mc13xxx_platform_data
	111	#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
	112	#define MC13783_USE_CODEC MC13XXX_USE_CODEC
	113	#define MC13783_USE_ADC MC13XXX_USE_ADC
	114	#define MC13783_USE_RTC MC13XXX_USE_RTC
	115	#define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR
	116	#define MC13783_USE_LED MC13XXX_USE_LED
9e272677 UKK	117
	118	#define MC13783_ADC_MODE_TS 1
	119	#define MC13783_ADC_MODE_SINGLE_CHAN 2
	120	#define MC13783_ADC_MODE_MULT_CHAN 3
8238addc SH	121
	122	int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
	123	unsigned int channel, unsigned int *sample);
	124
8238addc	125
57c78e35 YS	126	#define MC13783_REG_SW1A 0
	127	#define MC13783_REG_SW1B 1
	128	#define MC13783_REG_SW2A 2
	129	#define MC13783_REG_SW2B 3
	130	#define MC13783_REG_SW3 4
	131	#define MC13783_REG_PLL 5
	132	#define MC13783_REG_VAUDIO 6
	133	#define MC13783_REG_VIOHI 7
	134	#define MC13783_REG_VIOLO 8
	135	#define MC13783_REG_VDIG 9
	136	#define MC13783_REG_VGEN 10
	137	#define MC13783_REG_VRFDIG 11
	138	#define MC13783_REG_VRFREF 12
	139	#define MC13783_REG_VRFCP 13
	140	#define MC13783_REG_VSIM 14
	141	#define MC13783_REG_VESIM 15
	142	#define MC13783_REG_VCAM 16
	143	#define MC13783_REG_VRFBG 17
	144	#define MC13783_REG_VVIB 18
	145	#define MC13783_REG_VRF1 19
	146	#define MC13783_REG_VRF2 20
	147	#define MC13783_REG_VMMC1 21
	148	#define MC13783_REG_VMMC2 22
	149	#define MC13783_REG_GPO1 23
	150	#define MC13783_REG_GPO2 24
	151	#define MC13783_REG_GPO3 25
	152	#define MC13783_REG_GPO4 26
	153	#define MC13783_REG_V1 27
	154	#define MC13783_REG_V2 28
	155	#define MC13783_REG_V3 29
	156	#define MC13783_REG_V4 30
	157	#define MC13783_REG_PWGT1SPI 31
	158	#define MC13783_REG_PWGT2SPI 32
8238addc	159
8e005935 UKK	160	#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
	161	#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
	162	#define MC13783_IRQ_TS MC13XXX_IRQ_TS
9e272677 UKK	163	#define MC13783_IRQ_WHIGH 3
9e272677 UKK	164	#define MC13783_IRQ_WLOW 4
8e005935	165	#define MC13783_IRQ_CHGDET MC13XXX_IRQ_CHGDET
9e272677	166	#define MC13783_IRQ_CHGOV 7
8e005935 UKK	167	#define MC13783_IRQ_CHGREV MC13XXX_IRQ_CHGREV
	168	#define MC13783_IRQ_CHGSHORT MC13XXX_IRQ_CHGSHORT
	169	#define MC13783_IRQ_CCCV MC13XXX_IRQ_CCCV
	170	#define MC13783_IRQ_CHGCURR MC13XXX_IRQ_CHGCURR
	171	#define MC13783_IRQ_BPON MC13XXX_IRQ_BPON
	172	#define MC13783_IRQ_LOBATL MC13XXX_IRQ_LOBATL
	173	#define MC13783_IRQ_LOBATH MC13XXX_IRQ_LOBATH
9e272677 UKK	174	#define MC13783_IRQ_UDP 15
	175	#define MC13783_IRQ_USB 16
	176	#define MC13783_IRQ_ID 19
	177	#define MC13783_IRQ_SE1 21
	178	#define MC13783_IRQ_CKDET 22
	179	#define MC13783_IRQ_UDM 23
8e005935 UKK	180	#define MC13783_IRQ_1HZ MC13XXX_IRQ_1HZ
8e005935 UKK	181	#define MC13783_IRQ_TODA MC13XXX_IRQ_TODA
9e272677 UKK	182	#define MC13783_IRQ_ONOFD1 27
	183	#define MC13783_IRQ_ONOFD2 28
	184	#define MC13783_IRQ_ONOFD3 29
8e005935 UKK	185	#define MC13783_IRQ_SYSRST MC13XXX_IRQ_SYSRST
	186	#define MC13783_IRQ_RTCRST MC13XXX_IRQ_RTCRST
	187	#define MC13783_IRQ_PC MC13XXX_IRQ_PC
	188	#define MC13783_IRQ_WARM MC13XXX_IRQ_WARM
	189	#define MC13783_IRQ_MEMHLD MC13XXX_IRQ_MEMHLD
9e272677	190	#define MC13783_IRQ_PWRRDY 35
8e005935 UKK	191	#define MC13783_IRQ_THWARNL MC13XXX_IRQ_THWARNL
	192	#define MC13783_IRQ_THWARNH MC13XXX_IRQ_THWARNH
	193	#define MC13783_IRQ_CLK MC13XXX_IRQ_CLK
9e272677 UKK	194	#define MC13783_IRQ_SEMAF 39
	195	#define MC13783_IRQ_MC2B 41
	196	#define MC13783_IRQ_HSDET 42
	197	#define MC13783_IRQ_HSL 43
	198	#define MC13783_IRQ_ALSPTH 44
	199	#define MC13783_IRQ_AHSSHORT 45
8e005935	200	#define MC13783_NUM_IRQ MC13XXX_NUM_IRQ
8238addc	201
8e005935	202	#endif /* ifndef __LINUX_MFD_MC13783_H */