Commit | Line | Data |
---|---|---|
67d16a46 WW |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
09fd8678 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
67d16a46 WW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
67d16a46 WW |
20 | */ |
21 | ||
22 | #ifndef __RTSX_PCI_H | |
23 | #define __RTSX_PCI_H | |
24 | ||
25 | #include <linux/sched.h> | |
26 | #include <linux/pci.h> | |
5947c167 | 27 | #include <linux/mfd/rtsx_common.h> |
67d16a46 WW |
28 | |
29 | #define MAX_RW_REG_CNT 1024 | |
30 | ||
67d16a46 WW |
31 | #define RTSX_HCBAR 0x00 |
32 | #define RTSX_HCBCTLR 0x04 | |
ada71f55 MC |
33 | #define STOP_CMD (0x01 << 28) |
34 | #define READ_REG_CMD 0 | |
35 | #define WRITE_REG_CMD 1 | |
36 | #define CHECK_REG_CMD 2 | |
37 | ||
67d16a46 | 38 | #define RTSX_HDBAR 0x08 |
ada71f55 MC |
39 | #define SG_INT 0x04 |
40 | #define SG_END 0x02 | |
41 | #define SG_VALID 0x01 | |
42 | #define SG_NO_OP 0x00 | |
43 | #define SG_TRANS_DATA (0x02 << 4) | |
44 | #define SG_LINK_DESC (0x03 << 4) | |
67d16a46 | 45 | #define RTSX_HDBCTLR 0x0C |
ada71f55 MC |
46 | #define SDMA_MODE 0x00 |
47 | #define ADMA_MODE (0x02 << 26) | |
48 | #define STOP_DMA (0x01 << 28) | |
49 | #define TRIG_DMA (0x01 << 31) | |
50 | ||
67d16a46 | 51 | #define RTSX_HAIMR 0x10 |
ada71f55 MC |
52 | #define HAIMR_TRANS_START (0x01 << 31) |
53 | #define HAIMR_READ 0x00 | |
54 | #define HAIMR_WRITE (0x01 << 30) | |
55 | #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) | |
56 | #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) | |
57 | #define HAIMR_TRANS_END (HAIMR_TRANS_START) | |
67d16a46 | 58 | |
ada71f55 MC |
59 | #define RTSX_BIPR 0x14 |
60 | #define CMD_DONE_INT (1 << 31) | |
61 | #define DATA_DONE_INT (1 << 30) | |
62 | #define TRANS_OK_INT (1 << 29) | |
63 | #define TRANS_FAIL_INT (1 << 28) | |
64 | #define XD_INT (1 << 27) | |
65 | #define MS_INT (1 << 26) | |
66 | #define SD_INT (1 << 25) | |
67 | #define GPIO0_INT (1 << 24) | |
68 | #define OC_INT (1 << 23) | |
69 | #define SD_WRITE_PROTECT (1 << 19) | |
70 | #define XD_EXIST (1 << 18) | |
71 | #define MS_EXIST (1 << 17) | |
72 | #define SD_EXIST (1 << 16) | |
73 | #define DELINK_INT GPIO0_INT | |
74 | #define MS_OC_INT (1 << 23) | |
75 | #define SD_OC_INT (1 << 22) | |
67d16a46 WW |
76 | |
77 | #define CARD_INT (XD_INT | MS_INT | SD_INT) | |
78 | #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) | |
79 | #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ | |
80 | CARD_INT | GPIO0_INT | OC_INT) | |
67d16a46 WW |
81 | #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) |
82 | ||
ada71f55 MC |
83 | #define RTSX_BIER 0x18 |
84 | #define CMD_DONE_INT_EN (1 << 31) | |
85 | #define DATA_DONE_INT_EN (1 << 30) | |
86 | #define TRANS_OK_INT_EN (1 << 29) | |
87 | #define TRANS_FAIL_INT_EN (1 << 28) | |
88 | #define XD_INT_EN (1 << 27) | |
89 | #define MS_INT_EN (1 << 26) | |
90 | #define SD_INT_EN (1 << 25) | |
91 | #define GPIO0_INT_EN (1 << 24) | |
92 | #define OC_INT_EN (1 << 23) | |
93 | #define DELINK_INT_EN GPIO0_INT_EN | |
94 | #define MS_OC_INT_EN (1 << 23) | |
95 | #define SD_OC_INT_EN (1 << 22) | |
96 | ||
67d16a46 WW |
97 | |
98 | /* | |
99 | * macros for easy use | |
100 | */ | |
101 | #define rtsx_pci_writel(pcr, reg, value) \ | |
102 | iowrite32(value, (pcr)->remap_addr + reg) | |
103 | #define rtsx_pci_readl(pcr, reg) \ | |
104 | ioread32((pcr)->remap_addr + reg) | |
105 | #define rtsx_pci_writew(pcr, reg, value) \ | |
106 | iowrite16(value, (pcr)->remap_addr + reg) | |
107 | #define rtsx_pci_readw(pcr, reg) \ | |
108 | ioread16((pcr)->remap_addr + reg) | |
109 | #define rtsx_pci_writeb(pcr, reg, value) \ | |
110 | iowrite8(value, (pcr)->remap_addr + reg) | |
111 | #define rtsx_pci_readb(pcr, reg) \ | |
112 | ioread8((pcr)->remap_addr + reg) | |
113 | ||
114 | #define rtsx_pci_read_config_byte(pcr, where, val) \ | |
115 | pci_read_config_byte((pcr)->pci, where, val) | |
116 | ||
117 | #define rtsx_pci_write_config_byte(pcr, where, val) \ | |
118 | pci_write_config_byte((pcr)->pci, where, val) | |
119 | ||
120 | #define rtsx_pci_read_config_dword(pcr, where, val) \ | |
121 | pci_read_config_dword((pcr)->pci, where, val) | |
122 | ||
123 | #define rtsx_pci_write_config_dword(pcr, where, val) \ | |
124 | pci_write_config_dword((pcr)->pci, where, val) | |
125 | ||
ada71f55 MC |
126 | #define STATE_TRANS_NONE 0 |
127 | #define STATE_TRANS_CMD 1 | |
128 | #define STATE_TRANS_BUF 2 | |
129 | #define STATE_TRANS_SG 3 | |
773ccdfd | 130 | |
ada71f55 MC |
131 | #define TRANS_NOT_READY 0 |
132 | #define TRANS_RESULT_OK 1 | |
133 | #define TRANS_RESULT_FAIL 2 | |
134 | #define TRANS_NO_DEVICE 3 | |
67d16a46 | 135 | |
ada71f55 MC |
136 | #define RTSX_RESV_BUF_LEN 4096 |
137 | #define HOST_CMDS_BUF_LEN 1024 | |
138 | #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) | |
139 | #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8) | |
140 | #define MAX_SG_ITEM_LEN 0x80000 | |
141 | #define HOST_TO_DEVICE 0 | |
142 | #define DEVICE_TO_HOST 1 | |
143 | ||
144 | #define OUTPUT_3V3 0 | |
145 | #define OUTPUT_1V8 1 | |
67d16a46 | 146 | |
ada71f55 MC |
147 | #define RTSX_PHASE_MAX 32 |
148 | #define RX_TUNING_CNT 3 | |
5947c167 | 149 | |
67d16a46 | 150 | #define MS_CFG 0xFD40 |
ada71f55 MC |
151 | #define SAMPLE_TIME_RISING 0x00 |
152 | #define SAMPLE_TIME_FALLING 0x80 | |
153 | #define PUSH_TIME_DEFAULT 0x00 | |
154 | #define PUSH_TIME_ODD 0x40 | |
155 | #define NO_EXTEND_TOGGLE 0x00 | |
156 | #define EXTEND_TOGGLE_CHK 0x20 | |
157 | #define MS_BUS_WIDTH_1 0x00 | |
158 | #define MS_BUS_WIDTH_4 0x10 | |
159 | #define MS_BUS_WIDTH_8 0x18 | |
160 | #define MS_2K_SECTOR_MODE 0x04 | |
161 | #define MS_512_SECTOR_MODE 0x00 | |
162 | #define MS_TOGGLE_TIMEOUT_EN 0x00 | |
163 | #define MS_TOGGLE_TIMEOUT_DISEN 0x01 | |
164 | #define MS_NO_CHECK_INT 0x02 | |
67d16a46 WW |
165 | #define MS_TPC 0xFD41 |
166 | #define MS_TRANS_CFG 0xFD42 | |
ada71f55 MC |
167 | #define WAIT_INT 0x80 |
168 | #define NO_WAIT_INT 0x00 | |
169 | #define NO_AUTO_READ_INT_REG 0x00 | |
170 | #define AUTO_READ_INT_REG 0x40 | |
171 | #define MS_CRC16_ERR 0x20 | |
172 | #define MS_RDY_TIMEOUT 0x10 | |
173 | #define MS_INT_CMDNK 0x08 | |
174 | #define MS_INT_BREQ 0x04 | |
175 | #define MS_INT_ERR 0x02 | |
176 | #define MS_INT_CED 0x01 | |
67d16a46 | 177 | #define MS_TRANSFER 0xFD43 |
ada71f55 MC |
178 | #define MS_TRANSFER_START 0x80 |
179 | #define MS_TRANSFER_END 0x40 | |
180 | #define MS_TRANSFER_ERR 0x20 | |
181 | #define MS_BS_STATE 0x10 | |
182 | #define MS_TM_READ_BYTES 0x00 | |
183 | #define MS_TM_NORMAL_READ 0x01 | |
184 | #define MS_TM_WRITE_BYTES 0x04 | |
185 | #define MS_TM_NORMAL_WRITE 0x05 | |
186 | #define MS_TM_AUTO_READ 0x08 | |
187 | #define MS_TM_AUTO_WRITE 0x0C | |
67d16a46 WW |
188 | #define MS_INT_REG 0xFD44 |
189 | #define MS_BYTE_CNT 0xFD45 | |
190 | #define MS_SECTOR_CNT_L 0xFD46 | |
191 | #define MS_SECTOR_CNT_H 0xFD47 | |
192 | #define MS_DBUS_H 0xFD48 | |
193 | ||
194 | #define SD_CFG1 0xFDA0 | |
ada71f55 MC |
195 | #define SD_CLK_DIVIDE_0 0x00 |
196 | #define SD_CLK_DIVIDE_256 0xC0 | |
197 | #define SD_CLK_DIVIDE_128 0x80 | |
198 | #define SD_BUS_WIDTH_1BIT 0x00 | |
199 | #define SD_BUS_WIDTH_4BIT 0x01 | |
200 | #define SD_BUS_WIDTH_8BIT 0x02 | |
201 | #define SD_ASYNC_FIFO_NOT_RST 0x10 | |
202 | #define SD_20_MODE 0x00 | |
203 | #define SD_DDR_MODE 0x04 | |
204 | #define SD_30_MODE 0x08 | |
205 | #define SD_CLK_DIVIDE_MASK 0xC0 | |
67d16a46 | 206 | #define SD_CFG2 0xFDA1 |
ada71f55 MC |
207 | #define SD_CALCULATE_CRC7 0x00 |
208 | #define SD_NO_CALCULATE_CRC7 0x80 | |
209 | #define SD_CHECK_CRC16 0x00 | |
210 | #define SD_NO_CHECK_CRC16 0x40 | |
211 | #define SD_NO_CHECK_WAIT_CRC_TO 0x20 | |
212 | #define SD_WAIT_BUSY_END 0x08 | |
213 | #define SD_NO_WAIT_BUSY_END 0x00 | |
214 | #define SD_CHECK_CRC7 0x00 | |
215 | #define SD_NO_CHECK_CRC7 0x04 | |
216 | #define SD_RSP_LEN_0 0x00 | |
217 | #define SD_RSP_LEN_6 0x01 | |
218 | #define SD_RSP_LEN_17 0x02 | |
219 | #define SD_RSP_TYPE_R0 0x04 | |
220 | #define SD_RSP_TYPE_R1 0x01 | |
221 | #define SD_RSP_TYPE_R1b 0x09 | |
222 | #define SD_RSP_TYPE_R2 0x02 | |
223 | #define SD_RSP_TYPE_R3 0x05 | |
224 | #define SD_RSP_TYPE_R4 0x05 | |
225 | #define SD_RSP_TYPE_R5 0x01 | |
226 | #define SD_RSP_TYPE_R6 0x01 | |
227 | #define SD_RSP_TYPE_R7 0x01 | |
67d16a46 | 228 | #define SD_CFG3 0xFDA2 |
ada71f55 MC |
229 | #define SD_RSP_80CLK_TIMEOUT_EN 0x01 |
230 | ||
67d16a46 | 231 | #define SD_STAT1 0xFDA3 |
ada71f55 MC |
232 | #define SD_CRC7_ERR 0x80 |
233 | #define SD_CRC16_ERR 0x40 | |
234 | #define SD_CRC_WRITE_ERR 0x20 | |
235 | #define SD_CRC_WRITE_ERR_MASK 0x1C | |
236 | #define GET_CRC_TIME_OUT 0x02 | |
237 | #define SD_TUNING_COMPARE_ERR 0x01 | |
67d16a46 | 238 | #define SD_STAT2 0xFDA4 |
ada71f55 MC |
239 | #define SD_RSP_80CLK_TIMEOUT 0x01 |
240 | ||
67d16a46 | 241 | #define SD_BUS_STAT 0xFDA5 |
ada71f55 MC |
242 | #define SD_CLK_TOGGLE_EN 0x80 |
243 | #define SD_CLK_FORCE_STOP 0x40 | |
244 | #define SD_DAT3_STATUS 0x10 | |
245 | #define SD_DAT2_STATUS 0x08 | |
246 | #define SD_DAT1_STATUS 0x04 | |
247 | #define SD_DAT0_STATUS 0x02 | |
248 | #define SD_CMD_STATUS 0x01 | |
67d16a46 | 249 | #define SD_PAD_CTL 0xFDA6 |
ada71f55 MC |
250 | #define SD_IO_USING_1V8 0x80 |
251 | #define SD_IO_USING_3V3 0x7F | |
252 | #define TYPE_A_DRIVING 0x00 | |
253 | #define TYPE_B_DRIVING 0x01 | |
254 | #define TYPE_C_DRIVING 0x02 | |
255 | #define TYPE_D_DRIVING 0x03 | |
67d16a46 | 256 | #define SD_SAMPLE_POINT_CTL 0xFDA7 |
ada71f55 MC |
257 | #define DDR_FIX_RX_DAT 0x00 |
258 | #define DDR_VAR_RX_DAT 0x80 | |
259 | #define DDR_FIX_RX_DAT_EDGE 0x00 | |
260 | #define DDR_FIX_RX_DAT_14_DELAY 0x40 | |
261 | #define DDR_FIX_RX_CMD 0x00 | |
262 | #define DDR_VAR_RX_CMD 0x20 | |
263 | #define DDR_FIX_RX_CMD_POS_EDGE 0x00 | |
264 | #define DDR_FIX_RX_CMD_14_DELAY 0x10 | |
265 | #define SD20_RX_POS_EDGE 0x00 | |
266 | #define SD20_RX_14_DELAY 0x08 | |
267 | #define SD20_RX_SEL_MASK 0x08 | |
67d16a46 | 268 | #define SD_PUSH_POINT_CTL 0xFDA8 |
ada71f55 MC |
269 | #define DDR_FIX_TX_CMD_DAT 0x00 |
270 | #define DDR_VAR_TX_CMD_DAT 0x80 | |
271 | #define DDR_FIX_TX_DAT_14_TSU 0x00 | |
272 | #define DDR_FIX_TX_DAT_12_TSU 0x40 | |
273 | #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 | |
274 | #define DDR_FIX_TX_CMD_14_AHEAD 0x20 | |
275 | #define SD20_TX_NEG_EDGE 0x00 | |
276 | #define SD20_TX_14_AHEAD 0x10 | |
277 | #define SD20_TX_SEL_MASK 0x10 | |
278 | #define DDR_VAR_SDCLK_POL_SWAP 0x01 | |
67d16a46 | 279 | #define SD_CMD0 0xFDA9 |
a3b63979 | 280 | #define SD_CMD_START 0x40 |
67d16a46 WW |
281 | #define SD_CMD1 0xFDAA |
282 | #define SD_CMD2 0xFDAB | |
283 | #define SD_CMD3 0xFDAC | |
284 | #define SD_CMD4 0xFDAD | |
285 | #define SD_CMD5 0xFDAE | |
286 | #define SD_BYTE_CNT_L 0xFDAF | |
287 | #define SD_BYTE_CNT_H 0xFDB0 | |
288 | #define SD_BLOCK_CNT_L 0xFDB1 | |
289 | #define SD_BLOCK_CNT_H 0xFDB2 | |
290 | #define SD_TRANSFER 0xFDB3 | |
ada71f55 MC |
291 | #define SD_TRANSFER_START 0x80 |
292 | #define SD_TRANSFER_END 0x40 | |
293 | #define SD_STAT_IDLE 0x20 | |
294 | #define SD_TRANSFER_ERR 0x10 | |
295 | #define SD_TM_NORMAL_WRITE 0x00 | |
296 | #define SD_TM_AUTO_WRITE_3 0x01 | |
297 | #define SD_TM_AUTO_WRITE_4 0x02 | |
298 | #define SD_TM_AUTO_READ_3 0x05 | |
299 | #define SD_TM_AUTO_READ_4 0x06 | |
300 | #define SD_TM_CMD_RSP 0x08 | |
301 | #define SD_TM_AUTO_WRITE_1 0x09 | |
302 | #define SD_TM_AUTO_WRITE_2 0x0A | |
303 | #define SD_TM_NORMAL_READ 0x0C | |
304 | #define SD_TM_AUTO_READ_1 0x0D | |
305 | #define SD_TM_AUTO_READ_2 0x0E | |
306 | #define SD_TM_AUTO_TUNING 0x0F | |
67d16a46 | 307 | #define SD_CMD_STATE 0xFDB5 |
ada71f55 MC |
308 | #define SD_CMD_IDLE 0x80 |
309 | ||
67d16a46 | 310 | #define SD_DATA_STATE 0xFDB6 |
ada71f55 | 311 | #define SD_DATA_IDLE 0x80 |
67d16a46 WW |
312 | |
313 | #define SRCTL 0xFC13 | |
314 | ||
84f00b1b | 315 | #define DCM_DRP_CTL 0xFC23 |
ada71f55 MC |
316 | #define DCM_RESET 0x08 |
317 | #define DCM_LOCKED 0x04 | |
318 | #define DCM_208M 0x00 | |
319 | #define DCM_TX 0x01 | |
320 | #define DCM_RX 0x02 | |
84f00b1b | 321 | #define DCM_DRP_TRIG 0xFC24 |
ada71f55 MC |
322 | #define DRP_START 0x80 |
323 | #define DRP_DONE 0x40 | |
84f00b1b | 324 | #define DCM_DRP_CFG 0xFC25 |
ada71f55 MC |
325 | #define DRP_WRITE 0x80 |
326 | #define DRP_READ 0x00 | |
327 | #define DCM_WRITE_ADDRESS_50 0x50 | |
328 | #define DCM_WRITE_ADDRESS_51 0x51 | |
329 | #define DCM_READ_ADDRESS_00 0x00 | |
330 | #define DCM_READ_ADDRESS_51 0x51 | |
84f00b1b MC |
331 | #define DCM_DRP_WR_DATA_L 0xFC26 |
332 | #define DCM_DRP_WR_DATA_H 0xFC27 | |
333 | #define DCM_DRP_RD_DATA_L 0xFC28 | |
334 | #define DCM_DRP_RD_DATA_H 0xFC29 | |
67d16a46 WW |
335 | #define SD_VPCLK0_CTL 0xFC2A |
336 | #define SD_VPCLK1_CTL 0xFC2B | |
337 | #define SD_DCMPS0_CTL 0xFC2C | |
338 | #define SD_DCMPS1_CTL 0xFC2D | |
339 | #define SD_VPTX_CTL SD_VPCLK0_CTL | |
340 | #define SD_VPRX_CTL SD_VPCLK1_CTL | |
ada71f55 MC |
341 | #define PHASE_CHANGE 0x80 |
342 | #define PHASE_NOT_RESET 0x40 | |
67d16a46 WW |
343 | #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL |
344 | #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL | |
ada71f55 MC |
345 | #define DCMPS_CHANGE 0x80 |
346 | #define DCMPS_CHANGE_DONE 0x40 | |
347 | #define DCMPS_ERROR 0x20 | |
348 | #define DCMPS_CURRENT_PHASE 0x1F | |
67d16a46 | 349 | #define CARD_CLK_SOURCE 0xFC2E |
ada71f55 MC |
350 | #define CRC_FIX_CLK (0x00 << 0) |
351 | #define CRC_VAR_CLK0 (0x01 << 0) | |
352 | #define CRC_VAR_CLK1 (0x02 << 0) | |
353 | #define SD30_FIX_CLK (0x00 << 2) | |
354 | #define SD30_VAR_CLK0 (0x01 << 2) | |
355 | #define SD30_VAR_CLK1 (0x02 << 2) | |
356 | #define SAMPLE_FIX_CLK (0x00 << 4) | |
357 | #define SAMPLE_VAR_CLK0 (0x01 << 4) | |
358 | #define SAMPLE_VAR_CLK1 (0x02 << 4) | |
67d16a46 | 359 | #define CARD_PWR_CTL 0xFD50 |
ada71f55 MC |
360 | #define PMOS_STRG_MASK 0x10 |
361 | #define PMOS_STRG_800mA 0x10 | |
362 | #define PMOS_STRG_400mA 0x00 | |
363 | #define SD_POWER_OFF 0x03 | |
364 | #define SD_PARTIAL_POWER_ON 0x01 | |
365 | #define SD_POWER_ON 0x00 | |
366 | #define SD_POWER_MASK 0x03 | |
367 | #define MS_POWER_OFF 0x0C | |
368 | #define MS_PARTIAL_POWER_ON 0x04 | |
369 | #define MS_POWER_ON 0x00 | |
370 | #define MS_POWER_MASK 0x0C | |
371 | #define BPP_POWER_OFF 0x0F | |
372 | #define BPP_POWER_5_PERCENT_ON 0x0E | |
373 | #define BPP_POWER_10_PERCENT_ON 0x0C | |
374 | #define BPP_POWER_15_PERCENT_ON 0x08 | |
375 | #define BPP_POWER_ON 0x00 | |
376 | #define BPP_POWER_MASK 0x0F | |
377 | #define SD_VCC_PARTIAL_POWER_ON 0x02 | |
378 | #define SD_VCC_POWER_ON 0x00 | |
67d16a46 | 379 | #define CARD_CLK_SWITCH 0xFD51 |
9032eabd | 380 | #define RTL8411B_PACKAGE_MODE 0xFD51 |
67d16a46 | 381 | #define CARD_SHARE_MODE 0xFD52 |
ada71f55 MC |
382 | #define CARD_SHARE_MASK 0x0F |
383 | #define CARD_SHARE_MULTI_LUN 0x00 | |
384 | #define CARD_SHARE_NORMAL 0x00 | |
385 | #define CARD_SHARE_48_SD 0x04 | |
386 | #define CARD_SHARE_48_MS 0x08 | |
387 | #define CARD_SHARE_BAROSSA_SD 0x01 | |
388 | #define CARD_SHARE_BAROSSA_MS 0x02 | |
67d16a46 | 389 | #define CARD_DRIVE_SEL 0xFD53 |
ada71f55 MC |
390 | #define MS_DRIVE_8mA (0x01 << 6) |
391 | #define MMC_DRIVE_8mA (0x01 << 4) | |
392 | #define XD_DRIVE_8mA (0x01 << 2) | |
393 | #define GPIO_DRIVE_8mA 0x01 | |
394 | #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
395 | XD_DRIVE_8mA | GPIO_DRIVE_8mA) | |
396 | #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
397 | XD_DRIVE_8mA) | |
398 | #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA) | |
399 | ||
67d16a46 | 400 | #define CARD_STOP 0xFD54 |
ada71f55 MC |
401 | #define SPI_STOP 0x01 |
402 | #define XD_STOP 0x02 | |
403 | #define SD_STOP 0x04 | |
404 | #define MS_STOP 0x08 | |
405 | #define SPI_CLR_ERR 0x10 | |
406 | #define XD_CLR_ERR 0x20 | |
407 | #define SD_CLR_ERR 0x40 | |
408 | #define MS_CLR_ERR 0x80 | |
67d16a46 | 409 | #define CARD_OE 0xFD55 |
ada71f55 MC |
410 | #define SD_OUTPUT_EN 0x04 |
411 | #define MS_OUTPUT_EN 0x08 | |
67d16a46 WW |
412 | #define CARD_AUTO_BLINK 0xFD56 |
413 | #define CARD_GPIO_DIR 0xFD57 | |
414 | #define CARD_GPIO 0xFD58 | |
415 | #define CARD_DATA_SOURCE 0xFD5B | |
ada71f55 MC |
416 | #define PINGPONG_BUFFER 0x01 |
417 | #define RING_BUFFER 0x00 | |
e1237932 | 418 | #define SD30_CLK_DRIVE_SEL 0xFD5A |
ada71f55 MC |
419 | #define DRIVER_TYPE_A 0x05 |
420 | #define DRIVER_TYPE_B 0x03 | |
421 | #define DRIVER_TYPE_C 0x02 | |
422 | #define DRIVER_TYPE_D 0x01 | |
67d16a46 | 423 | #define CARD_SELECT 0xFD5C |
ada71f55 MC |
424 | #define SD_MOD_SEL 2 |
425 | #define MS_MOD_SEL 3 | |
67d16a46 | 426 | #define SD30_DRIVE_SEL 0xFD5E |
ada71f55 MC |
427 | #define CFG_DRIVER_TYPE_A 0x02 |
428 | #define CFG_DRIVER_TYPE_B 0x03 | |
429 | #define CFG_DRIVER_TYPE_C 0x01 | |
430 | #define CFG_DRIVER_TYPE_D 0x00 | |
e1237932 RT |
431 | #define SD30_CMD_DRIVE_SEL 0xFD5E |
432 | #define SD30_DAT_DRIVE_SEL 0xFD5F | |
67d16a46 | 433 | #define CARD_CLK_EN 0xFD69 |
ada71f55 MC |
434 | #define SD_CLK_EN 0x04 |
435 | #define MS_CLK_EN 0x08 | |
67d16a46 WW |
436 | #define SDIO_CTRL 0xFD6B |
437 | #define CD_PAD_CTL 0xFD73 | |
ada71f55 MC |
438 | #define CD_DISABLE_MASK 0x07 |
439 | #define MS_CD_DISABLE 0x04 | |
440 | #define SD_CD_DISABLE 0x02 | |
441 | #define XD_CD_DISABLE 0x01 | |
442 | #define CD_DISABLE 0x07 | |
443 | #define CD_ENABLE 0x00 | |
444 | #define MS_CD_EN_ONLY 0x03 | |
445 | #define SD_CD_EN_ONLY 0x05 | |
446 | #define XD_CD_EN_ONLY 0x06 | |
447 | #define FORCE_CD_LOW_MASK 0x38 | |
448 | #define FORCE_CD_XD_LOW 0x08 | |
449 | #define FORCE_CD_SD_LOW 0x10 | |
450 | #define FORCE_CD_MS_LOW 0x20 | |
451 | #define CD_AUTO_DISABLE 0x40 | |
67d16a46 | 452 | #define FPDCTL 0xFC00 |
ada71f55 MC |
453 | #define SSC_POWER_DOWN 0x01 |
454 | #define SD_OC_POWER_DOWN 0x02 | |
455 | #define ALL_POWER_DOWN 0x07 | |
456 | #define OC_POWER_DOWN 0x06 | |
67d16a46 WW |
457 | #define PDINFO 0xFC01 |
458 | ||
459 | #define CLK_CTL 0xFC02 | |
ada71f55 MC |
460 | #define CHANGE_CLK 0x01 |
461 | #define CLK_LOW_FREQ 0x01 | |
462 | ||
67d16a46 | 463 | #define CLK_DIV 0xFC03 |
ada71f55 MC |
464 | #define CLK_DIV_1 0x01 |
465 | #define CLK_DIV_2 0x02 | |
466 | #define CLK_DIV_4 0x03 | |
467 | #define CLK_DIV_8 0x04 | |
67d16a46 WW |
468 | #define CLK_SEL 0xFC04 |
469 | ||
470 | #define SSC_DIV_N_0 0xFC0F | |
471 | #define SSC_DIV_N_1 0xFC10 | |
472 | #define SSC_CTL1 0xFC11 | |
ada71f55 MC |
473 | #define SSC_RSTB 0x80 |
474 | #define SSC_8X_EN 0x40 | |
475 | #define SSC_FIX_FRAC 0x20 | |
476 | #define SSC_SEL_1M 0x00 | |
477 | #define SSC_SEL_2M 0x08 | |
478 | #define SSC_SEL_4M 0x10 | |
479 | #define SSC_SEL_8M 0x18 | |
67d16a46 | 480 | #define SSC_CTL2 0xFC12 |
ada71f55 MC |
481 | #define SSC_DEPTH_MASK 0x07 |
482 | #define SSC_DEPTH_DISALBE 0x00 | |
483 | #define SSC_DEPTH_4M 0x01 | |
484 | #define SSC_DEPTH_2M 0x02 | |
485 | #define SSC_DEPTH_1M 0x03 | |
486 | #define SSC_DEPTH_500K 0x04 | |
487 | #define SSC_DEPTH_250K 0x05 | |
67d16a46 WW |
488 | #define RCCTL 0xFC14 |
489 | ||
490 | #define FPGA_PULL_CTL 0xFC1D | |
491 | #define OLT_LED_CTL 0xFC1E | |
492 | #define GPIO_CTL 0xFC1F | |
493 | ||
494 | #define LDO_CTL 0xFC1E | |
ada71f55 MC |
495 | #define BPP_ASIC_1V7 0x00 |
496 | #define BPP_ASIC_1V8 0x01 | |
497 | #define BPP_ASIC_1V9 0x02 | |
498 | #define BPP_ASIC_2V0 0x03 | |
499 | #define BPP_ASIC_2V7 0x04 | |
500 | #define BPP_ASIC_2V8 0x05 | |
501 | #define BPP_ASIC_3V2 0x06 | |
502 | #define BPP_ASIC_3V3 0x07 | |
503 | #define BPP_REG_TUNED18 0x07 | |
504 | #define BPP_TUNED18_SHIFT_8402 5 | |
505 | #define BPP_TUNED18_SHIFT_8411 4 | |
506 | #define BPP_PAD_MASK 0x04 | |
507 | #define BPP_PAD_3V3 0x04 | |
508 | #define BPP_PAD_1V8 0x00 | |
509 | #define BPP_LDO_POWB 0x03 | |
510 | #define BPP_LDO_ON 0x00 | |
511 | #define BPP_LDO_SUSPEND 0x02 | |
512 | #define BPP_LDO_OFF 0x03 | |
67d16a46 WW |
513 | #define SYS_VER 0xFC32 |
514 | ||
515 | #define CARD_PULL_CTL1 0xFD60 | |
516 | #define CARD_PULL_CTL2 0xFD61 | |
517 | #define CARD_PULL_CTL3 0xFD62 | |
518 | #define CARD_PULL_CTL4 0xFD63 | |
519 | #define CARD_PULL_CTL5 0xFD64 | |
520 | #define CARD_PULL_CTL6 0xFD65 | |
521 | ||
522 | /* PCI Express Related Registers */ | |
523 | #define IRQEN0 0xFE20 | |
524 | #define IRQSTAT0 0xFE21 | |
ada71f55 MC |
525 | #define DMA_DONE_INT 0x80 |
526 | #define SUSPEND_INT 0x40 | |
527 | #define LINK_RDY_INT 0x20 | |
528 | #define LINK_DOWN_INT 0x10 | |
67d16a46 WW |
529 | #define IRQEN1 0xFE22 |
530 | #define IRQSTAT1 0xFE23 | |
531 | #define TLPRIEN 0xFE24 | |
532 | #define TLPRISTAT 0xFE25 | |
533 | #define TLPTIEN 0xFE26 | |
534 | #define TLPTISTAT 0xFE27 | |
535 | #define DMATC0 0xFE28 | |
536 | #define DMATC1 0xFE29 | |
537 | #define DMATC2 0xFE2A | |
538 | #define DMATC3 0xFE2B | |
539 | #define DMACTL 0xFE2C | |
ada71f55 MC |
540 | #define DMA_RST 0x80 |
541 | #define DMA_BUSY 0x04 | |
542 | #define DMA_DIR_TO_CARD 0x00 | |
543 | #define DMA_DIR_FROM_CARD 0x02 | |
544 | #define DMA_EN 0x01 | |
545 | #define DMA_128 (0 << 4) | |
546 | #define DMA_256 (1 << 4) | |
547 | #define DMA_512 (2 << 4) | |
548 | #define DMA_1024 (3 << 4) | |
549 | #define DMA_PACK_SIZE_MASK 0x30 | |
67d16a46 WW |
550 | #define BCTL 0xFE2D |
551 | #define RBBC0 0xFE2E | |
552 | #define RBBC1 0xFE2F | |
553 | #define RBDAT 0xFE30 | |
554 | #define RBCTL 0xFE34 | |
555 | #define CFGADDR0 0xFE35 | |
556 | #define CFGADDR1 0xFE36 | |
557 | #define CFGDATA0 0xFE37 | |
558 | #define CFGDATA1 0xFE38 | |
559 | #define CFGDATA2 0xFE39 | |
560 | #define CFGDATA3 0xFE3A | |
561 | #define CFGRWCTL 0xFE3B | |
562 | #define PHYRWCTL 0xFE3C | |
563 | #define PHYDATA0 0xFE3D | |
564 | #define PHYDATA1 0xFE3E | |
565 | #define PHYADDR 0xFE3F | |
566 | #define MSGRXDATA0 0xFE40 | |
567 | #define MSGRXDATA1 0xFE41 | |
568 | #define MSGRXDATA2 0xFE42 | |
569 | #define MSGRXDATA3 0xFE43 | |
570 | #define MSGTXDATA0 0xFE44 | |
571 | #define MSGTXDATA1 0xFE45 | |
572 | #define MSGTXDATA2 0xFE46 | |
573 | #define MSGTXDATA3 0xFE47 | |
574 | #define MSGTXCTL 0xFE48 | |
e1237932 RT |
575 | #define LTR_CTL 0xFE4A |
576 | #define OBFF_CFG 0xFE4C | |
67d16a46 WW |
577 | |
578 | #define CDRESUMECTL 0xFE52 | |
579 | #define WAKE_SEL_CTL 0xFE54 | |
663c425f MC |
580 | #define PCLK_CTL 0xFE55 |
581 | #define PCLK_MODE_SEL 0x20 | |
67d16a46 | 582 | #define PME_FORCE_CTL 0xFE56 |
663c425f | 583 | |
67d16a46 | 584 | #define ASPM_FORCE_CTL 0xFE57 |
663c425f MC |
585 | #define FORCE_ASPM_CTL0 0x10 |
586 | #define FORCE_ASPM_VAL_MASK 0x03 | |
587 | #define FORCE_ASPM_L1_EN 0x02 | |
588 | #define FORCE_ASPM_L0_EN 0x01 | |
589 | #define FORCE_ASPM_NO_ASPM 0x00 | |
67d16a46 | 590 | #define PM_CLK_FORCE_CTL 0xFE58 |
0ccc0065 | 591 | #define FUNC_FORCE_CTL 0xFE59 |
ce6a5acc | 592 | #define FUNC_FORCE_UPME_XMT_DBG 0x02 |
67d16a46 WW |
593 | #define PERST_GLITCH_WIDTH 0xFE5C |
594 | #define CHANGE_LINK_STATE 0xFE5B | |
595 | #define RESET_LOAD_REG 0xFE5E | |
596 | #define EFUSE_CONTENT 0xFE5F | |
597 | #define HOST_SLEEP_STATE 0xFE60 | |
ada71f55 MC |
598 | #define HOST_ENTER_S1 1 |
599 | #define HOST_ENTER_S3 2 | |
600 | ||
67d16a46 | 601 | #define SDIO_CFG 0xFE70 |
663c425f MC |
602 | #define PM_EVENT_DEBUG 0xFE71 |
603 | #define PME_DEBUG_0 0x08 | |
67d16a46 WW |
604 | #define NFTS_TX_CTRL 0xFE72 |
605 | ||
606 | #define PWR_GATE_CTRL 0xFE75 | |
ada71f55 MC |
607 | #define PWR_GATE_EN 0x01 |
608 | #define LDO3318_PWR_MASK 0x06 | |
609 | #define LDO_ON 0x00 | |
610 | #define LDO_SUSPEND 0x04 | |
611 | #define LDO_OFF 0x06 | |
67d16a46 WW |
612 | #define PWD_SUSPEND_EN 0xFE76 |
613 | #define LDO_PWR_SEL 0xFE78 | |
614 | ||
663c425f MC |
615 | #define L1SUB_CONFIG1 0xFE8D |
616 | #define L1SUB_CONFIG2 0xFE8E | |
617 | #define L1SUB_AUTO_CFG 0x02 | |
618 | #define L1SUB_CONFIG3 0xFE8F | |
619 | ||
67d16a46 WW |
620 | #define DUMMY_REG_RESET_0 0xFE90 |
621 | ||
773ccdfd | 622 | #define AUTOLOAD_CFG_BASE 0xFF00 |
9e33ce79 | 623 | #define PETXCFG 0xFF03 |
773ccdfd | 624 | |
5947c167 | 625 | #define PM_CTRL1 0xFF44 |
663c425f MC |
626 | #define CD_RESUME_EN_MASK 0xF0 |
627 | ||
5947c167 WW |
628 | #define PM_CTRL2 0xFF45 |
629 | #define PM_CTRL3 0xFF46 | |
5cb5d961 MC |
630 | #define SDIO_SEND_PME_EN 0x80 |
631 | #define FORCE_RC_MODE_ON 0x40 | |
632 | #define FORCE_RX50_LINK_ON 0x20 | |
633 | #define D3_DELINK_MODE_EN 0x10 | |
634 | #define USE_PESRTB_CTL_DELINK 0x08 | |
635 | #define DELAY_PIN_WAKE 0x04 | |
636 | #define RESET_PIN_WAKE 0x02 | |
637 | #define PM_WAKE_EN 0x01 | |
5947c167 WW |
638 | #define PM_CTRL4 0xFF47 |
639 | ||
67d16a46 WW |
640 | /* Memory mapping */ |
641 | #define SRAM_BASE 0xE600 | |
642 | #define RBUF_BASE 0xF400 | |
643 | #define PPBUF_BASE1 0xF800 | |
644 | #define PPBUF_BASE2 0xFA00 | |
645 | #define IMAGE_FLAG_ADDR0 0xCE80 | |
646 | #define IMAGE_FLAG_ADDR1 0xCE81 | |
647 | ||
663c425f MC |
648 | #define RREF_CFG 0xFF6C |
649 | #define RREF_VBGSEL_MASK 0x38 | |
650 | #define RREF_VBGSEL_1V25 0x28 | |
651 | ||
652 | #define OOBS_CONFIG 0xFF6E | |
653 | #define OOBS_AUTOK_DIS 0x80 | |
654 | #define OOBS_VAL_MASK 0x1F | |
655 | ||
656 | #define LDO_DV18_CFG 0xFF70 | |
657 | #define LDO_DV18_SR_MASK 0xC0 | |
658 | #define LDO_DV18_SR_DF 0x40 | |
659 | ||
660 | #define LDO_CONFIG2 0xFF71 | |
661 | #define LDO_D3318_MASK 0x07 | |
662 | #define LDO_D3318_33V 0x07 | |
663 | #define LDO_D3318_18V 0x02 | |
664 | ||
665 | #define LDO_VCC_CFG0 0xFF72 | |
666 | #define LDO_VCC_LMTVTH_MASK 0x30 | |
667 | #define LDO_VCC_LMTVTH_2A 0x10 | |
668 | ||
669 | #define LDO_VCC_CFG1 0xFF73 | |
670 | #define LDO_VCC_REF_TUNE_MASK 0x30 | |
671 | #define LDO_VCC_REF_1V2 0x20 | |
672 | #define LDO_VCC_TUNE_MASK 0x07 | |
673 | #define LDO_VCC_1V8 0x04 | |
674 | #define LDO_VCC_3V3 0x07 | |
675 | #define LDO_VCC_LMT_EN 0x08 | |
676 | ||
677 | #define LDO_VIO_CFG 0xFF75 | |
678 | #define LDO_VIO_SR_MASK 0xC0 | |
679 | #define LDO_VIO_SR_DF 0x40 | |
680 | #define LDO_VIO_REF_TUNE_MASK 0x30 | |
681 | #define LDO_VIO_REF_1V2 0x20 | |
682 | #define LDO_VIO_TUNE_MASK 0x07 | |
683 | #define LDO_VIO_1V7 0x03 | |
684 | #define LDO_VIO_1V8 0x04 | |
685 | #define LDO_VIO_3V3 0x07 | |
686 | ||
687 | #define LDO_DV12S_CFG 0xFF76 | |
688 | #define LDO_REF12_TUNE_MASK 0x18 | |
689 | #define LDO_REF12_TUNE_DF 0x10 | |
690 | #define LDO_D12_TUNE_MASK 0x07 | |
691 | #define LDO_D12_TUNE_DF 0x04 | |
692 | ||
693 | #define LDO_AV12S_CFG 0xFF77 | |
694 | #define LDO_AV12S_TUNE_MASK 0x07 | |
695 | #define LDO_AV12S_TUNE_DF 0x04 | |
696 | ||
697 | #define SD40_LDO_CTL1 0xFE7D | |
698 | #define SD40_VIO_TUNE_MASK 0x70 | |
699 | #define SD40_VIO_TUNE_1V7 0x30 | |
700 | #define SD_VIO_LDO_1V8 0x40 | |
701 | #define SD_VIO_LDO_3V3 0x70 | |
702 | ||
4c4b8c10 WW |
703 | /* Phy register */ |
704 | #define PHY_PCR 0x00 | |
b0385381 MC |
705 | #define PHY_PCR_FORCE_CODE 0xB000 |
706 | #define PHY_PCR_OOBS_CALI_50 0x0800 | |
707 | #define PHY_PCR_OOBS_VCM_08 0x0200 | |
708 | #define PHY_PCR_OOBS_SEN_90 0x0040 | |
709 | #define PHY_PCR_RSSI_EN 0x0002 | |
710 | #define PHY_PCR_RX10K 0x0001 | |
711 | ||
4c4b8c10 WW |
712 | #define PHY_RCR0 0x01 |
713 | #define PHY_RCR1 0x02 | |
b0385381 MC |
714 | #define PHY_RCR1_ADP_TIME_4 0x0400 |
715 | #define PHY_RCR1_VCO_COARSE 0x001F | |
ce6a5acc | 716 | #define PHY_RCR1_INIT_27S 0x0A1F |
663c425f MC |
717 | #define PHY_SSCCR2 0x02 |
718 | #define PHY_SSCCR2_PLL_NCODE 0x0A00 | |
719 | #define PHY_SSCCR2_TIME0 0x001C | |
720 | #define PHY_SSCCR2_TIME2_WIDTH 0x0003 | |
b0385381 | 721 | |
4c4b8c10 | 722 | #define PHY_RCR2 0x03 |
b0385381 MC |
723 | #define PHY_RCR2_EMPHASE_EN 0x8000 |
724 | #define PHY_RCR2_NADJR 0x4000 | |
725 | #define PHY_RCR2_CDR_SR_2 0x0100 | |
726 | #define PHY_RCR2_FREQSEL_12 0x0040 | |
727 | #define PHY_RCR2_CDR_SC_12P 0x0010 | |
728 | #define PHY_RCR2_CALIB_LATE 0x0002 | |
ce6a5acc | 729 | #define PHY_RCR2_INIT_27S 0xC152 |
663c425f MC |
730 | #define PHY_SSCCR3 0x03 |
731 | #define PHY_SSCCR3_STEP_IN 0x2740 | |
732 | #define PHY_SSCCR3_CHECK_DELAY 0x0008 | |
41bc2334 MC |
733 | #define _PHY_ANA03 0x03 |
734 | #define _PHY_ANA03_TIMER_MAX 0x2700 | |
735 | #define _PHY_ANA03_OOBS_DEB_EN 0x0040 | |
736 | #define _PHY_CMU_DEBUG_EN 0x0008 | |
b0385381 | 737 | |
4c4b8c10 WW |
738 | #define PHY_RTCR 0x04 |
739 | #define PHY_RDR 0x05 | |
b0385381 MC |
740 | #define PHY_RDR_RXDSEL_1_9 0x4000 |
741 | #define PHY_SSC_AUTO_PWD 0x0600 | |
4c4b8c10 WW |
742 | #define PHY_TCR0 0x06 |
743 | #define PHY_TCR1 0x07 | |
744 | #define PHY_TUNE 0x08 | |
b0385381 MC |
745 | #define PHY_TUNE_TUNEREF_1_0 0x4000 |
746 | #define PHY_TUNE_VBGSEL_1252 0x0C00 | |
747 | #define PHY_TUNE_SDBUS_33 0x0200 | |
748 | #define PHY_TUNE_TUNED18 0x01C0 | |
749 | #define PHY_TUNE_TUNED12 0X0020 | |
750 | #define PHY_TUNE_TUNEA12 0x0004 | |
663c425f MC |
751 | #define PHY_TUNE_VOLTAGE_MASK 0xFC3F |
752 | #define PHY_TUNE_VOLTAGE_3V3 0x03C0 | |
753 | #define PHY_TUNE_D18_1V8 0x0100 | |
754 | #define PHY_TUNE_D18_1V7 0x0080 | |
755 | #define PHY_ANA08 0x08 | |
756 | #define PHY_ANA08_RX_EQ_DCGAIN 0x5000 | |
757 | #define PHY_ANA08_SEL_RX_EN 0x0400 | |
758 | #define PHY_ANA08_RX_EQ_VAL 0x03C0 | |
759 | #define PHY_ANA08_SCP 0x0020 | |
760 | #define PHY_ANA08_SEL_IPI 0x0004 | |
b0385381 | 761 | |
4c4b8c10 WW |
762 | #define PHY_IMR 0x09 |
763 | #define PHY_BPCR 0x0A | |
b0385381 MC |
764 | #define PHY_BPCR_IBRXSEL 0x0400 |
765 | #define PHY_BPCR_IBTXSEL 0x0100 | |
766 | #define PHY_BPCR_IB_FILTER 0x0080 | |
767 | #define PHY_BPCR_CMIRROR_EN 0x0040 | |
768 | ||
4c4b8c10 WW |
769 | #define PHY_BIST 0x0B |
770 | #define PHY_RAW_L 0x0C | |
771 | #define PHY_RAW_H 0x0D | |
772 | #define PHY_RAW_DATA 0x0E | |
773 | #define PHY_HOST_CLK_CTRL 0x0F | |
774 | #define PHY_DMR 0x10 | |
775 | #define PHY_BACR 0x11 | |
663c425f | 776 | #define PHY_BACR_BASIC_MASK 0xFFF3 |
4c4b8c10 WW |
777 | #define PHY_IER 0x12 |
778 | #define PHY_BCSR 0x13 | |
779 | #define PHY_BPR 0x14 | |
780 | #define PHY_BPNR2 0x15 | |
781 | #define PHY_BPNR 0x16 | |
782 | #define PHY_BRNR2 0x17 | |
783 | #define PHY_BENR 0x18 | |
b0385381 MC |
784 | #define PHY_REV 0x19 |
785 | #define PHY_REV_RESV 0xE000 | |
786 | #define PHY_REV_RXIDLE_LATCHED 0x1000 | |
787 | #define PHY_REV_P1_EN 0x0800 | |
788 | #define PHY_REV_RXIDLE_EN 0x0400 | |
789 | #define PHY_REV_CLKREQ_TX_EN 0x0200 | |
790 | #define PHY_REV_CLKREQ_RX_EN 0x0100 | |
791 | #define PHY_REV_CLKREQ_DT_1_0 0x0040 | |
792 | #define PHY_REV_STOP_CLKRD 0x0020 | |
793 | #define PHY_REV_RX_PWST 0x0008 | |
794 | #define PHY_REV_STOP_CLKWR 0x0004 | |
41bc2334 MC |
795 | #define _PHY_REV0 0x19 |
796 | #define _PHY_REV0_FILTER_OUT 0x3800 | |
797 | #define _PHY_REV0_CDR_BYPASS_PFD 0x0100 | |
798 | #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 | |
b0385381 | 799 | |
4c4b8c10 | 800 | #define PHY_FLD0 0x1A |
663c425f MC |
801 | #define PHY_ANA1A 0x1A |
802 | #define PHY_ANA1A_TXR_LOOPBACK 0x2000 | |
803 | #define PHY_ANA1A_RXT_BIST 0x0500 | |
804 | #define PHY_ANA1A_TXR_BIST 0x0040 | |
805 | #define PHY_ANA1A_REV 0x0006 | |
ce6a5acc | 806 | #define PHY_FLD0_INIT_27S 0x2546 |
4c4b8c10 WW |
807 | #define PHY_FLD1 0x1B |
808 | #define PHY_FLD2 0x1C | |
809 | #define PHY_FLD3 0x1D | |
b0385381 MC |
810 | #define PHY_FLD3_TIMER_4 0x0800 |
811 | #define PHY_FLD3_TIMER_6 0x0020 | |
812 | #define PHY_FLD3_RXDELINK 0x0004 | |
ce6a5acc | 813 | #define PHY_FLD3_INIT_27S 0x0004 |
663c425f MC |
814 | #define PHY_ANA1D 0x1D |
815 | #define PHY_ANA1D_DEBUG_ADDR 0x0004 | |
41bc2334 MC |
816 | #define _PHY_FLD0 0x1D |
817 | #define _PHY_FLD0_CLK_REQ_20C 0x8000 | |
818 | #define _PHY_FLD0_RX_IDLE_EN 0x1000 | |
819 | #define _PHY_FLD0_BIT_ERR_RSTN 0x0800 | |
820 | #define _PHY_FLD0_BER_COUNT 0x01E0 | |
821 | #define _PHY_FLD0_BER_TIMER 0x001E | |
822 | #define _PHY_FLD0_CHECK_EN 0x0001 | |
b0385381 | 823 | |
4c4b8c10 | 824 | #define PHY_FLD4 0x1E |
b0385381 MC |
825 | #define PHY_FLD4_FLDEN_SEL 0x4000 |
826 | #define PHY_FLD4_REQ_REF 0x2000 | |
827 | #define PHY_FLD4_RXAMP_OFF 0x1000 | |
828 | #define PHY_FLD4_REQ_ADDA 0x0800 | |
829 | #define PHY_FLD4_BER_COUNT 0x00E0 | |
830 | #define PHY_FLD4_BER_TIMER 0x000A | |
831 | #define PHY_FLD4_BER_CHK_EN 0x0001 | |
ce6a5acc | 832 | #define PHY_FLD4_INIT_27S 0x5C7F |
663c425f MC |
833 | #define PHY_DIG1E 0x1E |
834 | #define PHY_DIG1E_REV 0x4000 | |
835 | #define PHY_DIG1E_D0_X_D1 0x1000 | |
836 | #define PHY_DIG1E_RX_ON_HOST 0x0800 | |
837 | #define PHY_DIG1E_RCLK_REF_HOST 0x0400 | |
838 | #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040 | |
839 | #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020 | |
840 | #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010 | |
841 | #define PHY_DIG1E_TX_TERM_KEEP 0x0008 | |
842 | #define PHY_DIG1E_RX_TERM_KEEP 0x0004 | |
843 | #define PHY_DIG1E_TX_EN_KEEP 0x0002 | |
844 | #define PHY_DIG1E_RX_EN_KEEP 0x0001 | |
4c4b8c10 WW |
845 | #define PHY_DUM_REG 0x1F |
846 | ||
773ccdfd WW |
847 | #define PCR_SETTING_REG1 0x724 |
848 | #define PCR_SETTING_REG2 0x814 | |
849 | #define PCR_SETTING_REG3 0x747 | |
850 | ||
67d16a46 WW |
851 | #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) |
852 | ||
853 | struct rtsx_pcr; | |
854 | ||
855 | struct pcr_handle { | |
856 | struct rtsx_pcr *pcr; | |
857 | }; | |
858 | ||
859 | struct pcr_ops { | |
663c425f MC |
860 | int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val); |
861 | int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val); | |
67d16a46 WW |
862 | int (*extra_init_hw)(struct rtsx_pcr *pcr); |
863 | int (*optimize_phy)(struct rtsx_pcr *pcr); | |
864 | int (*turn_on_led)(struct rtsx_pcr *pcr); | |
865 | int (*turn_off_led)(struct rtsx_pcr *pcr); | |
866 | int (*enable_auto_blink)(struct rtsx_pcr *pcr); | |
867 | int (*disable_auto_blink)(struct rtsx_pcr *pcr); | |
868 | int (*card_power_on)(struct rtsx_pcr *pcr, int card); | |
869 | int (*card_power_off)(struct rtsx_pcr *pcr, int card); | |
d817ac4e WW |
870 | int (*switch_output_voltage)(struct rtsx_pcr *pcr, |
871 | u8 voltage); | |
67d16a46 | 872 | unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); |
ab4e8f8b | 873 | int (*conv_clk_and_div_n)(int clk, int dir); |
773ccdfd | 874 | void (*fetch_vendor_settings)(struct rtsx_pcr *pcr); |
eb891c65 | 875 | void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state); |
67d16a46 WW |
876 | }; |
877 | ||
878 | enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; | |
879 | ||
880 | struct rtsx_pcr { | |
881 | struct pci_dev *pci; | |
882 | unsigned int id; | |
19f3bd54 | 883 | int pcie_cap; |
67d16a46 WW |
884 | |
885 | /* pci resources */ | |
886 | unsigned long addr; | |
887 | void __iomem *remap_addr; | |
888 | int irq; | |
889 | ||
890 | /* host reserved buffer */ | |
891 | void *rtsx_resv_buf; | |
892 | dma_addr_t rtsx_resv_buf_addr; | |
893 | ||
894 | void *host_cmds_ptr; | |
895 | dma_addr_t host_cmds_addr; | |
896 | int ci; | |
897 | ||
898 | void *host_sg_tbl_ptr; | |
899 | dma_addr_t host_sg_tbl_addr; | |
900 | int sgi; | |
901 | ||
902 | u32 bier; | |
903 | char trans_result; | |
904 | ||
905 | unsigned int card_inserted; | |
906 | unsigned int card_removed; | |
c3481955 | 907 | unsigned int card_exist; |
67d16a46 WW |
908 | |
909 | struct delayed_work carddet_work; | |
910 | struct delayed_work idle_work; | |
911 | ||
912 | spinlock_t lock; | |
913 | struct mutex pcr_mutex; | |
914 | struct completion *done; | |
915 | struct completion *finish_me; | |
916 | ||
917 | unsigned int cur_clock; | |
67d16a46 WW |
918 | bool remove_pci; |
919 | bool msi_en; | |
920 | ||
921 | #define EXTRA_CAPS_SD_SDR50 (1 << 0) | |
922 | #define EXTRA_CAPS_SD_SDR104 (1 << 1) | |
923 | #define EXTRA_CAPS_SD_DDR50 (1 << 2) | |
924 | #define EXTRA_CAPS_MMC_HSDDR (1 << 3) | |
925 | #define EXTRA_CAPS_MMC_HS200 (1 << 4) | |
926 | #define EXTRA_CAPS_MMC_8BIT (1 << 5) | |
927 | u32 extra_caps; | |
928 | ||
929 | #define IC_VER_A 0 | |
930 | #define IC_VER_B 1 | |
931 | #define IC_VER_C 2 | |
932 | #define IC_VER_D 3 | |
933 | u8 ic_version; | |
934 | ||
773ccdfd WW |
935 | u8 sd30_drive_sel_1v8; |
936 | u8 sd30_drive_sel_3v3; | |
937 | u8 card_drive_sel; | |
938 | #define ASPM_L1_EN 0x02 | |
939 | u8 aspm_en; | |
940 | ||
941 | #define PCR_MS_PMOS (1 << 0) | |
942 | #define PCR_REVERSE_SOCKET (1 << 1) | |
943 | u32 flags; | |
944 | ||
84d72f9c WW |
945 | u32 tx_initial_phase; |
946 | u32 rx_initial_phase; | |
947 | ||
67d16a46 WW |
948 | const u32 *sd_pull_ctl_enable_tbl; |
949 | const u32 *sd_pull_ctl_disable_tbl; | |
950 | const u32 *ms_pull_ctl_enable_tbl; | |
951 | const u32 *ms_pull_ctl_disable_tbl; | |
952 | ||
953 | const struct pcr_ops *ops; | |
954 | enum PDEV_STAT state; | |
955 | ||
663c425f MC |
956 | u16 reg_pm_ctrl3; |
957 | ||
67d16a46 WW |
958 | int num_slots; |
959 | struct rtsx_slot *slots; | |
960 | }; | |
961 | ||
962 | #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid)) | |
963 | #define PCI_VID(pcr) ((pcr)->pci->vendor) | |
964 | #define PCI_PID(pcr) ((pcr)->pci->device) | |
663c425f MC |
965 | #define is_version(pcr, pid, ver) \ |
966 | (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver)) | |
967 | #define pcr_dbg(pcr, fmt, arg...) \ | |
968 | dev_dbg(&(pcr)->pci->dev, fmt, ##arg) | |
67d16a46 | 969 | |
84d72f9c WW |
970 | #define SDR104_PHASE(val) ((val) & 0xFF) |
971 | #define SDR50_PHASE(val) (((val) >> 8) & 0xFF) | |
972 | #define DDR50_PHASE(val) (((val) >> 16) & 0xFF) | |
973 | #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase) | |
974 | #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase) | |
975 | #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase) | |
976 | #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase) | |
977 | #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase) | |
978 | #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase) | |
979 | #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ | |
980 | (((ddr50) << 16) | ((sdr50) << 8) | (sdr104)) | |
981 | ||
67d16a46 WW |
982 | void rtsx_pci_start_run(struct rtsx_pcr *pcr); |
983 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); | |
984 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); | |
985 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); | |
986 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); | |
987 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr); | |
988 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
989 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data); | |
990 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr); | |
991 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout); | |
992 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
993 | int num_sg, bool read, int timeout); | |
8cd11830 MC |
994 | int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, |
995 | int num_sg, bool read); | |
996 | void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
997 | int num_sg, bool read); | |
998 | int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
999 | int count, bool read, int timeout); | |
67d16a46 WW |
1000 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); |
1001 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); | |
1002 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card); | |
1003 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card); | |
1004 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
1005 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); | |
1006 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card); | |
1007 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card); | |
c3481955 | 1008 | int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card); |
d817ac4e | 1009 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage); |
67d16a46 WW |
1010 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr); |
1011 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr); | |
1012 | ||
1013 | static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) | |
1014 | { | |
1015 | return (u8 *)(pcr->host_cmds_ptr); | |
1016 | } | |
1017 | ||
5cb5d961 MC |
1018 | static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr, |
1019 | u8 mask, u8 append) | |
1020 | { | |
1021 | int err; | |
1022 | u8 val; | |
1023 | ||
1024 | err = pci_read_config_byte(pcr->pci, addr, &val); | |
1025 | if (err < 0) | |
1026 | return err; | |
1027 | return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); | |
1028 | } | |
1029 | ||
a3b63979 MC |
1030 | static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) |
1031 | { | |
1032 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); | |
1033 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); | |
1034 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); | |
1035 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); | |
1036 | } | |
1037 | ||
663c425f MC |
1038 | static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr, |
1039 | u16 mask, u16 append) | |
1040 | { | |
1041 | int err; | |
1042 | u16 val; | |
1043 | ||
1044 | err = rtsx_pci_read_phy_register(pcr, addr, &val); | |
1045 | if (err < 0) | |
1046 | return err; | |
1047 | ||
1048 | return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append); | |
1049 | } | |
1050 | ||
67d16a46 | 1051 | #endif |