projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f5f7078 SK |
1 | /* |
| 2 | * s5m-core.h | |
| 3 | * | |
| 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms of the GNU General Public License as published by the | |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 10 | * option) any later version. | |
| 11 | * | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __LINUX_MFD_S5M_CORE_H | |
| 15 | #define __LINUX_MFD_S5M_CORE_H | |
| 16 | ||
| 17 | #define NUM_IRQ_REGS 4 | |
| 18 | ||
| 63063bfb | 19 | enum sec_device_type { |
| 0f5f7078 SK |
20 | S5M8751X, |
| 21 | S5M8763X, | |
| 22 | S5M8767X, | |
| 23 | }; | |
| 24 | ||
| 25 | /* S5M8767 registers */ | |
| 26 | enum s5m8767_reg { | |
| 27 | S5M8767_REG_ID, | |
| 28 | S5M8767_REG_INT1, | |
| 29 | S5M8767_REG_INT2, | |
| 30 | S5M8767_REG_INT3, | |
| 31 | S5M8767_REG_INT1M, | |
| 32 | S5M8767_REG_INT2M, | |
| 33 | S5M8767_REG_INT3M, | |
| 34 | S5M8767_REG_STATUS1, | |
| 35 | S5M8767_REG_STATUS2, | |
| 36 | S5M8767_REG_STATUS3, | |
| 37 | S5M8767_REG_CTRL1, | |
| 38 | S5M8767_REG_CTRL2, | |
| 39 | S5M8767_REG_LOWBAT1, | |
| 40 | S5M8767_REG_LOWBAT2, | |
| 41 | S5M8767_REG_BUCHG, | |
| 42 | S5M8767_REG_DVSRAMP, | |
| 43 | S5M8767_REG_DVSTIMER2 = 0x10, | |
| 44 | S5M8767_REG_DVSTIMER3, | |
| 45 | S5M8767_REG_DVSTIMER4, | |
| 46 | S5M8767_REG_LDO1, | |
| 47 | S5M8767_REG_LDO2, | |
| 48 | S5M8767_REG_LDO3, | |
| 49 | S5M8767_REG_LDO4, | |
| 50 | S5M8767_REG_LDO5, | |
| 51 | S5M8767_REG_LDO6, | |
| 52 | S5M8767_REG_LDO7, | |
| 53 | S5M8767_REG_LDO8, | |
| 54 | S5M8767_REG_LDO9, | |
| 55 | S5M8767_REG_LDO10, | |
| 56 | S5M8767_REG_LDO11, | |
| 57 | S5M8767_REG_LDO12, | |
| 58 | S5M8767_REG_LDO13, | |
| 59 | S5M8767_REG_LDO14 = 0x20, | |
| 60 | S5M8767_REG_LDO15, | |
| 61 | S5M8767_REG_LDO16, | |
| 62 | S5M8767_REG_LDO17, | |
| 63 | S5M8767_REG_LDO18, | |
| 64 | S5M8767_REG_LDO19, | |
| 65 | S5M8767_REG_LDO20, | |
| 66 | S5M8767_REG_LDO21, | |
| 67 | S5M8767_REG_LDO22, | |
| 68 | S5M8767_REG_LDO23, | |
| 69 | S5M8767_REG_LDO24, | |
| 70 | S5M8767_REG_LDO25, | |
| 71 | S5M8767_REG_LDO26, | |
| 72 | S5M8767_REG_LDO27, | |
| 73 | S5M8767_REG_LDO28, | |
| 74 | S5M8767_REG_UVLO = 0x31, | |
| 75 | S5M8767_REG_BUCK1CTRL1, | |
| 76 | S5M8767_REG_BUCK1CTRL2, | |
| 77 | S5M8767_REG_BUCK2CTRL, | |
| 78 | S5M8767_REG_BUCK2DVS1, | |
| 79 | S5M8767_REG_BUCK2DVS2, | |
| 80 | S5M8767_REG_BUCK2DVS3, | |
| 81 | S5M8767_REG_BUCK2DVS4, | |
| 82 | S5M8767_REG_BUCK2DVS5, | |
| 83 | S5M8767_REG_BUCK2DVS6, | |
| 84 | S5M8767_REG_BUCK2DVS7, | |
| 85 | S5M8767_REG_BUCK2DVS8, | |
| 86 | S5M8767_REG_BUCK3CTRL, | |
| 87 | S5M8767_REG_BUCK3DVS1, | |
| 88 | S5M8767_REG_BUCK3DVS2, | |
| 89 | S5M8767_REG_BUCK3DVS3, | |
| 90 | S5M8767_REG_BUCK3DVS4, | |
| 91 | S5M8767_REG_BUCK3DVS5, | |
| 92 | S5M8767_REG_BUCK3DVS6, | |
| 93 | S5M8767_REG_BUCK3DVS7, | |
| 94 | S5M8767_REG_BUCK3DVS8, | |
| 95 | S5M8767_REG_BUCK4CTRL, | |
| 96 | S5M8767_REG_BUCK4DVS1, | |
| 97 | S5M8767_REG_BUCK4DVS2, | |
| 98 | S5M8767_REG_BUCK4DVS3, | |
| 99 | S5M8767_REG_BUCK4DVS4, | |
| 100 | S5M8767_REG_BUCK4DVS5, | |
| 101 | S5M8767_REG_BUCK4DVS6, | |
| 102 | S5M8767_REG_BUCK4DVS7, | |
| 103 | S5M8767_REG_BUCK4DVS8, | |
| 104 | S5M8767_REG_BUCK5CTRL1, | |
| 105 | S5M8767_REG_BUCK5CTRL2, | |
| 106 | S5M8767_REG_BUCK5CTRL3, | |
| 107 | S5M8767_REG_BUCK5CTRL4, | |
| 108 | S5M8767_REG_BUCK5CTRL5, | |
| 109 | S5M8767_REG_BUCK6CTRL1, | |
| 110 | S5M8767_REG_BUCK6CTRL2, | |
| 111 | S5M8767_REG_BUCK7CTRL1, | |
| 112 | S5M8767_REG_BUCK7CTRL2, | |
| 113 | S5M8767_REG_BUCK8CTRL1, | |
| 114 | S5M8767_REG_BUCK8CTRL2, | |
| 115 | S5M8767_REG_BUCK9CTRL1, | |
| 116 | S5M8767_REG_BUCK9CTRL2, | |
| 117 | S5M8767_REG_LDO1CTRL, | |
| 118 | S5M8767_REG_LDO2_1CTRL, | |
| 119 | S5M8767_REG_LDO2_2CTRL, | |
| 120 | S5M8767_REG_LDO2_3CTRL, | |
| 121 | S5M8767_REG_LDO2_4CTRL, | |
| 122 | S5M8767_REG_LDO3CTRL, | |
| 123 | S5M8767_REG_LDO4CTRL, | |
| 124 | S5M8767_REG_LDO5CTRL, | |
| 125 | S5M8767_REG_LDO6CTRL, | |
| 126 | S5M8767_REG_LDO7CTRL, | |
| 127 | S5M8767_REG_LDO8CTRL, | |
| 128 | S5M8767_REG_LDO9CTRL, | |
| 129 | S5M8767_REG_LDO10CTRL, | |
| 130 | S5M8767_REG_LDO11CTRL, | |
| 131 | S5M8767_REG_LDO12CTRL, | |
| 132 | S5M8767_REG_LDO13CTRL, | |
| 133 | S5M8767_REG_LDO14CTRL, | |
| 134 | S5M8767_REG_LDO15CTRL, | |
| 135 | S5M8767_REG_LDO16CTRL, | |
| 136 | S5M8767_REG_LDO17CTRL, | |
| 137 | S5M8767_REG_LDO18CTRL, | |
| 138 | S5M8767_REG_LDO19CTRL, | |
| 139 | S5M8767_REG_LDO20CTRL, | |
| 140 | S5M8767_REG_LDO21CTRL, | |
| 141 | S5M8767_REG_LDO22CTRL, | |
| 142 | S5M8767_REG_LDO23CTRL, | |
| 143 | S5M8767_REG_LDO24CTRL, | |
| 144 | S5M8767_REG_LDO25CTRL, | |
| 145 | S5M8767_REG_LDO26CTRL, | |
| 146 | S5M8767_REG_LDO27CTRL, | |
| 147 | S5M8767_REG_LDO28CTRL, | |
| 148 | }; | |
| 149 | ||
| 150 | /* S5M8763 registers */ | |
| 151 | enum s5m8763_reg { | |
| 152 | S5M8763_REG_IRQ1, | |
| 153 | S5M8763_REG_IRQ2, | |
| 154 | S5M8763_REG_IRQ3, | |
| 155 | S5M8763_REG_IRQ4, | |
| 156 | S5M8763_REG_IRQM1, | |
| 157 | S5M8763_REG_IRQM2, | |
| 158 | S5M8763_REG_IRQM3, | |
| 159 | S5M8763_REG_IRQM4, | |
| 160 | S5M8763_REG_STATUS1, | |
| 161 | S5M8763_REG_STATUS2, | |
| 162 | S5M8763_REG_STATUSM1, | |
| 163 | S5M8763_REG_STATUSM2, | |
| 164 | S5M8763_REG_CHGR1, | |
| 165 | S5M8763_REG_CHGR2, | |
| 166 | S5M8763_REG_LDO_ACTIVE_DISCHARGE1, | |
| 167 | S5M8763_REG_LDO_ACTIVE_DISCHARGE2, | |
| 168 | S5M8763_REG_BUCK_ACTIVE_DISCHARGE3, | |
| 169 | S5M8763_REG_ONOFF1, | |
| 170 | S5M8763_REG_ONOFF2, | |
| 171 | S5M8763_REG_ONOFF3, | |
| 172 | S5M8763_REG_ONOFF4, | |
| 173 | S5M8763_REG_BUCK1_VOLTAGE1, | |
| 174 | S5M8763_REG_BUCK1_VOLTAGE2, | |
| 175 | S5M8763_REG_BUCK1_VOLTAGE3, | |
| 176 | S5M8763_REG_BUCK1_VOLTAGE4, | |
| 177 | S5M8763_REG_BUCK2_VOLTAGE1, | |
| 178 | S5M8763_REG_BUCK2_VOLTAGE2, | |
| 179 | S5M8763_REG_BUCK3, | |
| 180 | S5M8763_REG_BUCK4, | |
| 181 | S5M8763_REG_LDO1_LDO2, | |
| 182 | S5M8763_REG_LDO3, | |
| 183 | S5M8763_REG_LDO4, | |
| 184 | S5M8763_REG_LDO5, | |
| 185 | S5M8763_REG_LDO6, | |
| 186 | S5M8763_REG_LDO7, | |
| 187 | S5M8763_REG_LDO7_LDO8, | |
| 188 | S5M8763_REG_LDO9_LDO10, | |
| 189 | S5M8763_REG_LDO11, | |
| 190 | S5M8763_REG_LDO12, | |
| 191 | S5M8763_REG_LDO13, | |
| 192 | S5M8763_REG_LDO14, | |
| 193 | S5M8763_REG_LDO15, | |
| 194 | S5M8763_REG_LDO16, | |
| 195 | S5M8763_REG_BKCHR, | |
| 196 | S5M8763_REG_LBCNFG1, | |
| 197 | S5M8763_REG_LBCNFG2, | |
| 198 | }; | |
| 199 | ||
| 200 | enum s5m8767_irq { | |
| 201 | S5M8767_IRQ_PWRR, | |
| 202 | S5M8767_IRQ_PWRF, | |
| 203 | S5M8767_IRQ_PWR1S, | |
| 204 | S5M8767_IRQ_JIGR, | |
| 205 | S5M8767_IRQ_JIGF, | |
| 206 | S5M8767_IRQ_LOWBAT2, | |
| 207 | S5M8767_IRQ_LOWBAT1, | |
| 208 | ||
| 209 | S5M8767_IRQ_MRB, | |
| 210 | S5M8767_IRQ_DVSOK2, | |
| 211 | S5M8767_IRQ_DVSOK3, | |
| 212 | S5M8767_IRQ_DVSOK4, | |
| 213 | ||
| 214 | S5M8767_IRQ_RTC60S, | |
| 215 | S5M8767_IRQ_RTCA1, | |
| 216 | S5M8767_IRQ_RTCA2, | |
| 217 | S5M8767_IRQ_SMPL, | |
| 218 | S5M8767_IRQ_RTC1S, | |
| 219 | S5M8767_IRQ_WTSR, | |
| 220 | ||
| 221 | S5M8767_IRQ_NR, | |
| 222 | }; | |
| 223 | ||
| 224 | #define S5M8767_IRQ_PWRR_MASK (1 << 0) | |
| 225 | #define S5M8767_IRQ_PWRF_MASK (1 << 1) | |
| 226 | #define S5M8767_IRQ_PWR1S_MASK (1 << 3) | |
| 227 | #define S5M8767_IRQ_JIGR_MASK (1 << 4) | |
| 228 | #define S5M8767_IRQ_JIGF_MASK (1 << 5) | |
| 229 | #define S5M8767_IRQ_LOWBAT2_MASK (1 << 6) | |
| 230 | #define S5M8767_IRQ_LOWBAT1_MASK (1 << 7) | |
| 231 | ||
| 232 | #define S5M8767_IRQ_MRB_MASK (1 << 2) | |
| 233 | #define S5M8767_IRQ_DVSOK2_MASK (1 << 3) | |
| 234 | #define S5M8767_IRQ_DVSOK3_MASK (1 << 4) | |
| 235 | #define S5M8767_IRQ_DVSOK4_MASK (1 << 5) | |
| 236 | ||
| 237 | #define S5M8767_IRQ_RTC60S_MASK (1 << 0) | |
| 238 | #define S5M8767_IRQ_RTCA1_MASK (1 << 1) | |
| 239 | #define S5M8767_IRQ_RTCA2_MASK (1 << 2) | |
| 240 | #define S5M8767_IRQ_SMPL_MASK (1 << 3) | |
| 241 | #define S5M8767_IRQ_RTC1S_MASK (1 << 4) | |
| 242 | #define S5M8767_IRQ_WTSR_MASK (1 << 5) | |
| 243 | ||
| 244 | enum s5m8763_irq { | |
| 245 | S5M8763_IRQ_DCINF, | |
| 246 | S5M8763_IRQ_DCINR, | |
| 247 | S5M8763_IRQ_JIGF, | |
| 248 | S5M8763_IRQ_JIGR, | |
| 249 | S5M8763_IRQ_PWRONF, | |
| 250 | S5M8763_IRQ_PWRONR, | |
| 251 | ||
| 252 | S5M8763_IRQ_WTSREVNT, | |
| 253 | S5M8763_IRQ_SMPLEVNT, | |
| 254 | S5M8763_IRQ_ALARM1, | |
| 255 | S5M8763_IRQ_ALARM0, | |
| 256 | ||
| 257 | S5M8763_IRQ_ONKEY1S, | |
| 258 | S5M8763_IRQ_TOPOFFR, | |
| 259 | S5M8763_IRQ_DCINOVPR, | |
| 260 | S5M8763_IRQ_CHGRSTF, | |
| 261 | S5M8763_IRQ_DONER, | |
| 262 | S5M8763_IRQ_CHGFAULT, | |
| 263 | ||
| 264 | S5M8763_IRQ_LOBAT1, | |
| 265 | S5M8763_IRQ_LOBAT2, | |
| 266 | ||
| 267 | S5M8763_IRQ_NR, | |
| 268 | }; | |
| 269 | ||
| 270 | #define S5M8763_IRQ_DCINF_MASK (1 << 2) | |
| 271 | #define S5M8763_IRQ_DCINR_MASK (1 << 3) | |
| 272 | #define S5M8763_IRQ_JIGF_MASK (1 << 4) | |
| 273 | #define S5M8763_IRQ_JIGR_MASK (1 << 5) | |
| 274 | #define S5M8763_IRQ_PWRONF_MASK (1 << 6) | |
| 275 | #define S5M8763_IRQ_PWRONR_MASK (1 << 7) | |
| 276 | ||
| 277 | #define S5M8763_IRQ_WTSREVNT_MASK (1 << 0) | |
| 278 | #define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1) | |
| 279 | #define S5M8763_IRQ_ALARM1_MASK (1 << 2) | |
| 280 | #define S5M8763_IRQ_ALARM0_MASK (1 << 3) | |
| 281 | ||
| 282 | #define S5M8763_IRQ_ONKEY1S_MASK (1 << 0) | |
| 283 | #define S5M8763_IRQ_TOPOFFR_MASK (1 << 2) | |
| 284 | #define S5M8763_IRQ_DCINOVPR_MASK (1 << 3) | |
| 285 | #define S5M8763_IRQ_CHGRSTF_MASK (1 << 4) | |
| 286 | #define S5M8763_IRQ_DONER_MASK (1 << 5) | |
| 287 | #define S5M8763_IRQ_CHGFAULT_MASK (1 << 7) | |
| 288 | ||
| 289 | #define S5M8763_IRQ_LOBAT1_MASK (1 << 0) | |
| 290 | #define S5M8763_IRQ_LOBAT2_MASK (1 << 1) | |
| 291 | ||
| 292 | #define S5M8763_ENRAMP (1 << 4) | |
| 293 | ||
| 294 | /** | |
| 63063bfb | 295 | * struct sec_pmic_dev - sec_pmic master device for sub-drivers |
| 0f5f7078 SK |
296 | * @dev: master device of the chip (can be used to access platform data) |
| 297 | * @i2c: i2c client private data for regulator | |
| 298 | * @rtc: i2c client private data for rtc | |
| 299 | * @iolock: mutex for serializing io access | |
| 300 | * @irqlock: mutex for buslock | |
| 63063bfb | 301 | * @irq_base: base IRQ number for sec_pmic, required for IRQs |
| 0f5f7078 SK |
302 | * @irq: generic IRQ number for s5m87xx |
| 303 | * @ono: power onoff IRQ number for s5m87xx | |
| 304 | * @irq_masks_cur: currently active value | |
| 305 | * @irq_masks_cache: cached hardware value | |
| 306 | * @type: indicate which s5m87xx "variant" is used | |
| 307 | */ | |
| 63063bfb | 308 | struct sec_pmic_dev { |
| 0f5f7078 SK |
309 | struct device *dev; |
| 310 | struct regmap *regmap; | |
| 311 | struct i2c_client *i2c; | |
| 312 | struct i2c_client *rtc; | |
| 313 | struct mutex iolock; | |
| 314 | struct mutex irqlock; | |
| 315 | ||
| 316 | int device_type; | |
| 317 | int irq_base; | |
| 318 | int irq; | |
| 319 | int ono; | |
| 320 | u8 irq_masks_cur[NUM_IRQ_REGS]; | |
| 321 | u8 irq_masks_cache[NUM_IRQ_REGS]; | |
| 322 | int type; | |
| 323 | bool wakeup; | |
| 324 | }; | |
| 325 | ||
| 63063bfb SK |
326 | int sec_irq_init(struct sec_pmic_dev *sec_pmic); |
| 327 | void sec_irq_exit(struct sec_pmic_dev *sec_pmic); | |
| 328 | int sec_irq_resume(struct sec_pmic_dev *sec_pmic); | |
| 0f5f7078 | 329 | |
| 63063bfb SK |
330 | extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest); |
| 331 | extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); | |
| 332 | extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value); | |
| 333 | extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); | |
| 334 | extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask); | |
| 0f5f7078 | 335 | |
| 63063bfb SK |
336 | struct sec_platform_data { |
| 337 | struct sec_regulator_data *regulators; | |
| 338 | struct sec_opmode_data *opmode; | |
| 0f5f7078 SK |
339 | int device_type; |
| 340 | int num_regulators; | |
| 341 | ||
| 342 | int irq_base; | |
| 66c9fbb9 | 343 | int (*cfg_pmic_irq)(void); |
| 0f5f7078 SK |
344 | |
| 345 | int ono; | |
| 346 | bool wakeup; | |
| 347 | bool buck_voltage_lock; | |
| 348 | ||
| 349 | int buck_gpios[3]; | |
| 350 | int buck2_voltage[8]; | |
| 351 | bool buck2_gpiodvs; | |
| 352 | int buck3_voltage[8]; | |
| 353 | bool buck3_gpiodvs; | |
| 354 | int buck4_voltage[8]; | |
| 355 | bool buck4_gpiodvs; | |
| 356 | ||
| 357 | int buck_set1; | |
| 358 | int buck_set2; | |
| 359 | int buck_set3; | |
| 360 | int buck2_enable; | |
| 361 | int buck3_enable; | |
| 362 | int buck4_enable; | |
| 363 | int buck_default_idx; | |
| 364 | int buck2_default_idx; | |
| 365 | int buck3_default_idx; | |
| 366 | int buck4_default_idx; | |
| 367 | ||
| 368 | int buck_ramp_delay; | |
| 369 | bool buck2_ramp_enable; | |
| 370 | bool buck3_ramp_enable; | |
| 371 | bool buck4_ramp_enable; | |
| 372 | }; | |
| 373 | ||
| 374 | #endif /* __LINUX_MFD_S5M_CORE_H */ |