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{NET, IB}/mlx4: Add device managed flow steering firmware API
[deliverable/linux.git] / include / linux / mlx4 / device.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
60063497 40#include <linux/atomic.h>
225c7b1f 41
0b7ca5a9
YP		 42#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
225c7b1f
RD		 47enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 53};
54
55enum {
56 MLX4_MAX_PORTS = 2
57};
58
cd9281d8
JM		 59enum {
60 MLX4_BOARD_ID_LEN = 64
61};
62
623ed84b
JM		 63enum {
64 MLX4_MAX_NUM_PF = 16,
65 MLX4_MAX_NUM_VF = 64,
66 MLX4_MFUNC_MAX = 80,
3fc929e2 67 MLX4_MAX_EQ_NUM = 1024,
623ed84b
JM		 68 MLX4_MFUNC_EQ_NUM = 4,
69 MLX4_MFUNC_MAX_EQES = 8,
70 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
71};
72
0ff1fb65
HHZ		 73/* Driver supports 3 diffrent device methods to manage traffic steering:
74 * -device managed - High level API for ib and eth flow steering. FW is
75 * managing flow steering tables.
c96d97f4
HHZ		 76 * - B0 steering mode - Common low level API for ib and (if supported) eth.
77 * - A0 steering mode - Limited low level API for eth. In case of IB,
78 * B0 mode is in use.
79 */
80enum {
81 MLX4_STEERING_MODE_A0,
0ff1fb65
HHZ		 82 MLX4_STEERING_MODE_B0,
83 MLX4_STEERING_MODE_DEVICE_MANAGED
c96d97f4
HHZ		 84};
85
86static inline const char *mlx4_steering_mode_str(int steering_mode)
87{
88 switch (steering_mode) {
89 case MLX4_STEERING_MODE_A0:
90 return "A0 steering";
91
92 case MLX4_STEERING_MODE_B0:
93 return "B0 steering";
0ff1fb65
HHZ		 94
95 case MLX4_STEERING_MODE_DEVICE_MANAGED:
96 return "Device managed flow steering";
97
c96d97f4
HHZ		 98 default:
99 return "Unrecognize steering mode";
100 }
101}
102
225c7b1f 103enum {
52eafc68
OG		 104 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
105 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
106 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 107 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 108 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
109 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
110 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
111 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
112 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
113 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
114 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
115 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
116 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
117 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
118 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
119 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 120 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
121 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 122 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 123 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
124 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 125 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
126 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 127 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168
YP		 128 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
129 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
225c7b1f
RD		 130};
131
b3416f44
SP		 132enum {
133 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
134 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
0ff1fb65
HHZ		 135 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
136 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3
b3416f44
SP		 137};
138
97285b78
MA		 139#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
140
95d04f07
RD		 141enum {
142 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
143 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
144 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
145 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
146 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
147};
148
225c7b1f
RD		 149enum mlx4_event {
150 MLX4_EVENT_TYPE_COMP = 0x00,
151 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
152 MLX4_EVENT_TYPE_COMM_EST = 0x02,
153 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
154 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
155 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
156 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
157 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
158 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
159 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
160 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
161 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
162 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
163 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
164 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
165 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
166 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 167 MLX4_EVENT_TYPE_CMD = 0x0a,
168 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
169 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 170 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b
JM		 171 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
172 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 173};
174
175enum {
176 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
177 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
178};
179
5984be90
JM		 180enum {
181 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
182};
183
225c7b1f
RD		 184enum {
185 MLX4_PERM_LOCAL_READ = 1 << 10,
186 MLX4_PERM_LOCAL_WRITE = 1 << 11,
187 MLX4_PERM_REMOTE_READ = 1 << 12,
188 MLX4_PERM_REMOTE_WRITE = 1 << 13,
189 MLX4_PERM_ATOMIC = 1 << 14
190};
191
192enum {
193 MLX4_OPCODE_NOP = 0x00,
194 MLX4_OPCODE_SEND_INVAL = 0x01,
195 MLX4_OPCODE_RDMA_WRITE = 0x08,
196 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
197 MLX4_OPCODE_SEND = 0x0a,
198 MLX4_OPCODE_SEND_IMM = 0x0b,
199 MLX4_OPCODE_LSO = 0x0e,
200 MLX4_OPCODE_RDMA_READ = 0x10,
201 MLX4_OPCODE_ATOMIC_CS = 0x11,
202 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 203 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
204 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 205 MLX4_OPCODE_BIND_MW = 0x18,
206 MLX4_OPCODE_FMR = 0x19,
207 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
208 MLX4_OPCODE_CONFIG_CMD = 0x1f,
209
210 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
211 MLX4_RECV_OPCODE_SEND = 0x01,
212 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
213 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
214
215 MLX4_CQE_OPCODE_ERROR = 0x1e,
216 MLX4_CQE_OPCODE_RESIZE = 0x16,
217};
218
219enum {
220 MLX4_STAT_RATE_OFFSET = 5
221};
222
da995a8a 223enum mlx4_protocol {
0345584e
YP		 224 MLX4_PROT_IB_IPV6 = 0,
225 MLX4_PROT_ETH,
226 MLX4_PROT_IB_IPV4,
227 MLX4_PROT_FCOE
da995a8a
AS		 228};
229
29bdc883
VS		 230enum {
231 MLX4_MTT_FLAG_PRESENT = 1
232};
233
93fc9e1b
YP		 234enum mlx4_qp_region {
235 MLX4_QP_REGION_FW = 0,
236 MLX4_QP_REGION_ETH_ADDR,
237 MLX4_QP_REGION_FC_ADDR,
238 MLX4_QP_REGION_FC_EXCH,
239 MLX4_NUM_QP_REGION
240};
241
7ff93f8b 242enum mlx4_port_type {
623ed84b 243 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 244 MLX4_PORT_TYPE_IB = 1,
245 MLX4_PORT_TYPE_ETH = 2,
246 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 247};
248
2a2336f8
YP		 249enum mlx4_special_vlan_idx {
250 MLX4_NO_VLAN_IDX = 0,
251 MLX4_VLAN_MISS_IDX,
252 MLX4_VLAN_REGULAR
253};
254
0345584e
YP		 255enum mlx4_steer_type {
256 MLX4_MC_STEER = 0,
257 MLX4_UC_STEER,
258 MLX4_NUM_STEERS
259};
260
93fc9e1b
YP		 261enum {
262 MLX4_NUM_FEXCH = 64 * 1024,
263};
264
5a0fd094
EC		 265enum {
266 MLX4_MAX_FAST_REG_PAGES = 511,
267};
268
ea54b10c
JM		 269static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
270{
271 return (major << 32) | (minor << 16) | subminor;
272}
273
3fc929e2
MA		 274struct mlx4_phys_caps {
275 u32 num_phys_eqs;
276};
277
225c7b1f
RD		 278struct mlx4_caps {
279 u64 fw_ver;
623ed84b 280 u32 function;
225c7b1f 281 int num_ports;
5ae2a7a8 282 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 283 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 284 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 285 u64 def_mac[MLX4_MAX_PORTS + 1];
286 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 287 int gid_table_len[MLX4_MAX_PORTS + 1];
288 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 289 int trans_type[MLX4_MAX_PORTS + 1];
290 int vendor_oui[MLX4_MAX_PORTS + 1];
291 int wavelength[MLX4_MAX_PORTS + 1];
292 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 293 int local_ca_ack_delay;
294 int num_uars;
f5311ac1 295 u32 uar_page_size;
225c7b1f
RD		 296 int bf_reg_size;
297 int bf_regs_per_page;
298 int max_sq_sg;
299 int max_rq_sg;
300 int num_qps;
301 int max_wqes;
302 int max_sq_desc_sz;
303 int max_rq_desc_sz;
304 int max_qp_init_rdma;
305 int max_qp_dest_rdma;
225c7b1f
RD		 306 int sqp_start;
307 int num_srqs;
308 int max_srq_wqes;
309 int max_srq_sge;
310 int reserved_srqs;
311 int num_cqs;
312 int max_cqes;
313 int reserved_cqs;
314 int num_eqs;
315 int reserved_eqs;
b8dd786f 316 int num_comp_vectors;
0b7ca5a9 317 int comp_pool;
225c7b1f 318 int num_mpts;
a5bbe892 319 int max_fmr_maps;
2b8fb286 320 int num_mtts;
225c7b1f
RD		 321 int fmr_reserved_mtts;
322 int reserved_mtts;
323 int reserved_mrws;
324 int reserved_uars;
325 int num_mgms;
326 int num_amgms;
327 int reserved_mcgs;
328 int num_qp_per_mgm;
c96d97f4 329 int steering_mode;
0ff1fb65 330 int fs_log_max_ucast_qp_range_size;
225c7b1f
RD		 331 int num_pds;
332 int reserved_pds;
012a8ff5
SH		 333 int max_xrcds;
334 int reserved_xrcds;
225c7b1f 335 int mtt_entry_sz;
149983af 336 u32 max_msg_sz;
225c7b1f 337 u32 page_size_cap;
52eafc68 338 u64 flags;
b3416f44 339 u64 flags2;
95d04f07
RD		 340 u32 bmme_flags;
341 u32 reserved_lkey;
225c7b1f 342 u16 stat_rate_support;
5ae2a7a8 343 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 344 int max_gso_sz;
b3416f44 345 int max_rss_tbl_sz;
93fc9e1b
YP		 346 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
347 int reserved_qps;
348 int reserved_qps_base[MLX4_NUM_QP_REGION];
349 int log_num_macs;
350 int log_num_vlans;
351 int log_num_prios;
7ff93f8b
YP		 352 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
353 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 354 u8 suggested_type[MLX4_MAX_PORTS + 1];
355 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 356 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 357 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 358 u32 max_counters;
096335b3 359 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 360};
361
362struct mlx4_buf_list {
363 void *buf;
364 dma_addr_t map;
365};
366
367struct mlx4_buf {
b57aacfa
RD		 368 struct mlx4_buf_list direct;
369 struct mlx4_buf_list *page_list;
225c7b1f
RD		 370 int nbufs;
371 int npages;
372 int page_shift;
373};
374
375struct mlx4_mtt {
2b8fb286 376 u32 offset;
225c7b1f
RD		 377 int order;
378 int page_shift;
379};
380
6296883c
YP		 381enum {
382 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
383};
384
385struct mlx4_db_pgdir {
386 struct list_head list;
387 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
388 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
389 unsigned long *bits[2];
390 __be32 *db_page;
391 dma_addr_t db_dma;
392};
393
394struct mlx4_ib_user_db_page;
395
396struct mlx4_db {
397 __be32 *db;
398 union {
399 struct mlx4_db_pgdir *pgdir;
400 struct mlx4_ib_user_db_page *user_page;
401 } u;
402 dma_addr_t dma;
403 int index;
404 int order;
405};
406
38ae6a53
YP		 407struct mlx4_hwq_resources {
408 struct mlx4_db db;
409 struct mlx4_mtt mtt;
410 struct mlx4_buf buf;
411};
412
225c7b1f
RD		 413struct mlx4_mr {
414 struct mlx4_mtt mtt;
415 u64 iova;
416 u64 size;
417 u32 key;
418 u32 pd;
419 u32 access;
420 int enabled;
421};
422
8ad11fb6
JM		 423struct mlx4_fmr {
424 struct mlx4_mr mr;
425 struct mlx4_mpt_entry *mpt;
426 __be64 *mtts;
427 dma_addr_t dma_handle;
428 int max_pages;
429 int max_maps;
430 int maps;
431 u8 page_shift;
432};
433
225c7b1f
RD		 434struct mlx4_uar {
435 unsigned long pfn;
436 int index;
c1b43dca
EC		 437 struct list_head bf_list;
438 unsigned free_bf_bmap;
439 void __iomem *map;
440 void __iomem *bf_map;
441};
442
443struct mlx4_bf {
444 unsigned long offset;
445 int buf_size;
446 struct mlx4_uar *uar;
447 void __iomem *reg;
225c7b1f
RD		 448};
449
450struct mlx4_cq {
451 void (*comp) (struct mlx4_cq *);
452 void (*event) (struct mlx4_cq *, enum mlx4_event);
453
454 struct mlx4_uar *uar;
455
456 u32 cons_index;
457
458 __be32 *set_ci_db;
459 __be32 *arm_db;
460 int arm_sn;
461
462 int cqn;
b8dd786f 463 unsigned vector;
225c7b1f
RD		 464
465 atomic_t refcount;
466 struct completion free;
467};
468
469struct mlx4_qp {
470 void (*event) (struct mlx4_qp *, enum mlx4_event);
471
472 int qpn;
473
474 atomic_t refcount;
475 struct completion free;
476};
477
478struct mlx4_srq {
479 void (*event) (struct mlx4_srq *, enum mlx4_event);
480
481 int srqn;
482 int max;
483 int max_gs;
484 int wqe_shift;
485
486 atomic_t refcount;
487 struct completion free;
488};
489
490struct mlx4_av {
491 __be32 port_pd;
492 u8 reserved1;
493 u8 g_slid;
494 __be16 dlid;
495 u8 reserved2;
496 u8 gid_index;
497 u8 stat_rate;
498 u8 hop_limit;
499 __be32 sl_tclass_flowlabel;
500 u8 dgid[16];
501};
502
fa417f7b
EC		 503struct mlx4_eth_av {
504 __be32 port_pd;
505 u8 reserved1;
506 u8 smac_idx;
507 u16 reserved2;
508 u8 reserved3;
509 u8 gid_index;
510 u8 stat_rate;
511 u8 hop_limit;
512 __be32 sl_tclass_flowlabel;
513 u8 dgid[16];
514 u32 reserved4[2];
515 __be16 vlan;
516 u8 mac[6];
517};
518
519union mlx4_ext_av {
520 struct mlx4_av ib;
521 struct mlx4_eth_av eth;
522};
523
f2a3f6a3
OG		 524struct mlx4_counter {
525 u8 reserved1[3];
526 u8 counter_mode;
527 __be32 num_ifc;
528 u32 reserved2[2];
529 __be64 rx_frames;
530 __be64 rx_bytes;
531 __be64 tx_frames;
532 __be64 tx_bytes;
533};
534
225c7b1f
RD		 535struct mlx4_dev {
536 struct pci_dev *pdev;
537 unsigned long flags;
623ed84b 538 unsigned long num_slaves;
225c7b1f 539 struct mlx4_caps caps;
3fc929e2 540 struct mlx4_phys_caps phys_caps;
225c7b1f 541 struct radix_tree_root qp_table_tree;
725c8999 542 u8 rev_id;
cd9281d8 543 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 544 int num_vfs;
225c7b1f
RD		 545};
546
547struct mlx4_init_port_param {
548 int set_guid0;
549 int set_node_guid;
550 int set_si_guid;
551 u16 mtu;
552 int port_width_cap;
553 u16 vl_cap;
554 u16 max_gid;
555 u16 max_pkey;
556 u64 guid0;
557 u64 node_guid;
558 u64 si_guid;
559};
560
7ff93f8b
YP		 561#define mlx4_foreach_port(port, dev, type) \
562 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 563 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 564
65dab25d
JM		 565#define mlx4_foreach_ib_transport_port(port, dev) \
566 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
567 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
568 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b
JM		 569
570static inline int mlx4_is_master(struct mlx4_dev *dev)
571{
572 return dev->flags & MLX4_FLAG_MASTER;
573}
574
575static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
576{
577 return (qpn < dev->caps.sqp_start + 8);
578}
fa417f7b 579
623ed84b
JM		 580static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
581{
582 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
583}
584
585static inline int mlx4_is_slave(struct mlx4_dev *dev)
586{
587 return dev->flags & MLX4_FLAG_SLAVE;
588}
fa417f7b 589
225c7b1f
RD		 590int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
591 struct mlx4_buf *buf);
592void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 593static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
594{
313abe55 595 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 596 return buf->direct.buf + offset;
1c69fc2a 597 else
b57aacfa 598 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 599 (offset & (PAGE_SIZE - 1));
600}
225c7b1f
RD		 601
602int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
603void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 604int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
605void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 606
607int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
608void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 609int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
610void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 611
612int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
613 struct mlx4_mtt *mtt);
614void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
615u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
616
617int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
618 int npages, int page_shift, struct mlx4_mr *mr);
619void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
620int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
621int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
622 int start_index, int npages, u64 *page_list);
623int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
624 struct mlx4_buf *buf);
625
6296883c
YP		 626int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
627void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
628
38ae6a53
YP		 629int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
630 int size, int max_direct);
631void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
632 int size);
633
225c7b1f 634int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 635 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 636 unsigned vector, int collapsed);
225c7b1f
RD		 637void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
638
a3cdcbfa
YP		 639int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
640void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
641
642int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 643void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
644
18abd5ea
SH		 645int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
646 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 647void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
648int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 649int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 650
5ae2a7a8 651int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 652int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
653
ffe455ad
EE		 654int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
655 int block_mcast_loopback, enum mlx4_protocol prot);
656int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
657 enum mlx4_protocol prot);
521e575b 658int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 659 u8 port, int block_mcast_loopback,
660 enum mlx4_protocol protocol, u64 *reg_id);
da995a8a 661int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 662 enum mlx4_protocol protocol, u64 reg_id);
663
664enum {
665 MLX4_DOMAIN_UVERBS = 0x1000,
666 MLX4_DOMAIN_ETHTOOL = 0x2000,
667 MLX4_DOMAIN_RFS = 0x3000,
668 MLX4_DOMAIN_NIC = 0x5000,
669};
670
671enum mlx4_net_trans_rule_id {
672 MLX4_NET_TRANS_RULE_ID_ETH = 0,
673 MLX4_NET_TRANS_RULE_ID_IB,
674 MLX4_NET_TRANS_RULE_ID_IPV6,
675 MLX4_NET_TRANS_RULE_ID_IPV4,
676 MLX4_NET_TRANS_RULE_ID_TCP,
677 MLX4_NET_TRANS_RULE_ID_UDP,
678 MLX4_NET_TRANS_RULE_NUM, /* should be last */
679};
680
681enum mlx4_net_trans_promisc_mode {
682 MLX4_FS_PROMISC_NONE = 0,
683 MLX4_FS_PROMISC_UPLINK,
684 MLX4_FS_PROMISC_FUNCTION_PORT,
685 MLX4_FS_PROMISC_ALL_MULTI,
686};
687
688struct mlx4_spec_eth {
689 u8 dst_mac[6];
690 u8 dst_mac_msk[6];
691 u8 src_mac[6];
692 u8 src_mac_msk[6];
693 u8 ether_type_enable;
694 __be16 ether_type;
695 __be16 vlan_id_msk;
696 __be16 vlan_id;
697};
698
699struct mlx4_spec_tcp_udp {
700 __be16 dst_port;
701 __be16 dst_port_msk;
702 __be16 src_port;
703 __be16 src_port_msk;
704};
705
706struct mlx4_spec_ipv4 {
707 __be32 dst_ip;
708 __be32 dst_ip_msk;
709 __be32 src_ip;
710 __be32 src_ip_msk;
711};
712
713struct mlx4_spec_ib {
714 __be32 r_qpn;
715 __be32 qpn_msk;
716 u8 dst_gid[16];
717 u8 dst_gid_msk[16];
718};
719
720struct mlx4_spec_list {
721 struct list_head list;
722 enum mlx4_net_trans_rule_id id;
723 union {
724 struct mlx4_spec_eth eth;
725 struct mlx4_spec_ib ib;
726 struct mlx4_spec_ipv4 ipv4;
727 struct mlx4_spec_tcp_udp tcp_udp;
728 };
729};
730
731enum mlx4_net_trans_hw_rule_queue {
732 MLX4_NET_TRANS_Q_FIFO,
733 MLX4_NET_TRANS_Q_LIFO,
734};
735
736struct mlx4_net_trans_rule {
737 struct list_head list;
738 enum mlx4_net_trans_hw_rule_queue queue_mode;
739 bool exclusive;
740 bool allow_loopback;
741 enum mlx4_net_trans_promisc_mode promisc_mode;
742 u8 port;
743 u16 priority;
744 u32 qpn;
745};
746
1679200f
YP		 747int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
748int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
749int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
750int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
751int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
752
ffe455ad
EE		 753int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
754void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
755int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
756int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
757void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 758void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
9a9a232a
YP		 759int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
760 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
761int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
762 u8 promisc);
e5395e92
AV		 763int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
764int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
765 u8 *pg, u16 *ratelimit);
4c3eb3ca 766int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 767int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
768void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
769
8ad11fb6
JM		 770int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
771 int npages, u64 iova, u32 *lkey, u32 *rkey);
772int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
773 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
774int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
775void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
776 u32 *lkey, u32 *rkey);
777int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
778int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 779int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9
YP		 780int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
781void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 782
14c07b13
YP		 783int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
784int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
785
f2a3f6a3
OG		 786int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
787void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
788
0ff1fb65
HHZ		 789int mlx4_flow_attach(struct mlx4_dev *dev,
790 struct mlx4_net_trans_rule *rule, u64 *reg_id);
791int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
792
225c7b1f 793#endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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