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mlx4: Put physical GID and P_Key table sizes in mlx4_phys_caps struct and paravirtual...
[deliverable/linux.git] / include / linux / mlx4 / device.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
60063497 40#include <linux/atomic.h>
225c7b1f 41
0b7ca5a9
YP		 42#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
225c7b1f
RD		 47enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 53};
54
55enum {
56 MLX4_MAX_PORTS = 2
57};
58
396f2feb
JM		 59/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
60 * These qkeys must not be allowed for general use. This is a 64k range,
61 * and to test for violation, we use the mask (protect against future chg).
62 */
63#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
64#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
65
cd9281d8
JM		 66enum {
67 MLX4_BOARD_ID_LEN = 64
68};
69
623ed84b
JM		 70enum {
71 MLX4_MAX_NUM_PF = 16,
72 MLX4_MAX_NUM_VF = 64,
73 MLX4_MFUNC_MAX = 80,
3fc929e2 74 MLX4_MAX_EQ_NUM = 1024,
623ed84b
JM		 75 MLX4_MFUNC_EQ_NUM = 4,
76 MLX4_MFUNC_MAX_EQES = 8,
77 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
78};
79
225c7b1f 80enum {
52eafc68
OG		 81 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
82 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
83 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 84 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 85 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
86 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
87 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
88 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
89 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
90 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
91 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
92 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
93 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
94 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
95 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
96 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 97 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
98 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 99 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 100 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
101 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 102 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
103 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 104 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168 105 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
00f5ce99
JM		 106 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
107 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
225c7b1f
RD		 108};
109
b3416f44
SP		 110enum {
111 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
112 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
113 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2
114};
115
97285b78
MA		 116#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
117
95d04f07
RD		 118enum {
119 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
120 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
121 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
122 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
123 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
124};
125
225c7b1f
RD		 126enum mlx4_event {
127 MLX4_EVENT_TYPE_COMP = 0x00,
128 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
129 MLX4_EVENT_TYPE_COMM_EST = 0x02,
130 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
131 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
132 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
133 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
134 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
135 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
136 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
137 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
138 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
139 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
140 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
141 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
142 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
143 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 144 MLX4_EVENT_TYPE_CMD = 0x0a,
145 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
146 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 147 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b 148 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
00f5ce99 149 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
623ed84b 150 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 151};
152
153enum {
154 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
155 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
156};
157
5984be90
JM		 158enum {
159 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
160};
161
225c7b1f
RD		 162enum {
163 MLX4_PERM_LOCAL_READ = 1 << 10,
164 MLX4_PERM_LOCAL_WRITE = 1 << 11,
165 MLX4_PERM_REMOTE_READ = 1 << 12,
166 MLX4_PERM_REMOTE_WRITE = 1 << 13,
167 MLX4_PERM_ATOMIC = 1 << 14
168};
169
170enum {
171 MLX4_OPCODE_NOP = 0x00,
172 MLX4_OPCODE_SEND_INVAL = 0x01,
173 MLX4_OPCODE_RDMA_WRITE = 0x08,
174 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
175 MLX4_OPCODE_SEND = 0x0a,
176 MLX4_OPCODE_SEND_IMM = 0x0b,
177 MLX4_OPCODE_LSO = 0x0e,
178 MLX4_OPCODE_RDMA_READ = 0x10,
179 MLX4_OPCODE_ATOMIC_CS = 0x11,
180 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 181 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
182 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 183 MLX4_OPCODE_BIND_MW = 0x18,
184 MLX4_OPCODE_FMR = 0x19,
185 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
186 MLX4_OPCODE_CONFIG_CMD = 0x1f,
187
188 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
189 MLX4_RECV_OPCODE_SEND = 0x01,
190 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
191 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
192
193 MLX4_CQE_OPCODE_ERROR = 0x1e,
194 MLX4_CQE_OPCODE_RESIZE = 0x16,
195};
196
197enum {
198 MLX4_STAT_RATE_OFFSET = 5
199};
200
da995a8a 201enum mlx4_protocol {
0345584e
YP		 202 MLX4_PROT_IB_IPV6 = 0,
203 MLX4_PROT_ETH,
204 MLX4_PROT_IB_IPV4,
205 MLX4_PROT_FCOE
da995a8a
AS		 206};
207
29bdc883
VS		 208enum {
209 MLX4_MTT_FLAG_PRESENT = 1
210};
211
93fc9e1b
YP		 212enum mlx4_qp_region {
213 MLX4_QP_REGION_FW = 0,
214 MLX4_QP_REGION_ETH_ADDR,
215 MLX4_QP_REGION_FC_ADDR,
216 MLX4_QP_REGION_FC_EXCH,
217 MLX4_NUM_QP_REGION
218};
219
7ff93f8b 220enum mlx4_port_type {
623ed84b 221 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 222 MLX4_PORT_TYPE_IB = 1,
223 MLX4_PORT_TYPE_ETH = 2,
224 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 225};
226
2a2336f8
YP		 227enum mlx4_special_vlan_idx {
228 MLX4_NO_VLAN_IDX = 0,
229 MLX4_VLAN_MISS_IDX,
230 MLX4_VLAN_REGULAR
231};
232
0345584e
YP		 233enum mlx4_steer_type {
234 MLX4_MC_STEER = 0,
235 MLX4_UC_STEER,
236 MLX4_NUM_STEERS
237};
238
93fc9e1b
YP		 239enum {
240 MLX4_NUM_FEXCH = 64 * 1024,
241};
242
5a0fd094
EC		 243enum {
244 MLX4_MAX_FAST_REG_PAGES = 511,
245};
246
00f5ce99
JM		 247enum {
248 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
249 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
250 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
251};
252
253/* Port mgmt change event handling */
254enum {
255 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
256 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
257 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
258 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
259 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
260};
261
262#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
263 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
264
ea54b10c
JM		 265static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
266{
267 return (major << 32) | (minor << 16) | subminor;
268}
269
3fc929e2 270struct mlx4_phys_caps {
6634961c
JM		 271 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
272 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
3fc929e2
MA		 273 u32 num_phys_eqs;
274};
275
225c7b1f
RD		 276struct mlx4_caps {
277 u64 fw_ver;
623ed84b 278 u32 function;
225c7b1f 279 int num_ports;
5ae2a7a8 280 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 281 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 282 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 283 u64 def_mac[MLX4_MAX_PORTS + 1];
284 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 285 int gid_table_len[MLX4_MAX_PORTS + 1];
286 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 287 int trans_type[MLX4_MAX_PORTS + 1];
288 int vendor_oui[MLX4_MAX_PORTS + 1];
289 int wavelength[MLX4_MAX_PORTS + 1];
290 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 291 int local_ca_ack_delay;
292 int num_uars;
f5311ac1 293 u32 uar_page_size;
225c7b1f
RD		 294 int bf_reg_size;
295 int bf_regs_per_page;
296 int max_sq_sg;
297 int max_rq_sg;
298 int num_qps;
299 int max_wqes;
300 int max_sq_desc_sz;
301 int max_rq_desc_sz;
302 int max_qp_init_rdma;
303 int max_qp_dest_rdma;
225c7b1f 304 int sqp_start;
396f2feb
JM		 305 u32 base_sqpn;
306 u32 base_tunnel_sqpn;
225c7b1f
RD		 307 int num_srqs;
308 int max_srq_wqes;
309 int max_srq_sge;
310 int reserved_srqs;
311 int num_cqs;
312 int max_cqes;
313 int reserved_cqs;
314 int num_eqs;
315 int reserved_eqs;
b8dd786f 316 int num_comp_vectors;
0b7ca5a9 317 int comp_pool;
225c7b1f 318 int num_mpts;
a5bbe892 319 int max_fmr_maps;
2b8fb286 320 int num_mtts;
225c7b1f
RD		 321 int fmr_reserved_mtts;
322 int reserved_mtts;
323 int reserved_mrws;
324 int reserved_uars;
325 int num_mgms;
326 int num_amgms;
327 int reserved_mcgs;
328 int num_qp_per_mgm;
329 int num_pds;
330 int reserved_pds;
012a8ff5
SH		 331 int max_xrcds;
332 int reserved_xrcds;
225c7b1f 333 int mtt_entry_sz;
149983af 334 u32 max_msg_sz;
225c7b1f 335 u32 page_size_cap;
52eafc68 336 u64 flags;
b3416f44 337 u64 flags2;
95d04f07
RD		 338 u32 bmme_flags;
339 u32 reserved_lkey;
225c7b1f 340 u16 stat_rate_support;
5ae2a7a8 341 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 342 int max_gso_sz;
b3416f44 343 int max_rss_tbl_sz;
93fc9e1b
YP		 344 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
345 int reserved_qps;
346 int reserved_qps_base[MLX4_NUM_QP_REGION];
347 int log_num_macs;
348 int log_num_vlans;
349 int log_num_prios;
7ff93f8b
YP		 350 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
351 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 352 u8 suggested_type[MLX4_MAX_PORTS + 1];
353 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 354 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 355 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 356 u32 max_counters;
096335b3 357 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 358};
359
360struct mlx4_buf_list {
361 void *buf;
362 dma_addr_t map;
363};
364
365struct mlx4_buf {
b57aacfa
RD		 366 struct mlx4_buf_list direct;
367 struct mlx4_buf_list *page_list;
225c7b1f
RD		 368 int nbufs;
369 int npages;
370 int page_shift;
371};
372
373struct mlx4_mtt {
2b8fb286 374 u32 offset;
225c7b1f
RD		 375 int order;
376 int page_shift;
377};
378
6296883c
YP		 379enum {
380 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
381};
382
383struct mlx4_db_pgdir {
384 struct list_head list;
385 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
386 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
387 unsigned long *bits[2];
388 __be32 *db_page;
389 dma_addr_t db_dma;
390};
391
392struct mlx4_ib_user_db_page;
393
394struct mlx4_db {
395 __be32 *db;
396 union {
397 struct mlx4_db_pgdir *pgdir;
398 struct mlx4_ib_user_db_page *user_page;
399 } u;
400 dma_addr_t dma;
401 int index;
402 int order;
403};
404
38ae6a53
YP		 405struct mlx4_hwq_resources {
406 struct mlx4_db db;
407 struct mlx4_mtt mtt;
408 struct mlx4_buf buf;
409};
410
225c7b1f
RD		 411struct mlx4_mr {
412 struct mlx4_mtt mtt;
413 u64 iova;
414 u64 size;
415 u32 key;
416 u32 pd;
417 u32 access;
418 int enabled;
419};
420
8ad11fb6
JM		 421struct mlx4_fmr {
422 struct mlx4_mr mr;
423 struct mlx4_mpt_entry *mpt;
424 __be64 *mtts;
425 dma_addr_t dma_handle;
426 int max_pages;
427 int max_maps;
428 int maps;
429 u8 page_shift;
430};
431
225c7b1f
RD		 432struct mlx4_uar {
433 unsigned long pfn;
434 int index;
c1b43dca
EC		 435 struct list_head bf_list;
436 unsigned free_bf_bmap;
437 void __iomem *map;
438 void __iomem *bf_map;
439};
440
441struct mlx4_bf {
442 unsigned long offset;
443 int buf_size;
444 struct mlx4_uar *uar;
445 void __iomem *reg;
225c7b1f
RD		 446};
447
448struct mlx4_cq {
449 void (*comp) (struct mlx4_cq *);
450 void (*event) (struct mlx4_cq *, enum mlx4_event);
451
452 struct mlx4_uar *uar;
453
454 u32 cons_index;
455
456 __be32 *set_ci_db;
457 __be32 *arm_db;
458 int arm_sn;
459
460 int cqn;
b8dd786f 461 unsigned vector;
225c7b1f
RD		 462
463 atomic_t refcount;
464 struct completion free;
465};
466
467struct mlx4_qp {
468 void (*event) (struct mlx4_qp *, enum mlx4_event);
469
470 int qpn;
471
472 atomic_t refcount;
473 struct completion free;
474};
475
476struct mlx4_srq {
477 void (*event) (struct mlx4_srq *, enum mlx4_event);
478
479 int srqn;
480 int max;
481 int max_gs;
482 int wqe_shift;
483
484 atomic_t refcount;
485 struct completion free;
486};
487
488struct mlx4_av {
489 __be32 port_pd;
490 u8 reserved1;
491 u8 g_slid;
492 __be16 dlid;
493 u8 reserved2;
494 u8 gid_index;
495 u8 stat_rate;
496 u8 hop_limit;
497 __be32 sl_tclass_flowlabel;
498 u8 dgid[16];
499};
500
fa417f7b
EC		 501struct mlx4_eth_av {
502 __be32 port_pd;
503 u8 reserved1;
504 u8 smac_idx;
505 u16 reserved2;
506 u8 reserved3;
507 u8 gid_index;
508 u8 stat_rate;
509 u8 hop_limit;
510 __be32 sl_tclass_flowlabel;
511 u8 dgid[16];
512 u32 reserved4[2];
513 __be16 vlan;
514 u8 mac[6];
515};
516
517union mlx4_ext_av {
518 struct mlx4_av ib;
519 struct mlx4_eth_av eth;
520};
521
f2a3f6a3
OG		 522struct mlx4_counter {
523 u8 reserved1[3];
524 u8 counter_mode;
525 __be32 num_ifc;
526 u32 reserved2[2];
527 __be64 rx_frames;
528 __be64 rx_bytes;
529 __be64 tx_frames;
530 __be64 tx_bytes;
531};
532
225c7b1f
RD		 533struct mlx4_dev {
534 struct pci_dev *pdev;
535 unsigned long flags;
623ed84b 536 unsigned long num_slaves;
225c7b1f 537 struct mlx4_caps caps;
3fc929e2 538 struct mlx4_phys_caps phys_caps;
225c7b1f 539 struct radix_tree_root qp_table_tree;
725c8999 540 u8 rev_id;
cd9281d8 541 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 542 int num_vfs;
225c7b1f
RD		 543};
544
00f5ce99
JM		 545struct mlx4_eqe {
546 u8 reserved1;
547 u8 type;
548 u8 reserved2;
549 u8 subtype;
550 union {
551 u32 raw[6];
552 struct {
553 __be32 cqn;
554 } __packed comp;
555 struct {
556 u16 reserved1;
557 __be16 token;
558 u32 reserved2;
559 u8 reserved3[3];
560 u8 status;
561 __be64 out_param;
562 } __packed cmd;
563 struct {
564 __be32 qpn;
565 } __packed qp;
566 struct {
567 __be32 srqn;
568 } __packed srq;
569 struct {
570 __be32 cqn;
571 u32 reserved1;
572 u8 reserved2[3];
573 u8 syndrome;
574 } __packed cq_err;
575 struct {
576 u32 reserved1[2];
577 __be32 port;
578 } __packed port_change;
579 struct {
580 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
581 u32 reserved;
582 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
583 } __packed comm_channel_arm;
584 struct {
585 u8 port;
586 u8 reserved[3];
587 __be64 mac;
588 } __packed mac_update;
589 struct {
590 __be32 slave_id;
591 } __packed flr_event;
592 struct {
593 __be16 current_temperature;
594 __be16 warning_threshold;
595 } __packed warming;
596 struct {
597 u8 reserved[3];
598 u8 port;
599 union {
600 struct {
601 __be16 mstr_sm_lid;
602 __be16 port_lid;
603 __be32 changed_attr;
604 u8 reserved[3];
605 u8 mstr_sm_sl;
606 __be64 gid_prefix;
607 } __packed port_info;
608 struct {
609 __be32 block_ptr;
610 __be32 tbl_entries_mask;
611 } __packed tbl_change_info;
612 } params;
613 } __packed port_mgmt_change;
614 } event;
615 u8 slave_id;
616 u8 reserved3[2];
617 u8 owner;
618} __packed;
619
225c7b1f
RD		 620struct mlx4_init_port_param {
621 int set_guid0;
622 int set_node_guid;
623 int set_si_guid;
624 u16 mtu;
625 int port_width_cap;
626 u16 vl_cap;
627 u16 max_gid;
628 u16 max_pkey;
629 u64 guid0;
630 u64 node_guid;
631 u64 si_guid;
632};
633
7ff93f8b
YP		 634#define mlx4_foreach_port(port, dev, type) \
635 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 636 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 637
65dab25d
JM		 638#define mlx4_foreach_ib_transport_port(port, dev) \
639 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
640 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
641 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b 642
752a50ca
JM		 643#define MLX4_INVALID_SLAVE_ID 0xFF
644
00f5ce99
JM		 645void handle_port_mgmt_change_event(struct work_struct *work);
646
2aca1172
JM		 647static inline int mlx4_master_func_num(struct mlx4_dev *dev)
648{
649 return dev->caps.function;
650}
651
623ed84b
JM		 652static inline int mlx4_is_master(struct mlx4_dev *dev)
653{
654 return dev->flags & MLX4_FLAG_MASTER;
655}
656
657static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
658{
659 return (qpn < dev->caps.sqp_start + 8);
660}
fa417f7b 661
623ed84b
JM		 662static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
663{
664 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
665}
666
667static inline int mlx4_is_slave(struct mlx4_dev *dev)
668{
669 return dev->flags & MLX4_FLAG_SLAVE;
670}
fa417f7b 671
225c7b1f
RD		 672int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
673 struct mlx4_buf *buf);
674void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 675static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
676{
313abe55 677 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 678 return buf->direct.buf + offset;
1c69fc2a 679 else
b57aacfa 680 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 681 (offset & (PAGE_SIZE - 1));
682}
225c7b1f
RD		 683
684int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
685void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 686int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
687void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 688
689int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
690void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 691int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
692void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 693
694int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
695 struct mlx4_mtt *mtt);
696void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
697u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
698
699int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
700 int npages, int page_shift, struct mlx4_mr *mr);
701void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
702int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
703int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
704 int start_index, int npages, u64 *page_list);
705int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
706 struct mlx4_buf *buf);
707
6296883c
YP		 708int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
709void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
710
38ae6a53
YP		 711int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
712 int size, int max_direct);
713void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
714 int size);
715
225c7b1f 716int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 717 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 718 unsigned vector, int collapsed);
225c7b1f
RD		 719void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
720
a3cdcbfa
YP		 721int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
722void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
723
724int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 725void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
726
18abd5ea
SH		 727int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
728 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 729void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
730int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 731int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 732
5ae2a7a8 733int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 734int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
735
ffe455ad
EE		 736int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
737 int block_mcast_loopback, enum mlx4_protocol prot);
738int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
739 enum mlx4_protocol prot);
521e575b 740int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
da995a8a
AS		 741 int block_mcast_loopback, enum mlx4_protocol protocol);
742int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
743 enum mlx4_protocol protocol);
1679200f
YP		 744int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
745int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
746int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
747int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
748int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
749
ffe455ad
EE		 750int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
751void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
752int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
753int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
754void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 755void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
9a9a232a
YP		 756int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
757 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
758int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
759 u8 promisc);
e5395e92
AV		 760int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
761int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
762 u8 *pg, u16 *ratelimit);
4c3eb3ca 763int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 764int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
765void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
766
8ad11fb6
JM		 767int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
768 int npages, u64 iova, u32 *lkey, u32 *rkey);
769int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
770 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
771int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
772void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
773 u32 *lkey, u32 *rkey);
774int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
775int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 776int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9
YP		 777int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
778void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 779
14c07b13
YP		 780int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
781int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
782
f2a3f6a3
OG		 783int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
784void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
785
396f2feb
JM		 786int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
787
225c7b1f 788#endif /* MLX4_DEVICE_H */
Linux kernel - Deliverables
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