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1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_CORE_CQ_H | |
34 | #define MLX5_CORE_CQ_H | |
35 | ||
36 | #include <rdma/ib_verbs.h> | |
37 | #include <linux/mlx5/driver.h> | |
38 | ||
39 | ||
40 | struct mlx5_core_cq { | |
41 | u32 cqn; | |
42 | int cqe_sz; | |
43 | __be32 *set_ci_db; | |
44 | __be32 *arm_db; | |
45 | atomic_t refcount; | |
46 | struct completion free; | |
47 | unsigned vector; | |
48 | int irqn; | |
49 | void (*comp) (struct mlx5_core_cq *); | |
50 | void (*event) (struct mlx5_core_cq *, enum mlx5_event); | |
51 | struct mlx5_uar *uar; | |
52 | u32 cons_index; | |
53 | unsigned arm_sn; | |
54 | struct mlx5_rsc_debug *dbg; | |
55 | int pid; | |
56 | }; | |
57 | ||
58 | ||
59 | enum { | |
60 | MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01, | |
61 | MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02, | |
62 | MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04, | |
63 | MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05, | |
64 | MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06, | |
65 | MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10, | |
66 | MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11, | |
67 | MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, | |
68 | MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13, | |
69 | MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14, | |
70 | MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15, | |
71 | MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16, | |
72 | MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MLX5_CQE_OWNER_MASK = 1, | |
77 | MLX5_CQE_REQ = 0, | |
78 | MLX5_CQE_RESP_WR_IMM = 1, | |
79 | MLX5_CQE_RESP_SEND = 2, | |
80 | MLX5_CQE_RESP_SEND_IMM = 3, | |
81 | MLX5_CQE_RESP_SEND_INV = 4, | |
82 | MLX5_CQE_RESIZE_CQ = 0xff, /* TBD */ | |
83 | MLX5_CQE_REQ_ERR = 13, | |
84 | MLX5_CQE_RESP_ERR = 14, | |
85 | }; | |
86 | ||
87 | enum { | |
88 | MLX5_CQ_MODIFY_RESEIZE = 0, | |
89 | MLX5_CQ_MODIFY_MODER = 1, | |
90 | MLX5_CQ_MODIFY_MAPPING = 2, | |
91 | }; | |
92 | ||
93 | struct mlx5_cq_modify_params { | |
94 | int type; | |
95 | union { | |
96 | struct { | |
97 | u32 page_offset; | |
98 | u8 log_cq_size; | |
99 | } resize; | |
100 | ||
101 | struct { | |
102 | } moder; | |
103 | ||
104 | struct { | |
105 | } mapping; | |
106 | } params; | |
107 | }; | |
108 | ||
109 | enum { | |
110 | CQE_SIZE_64 = 0, | |
111 | CQE_SIZE_128 = 1, | |
112 | }; | |
113 | ||
114 | static inline int cqe_sz_to_mlx_sz(u8 size) | |
115 | { | |
116 | return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128; | |
117 | } | |
118 | ||
119 | static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq) | |
120 | { | |
121 | *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff); | |
122 | } | |
123 | ||
124 | enum { | |
125 | MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24, | |
126 | MLX5_CQ_DB_REQ_NOT = 0 << 24 | |
127 | }; | |
128 | ||
129 | static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd, | |
130 | void __iomem *uar_page, | |
131 | spinlock_t *doorbell_lock) | |
132 | { | |
133 | __be32 doorbell[2]; | |
134 | u32 sn; | |
135 | u32 ci; | |
136 | ||
137 | sn = cq->arm_sn & 3; | |
138 | ci = cq->cons_index & 0xffffff; | |
139 | ||
140 | *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci); | |
141 | ||
142 | /* Make sure that the doorbell record in host memory is | |
143 | * written before ringing the doorbell via PCI MMIO. | |
144 | */ | |
145 | wmb(); | |
146 | ||
147 | doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci); | |
148 | doorbell[1] = cpu_to_be32(cq->cqn); | |
149 | ||
150 | mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock); | |
151 | } | |
152 | ||
153 | int mlx5_init_cq_table(struct mlx5_core_dev *dev); | |
154 | void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev); | |
155 | int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | |
156 | struct mlx5_create_cq_mbox_in *in, int inlen); | |
157 | int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | |
158 | int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | |
159 | struct mlx5_query_cq_mbox_out *out); | |
160 | int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | |
161 | int type, struct mlx5_cq_modify_params *params); | |
162 | int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | |
163 | void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); | |
164 | ||
165 | #endif /* MLX5_CORE_CQ_H */ |