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e126ba97 EC |
1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
38 | ||
39 | #if defined(__LITTLE_ENDIAN) | |
40 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
41 | #elif defined(__BIG_ENDIAN) | |
42 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
43 | #else | |
44 | #error Host endianness not defined | |
45 | #endif | |
46 | ||
47 | enum { | |
48 | MLX5_MAX_COMMANDS = 32, | |
49 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
50 | MLX5_PCI_CMD_XPORT = 7, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
55 | }; | |
56 | ||
57 | enum { | |
58 | MLX5_CQ_STATE_ARMED = 9, | |
59 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
60 | MLX5_CQ_STATE_FIRED = 0xa, | |
61 | }; | |
62 | ||
63 | enum { | |
64 | MLX5_STAT_RATE_OFFSET = 5, | |
65 | }; | |
66 | ||
67 | enum { | |
68 | MLX5_INLINE_SEG = 0x80000000, | |
69 | }; | |
70 | ||
71 | enum { | |
72 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
73 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
74 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
75 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
76 | MLX5_PERM_ATOMIC = 1 << 6, | |
77 | MLX5_PERM_UMR_EN = 1 << 7, | |
78 | }; | |
79 | ||
80 | enum { | |
81 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
82 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
83 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
84 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
85 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
86 | }; | |
87 | ||
88 | enum { | |
89 | MLX5_ACCESS_MODE_PA = 0, | |
90 | MLX5_ACCESS_MODE_MTT = 1, | |
91 | MLX5_ACCESS_MODE_KLM = 2 | |
92 | }; | |
93 | ||
94 | enum { | |
95 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
96 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
97 | MLX5_MKEY_BSF_EN = 1 << 30, | |
98 | MLX5_MKEY_LEN64 = 1 << 31, | |
99 | }; | |
100 | ||
101 | enum { | |
102 | MLX5_EN_RD = (u64)1, | |
103 | MLX5_EN_WR = (u64)2 | |
104 | }; | |
105 | ||
106 | enum { | |
c1be5232 EC |
107 | MLX5_BF_REGS_PER_PAGE = 4, |
108 | MLX5_MAX_UAR_PAGES = 1 << 8, | |
109 | MLX5_NON_FP_BF_REGS_PER_PAGE = 2, | |
110 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, | |
e126ba97 EC |
111 | }; |
112 | ||
113 | enum { | |
114 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
115 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
116 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
117 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
118 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
119 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, | |
120 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
121 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
122 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
123 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
124 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
125 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
126 | MLX5_MKEY_MASK_A = 1ull << 21, | |
127 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
128 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
129 | }; | |
130 | ||
131 | enum mlx5_event { | |
132 | MLX5_EVENT_TYPE_COMP = 0x0, | |
133 | ||
134 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, | |
135 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
136 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
137 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
138 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
139 | ||
140 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
141 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
142 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
143 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
144 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
145 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
146 | ||
147 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
148 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
149 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
150 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | |
151 | ||
152 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
153 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
154 | ||
155 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
156 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
157 | }; | |
158 | ||
159 | enum { | |
160 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
161 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
162 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
163 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
164 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
165 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
166 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
167 | }; | |
168 | ||
169 | enum { | |
170 | MLX5_DEV_CAP_FLAG_RC = 1LL << 0, | |
171 | MLX5_DEV_CAP_FLAG_UC = 1LL << 1, | |
172 | MLX5_DEV_CAP_FLAG_UD = 1LL << 2, | |
173 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, | |
174 | MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6, | |
175 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
176 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
177 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
178 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
179 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, | |
3bdb31f6 | 180 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, |
e126ba97 EC |
181 | MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, |
182 | MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, | |
183 | MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, | |
184 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, | |
185 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 41, | |
c1868b82 | 186 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, |
e126ba97 EC |
187 | }; |
188 | ||
189 | enum { | |
190 | MLX5_OPCODE_NOP = 0x00, | |
191 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
192 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
193 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
194 | MLX5_OPCODE_SEND = 0x0a, | |
195 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
196 | MLX5_OPCODE_RDMA_READ = 0x10, | |
197 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
198 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
199 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
200 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
201 | MLX5_OPCODE_BIND_MW = 0x18, | |
202 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
203 | ||
204 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
205 | MLX5_RECV_OPCODE_SEND = 0x01, | |
206 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
207 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
208 | ||
209 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
210 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
211 | ||
212 | MLX5_OPCODE_SET_PSV = 0x20, | |
213 | MLX5_OPCODE_GET_PSV = 0x21, | |
214 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
215 | MLX5_OPCODE_RGET_PSV = 0x26, | |
216 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
217 | ||
218 | MLX5_OPCODE_UMR = 0x25, | |
219 | ||
220 | }; | |
221 | ||
222 | enum { | |
223 | MLX5_SET_PORT_RESET_QKEY = 0, | |
224 | MLX5_SET_PORT_GUID0 = 16, | |
225 | MLX5_SET_PORT_NODE_GUID = 17, | |
226 | MLX5_SET_PORT_SYS_GUID = 18, | |
227 | MLX5_SET_PORT_GID_TABLE = 19, | |
228 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
229 | }; | |
230 | ||
231 | enum { | |
232 | MLX5_MAX_PAGE_SHIFT = 31 | |
233 | }; | |
234 | ||
1b77d2bd EC |
235 | enum { |
236 | MLX5_ADAPTER_PAGE_SHIFT = 12 | |
237 | }; | |
238 | ||
87b8de49 EC |
239 | enum { |
240 | MLX5_CAP_OFF_DCT = 41, | |
241 | MLX5_CAP_OFF_CMDIF_CSUM = 46, | |
242 | }; | |
243 | ||
e126ba97 EC |
244 | struct mlx5_inbox_hdr { |
245 | __be16 opcode; | |
246 | u8 rsvd[4]; | |
247 | __be16 opmod; | |
248 | }; | |
249 | ||
250 | struct mlx5_outbox_hdr { | |
251 | u8 status; | |
252 | u8 rsvd[3]; | |
253 | __be32 syndrome; | |
254 | }; | |
255 | ||
256 | struct mlx5_cmd_query_adapter_mbox_in { | |
257 | struct mlx5_inbox_hdr hdr; | |
258 | u8 rsvd[8]; | |
259 | }; | |
260 | ||
261 | struct mlx5_cmd_query_adapter_mbox_out { | |
262 | struct mlx5_outbox_hdr hdr; | |
263 | u8 rsvd0[24]; | |
264 | u8 intapin; | |
265 | u8 rsvd1[13]; | |
266 | __be16 vsd_vendor_id; | |
267 | u8 vsd[208]; | |
268 | u8 vsd_psid[16]; | |
269 | }; | |
270 | ||
271 | struct mlx5_hca_cap { | |
272 | u8 rsvd1[16]; | |
273 | u8 log_max_srq_sz; | |
274 | u8 log_max_qp_sz; | |
275 | u8 rsvd2; | |
276 | u8 log_max_qp; | |
277 | u8 log_max_strq_sz; | |
278 | u8 log_max_srqs; | |
279 | u8 rsvd4[2]; | |
280 | u8 rsvd5; | |
281 | u8 log_max_cq_sz; | |
282 | u8 rsvd6; | |
283 | u8 log_max_cq; | |
284 | u8 log_max_eq_sz; | |
285 | u8 log_max_mkey; | |
286 | u8 rsvd7; | |
287 | u8 log_max_eq; | |
288 | u8 max_indirection; | |
289 | u8 log_max_mrw_sz; | |
290 | u8 log_max_bsf_list_sz; | |
291 | u8 log_max_klm_list_sz; | |
292 | u8 rsvd_8_0; | |
293 | u8 log_max_ra_req_dc; | |
294 | u8 rsvd_8_1; | |
295 | u8 log_max_ra_res_dc; | |
296 | u8 rsvd9; | |
297 | u8 log_max_ra_req_qp; | |
298 | u8 rsvd10; | |
299 | u8 log_max_ra_res_qp; | |
300 | u8 rsvd11[4]; | |
301 | __be16 max_qp_count; | |
302 | __be16 rsvd12; | |
303 | u8 rsvd13; | |
304 | u8 local_ca_ack_delay; | |
305 | u8 rsvd14; | |
306 | u8 num_ports; | |
307 | u8 log_max_msg; | |
308 | u8 rsvd15[3]; | |
309 | __be16 stat_rate_support; | |
310 | u8 rsvd16[2]; | |
311 | __be64 flags; | |
312 | u8 rsvd17; | |
313 | u8 uar_sz; | |
314 | u8 rsvd18; | |
315 | u8 log_pg_sz; | |
316 | __be16 bf_log_bf_reg_size; | |
317 | u8 rsvd19[4]; | |
318 | __be16 max_desc_sz_sq; | |
319 | u8 rsvd20[2]; | |
320 | __be16 max_desc_sz_rq; | |
321 | u8 rsvd21[2]; | |
322 | __be16 max_desc_sz_sq_dc; | |
0a324f31 ML |
323 | __be32 max_qp_mcg; |
324 | u8 rsvd22[3]; | |
e126ba97 | 325 | u8 log_max_mcg; |
0a324f31 | 326 | u8 rsvd23; |
e126ba97 | 327 | u8 log_max_pd; |
0a324f31 | 328 | u8 rsvd24; |
e126ba97 | 329 | u8 log_max_xrcd; |
0a324f31 | 330 | u8 rsvd25[42]; |
288dde9f | 331 | __be16 log_uar_page_sz; |
0a324f31 | 332 | u8 rsvd26[28]; |
87b8de49 | 333 | u8 log_max_atomic_size_qp; |
0a324f31 | 334 | u8 rsvd27[2]; |
87b8de49 | 335 | u8 log_max_atomic_size_dc; |
0a324f31 | 336 | u8 rsvd28[76]; |
e126ba97 EC |
337 | }; |
338 | ||
339 | ||
340 | struct mlx5_cmd_query_hca_cap_mbox_in { | |
341 | struct mlx5_inbox_hdr hdr; | |
342 | u8 rsvd[8]; | |
343 | }; | |
344 | ||
345 | ||
346 | struct mlx5_cmd_query_hca_cap_mbox_out { | |
347 | struct mlx5_outbox_hdr hdr; | |
348 | u8 rsvd0[8]; | |
349 | struct mlx5_hca_cap hca_cap; | |
350 | }; | |
351 | ||
352 | ||
353 | struct mlx5_cmd_set_hca_cap_mbox_in { | |
354 | struct mlx5_inbox_hdr hdr; | |
355 | u8 rsvd[8]; | |
356 | struct mlx5_hca_cap hca_cap; | |
357 | }; | |
358 | ||
359 | ||
360 | struct mlx5_cmd_set_hca_cap_mbox_out { | |
361 | struct mlx5_outbox_hdr hdr; | |
362 | u8 rsvd0[8]; | |
363 | }; | |
364 | ||
365 | ||
366 | struct mlx5_cmd_init_hca_mbox_in { | |
367 | struct mlx5_inbox_hdr hdr; | |
368 | u8 rsvd0[2]; | |
369 | __be16 profile; | |
370 | u8 rsvd1[4]; | |
371 | }; | |
372 | ||
373 | struct mlx5_cmd_init_hca_mbox_out { | |
374 | struct mlx5_outbox_hdr hdr; | |
375 | u8 rsvd[8]; | |
376 | }; | |
377 | ||
378 | struct mlx5_cmd_teardown_hca_mbox_in { | |
379 | struct mlx5_inbox_hdr hdr; | |
380 | u8 rsvd0[2]; | |
381 | __be16 profile; | |
382 | u8 rsvd1[4]; | |
383 | }; | |
384 | ||
385 | struct mlx5_cmd_teardown_hca_mbox_out { | |
386 | struct mlx5_outbox_hdr hdr; | |
387 | u8 rsvd[8]; | |
388 | }; | |
389 | ||
390 | struct mlx5_cmd_layout { | |
391 | u8 type; | |
392 | u8 rsvd0[3]; | |
393 | __be32 inlen; | |
394 | __be64 in_ptr; | |
395 | __be32 in[4]; | |
396 | __be32 out[4]; | |
397 | __be64 out_ptr; | |
398 | __be32 outlen; | |
399 | u8 token; | |
400 | u8 sig; | |
401 | u8 rsvd1; | |
402 | u8 status_own; | |
403 | }; | |
404 | ||
405 | ||
406 | struct health_buffer { | |
407 | __be32 assert_var[5]; | |
408 | __be32 rsvd0[3]; | |
409 | __be32 assert_exit_ptr; | |
410 | __be32 assert_callra; | |
411 | __be32 rsvd1[2]; | |
412 | __be32 fw_ver; | |
413 | __be32 hw_id; | |
414 | __be32 rsvd2; | |
415 | u8 irisc_index; | |
416 | u8 synd; | |
417 | __be16 ext_sync; | |
418 | }; | |
419 | ||
420 | struct mlx5_init_seg { | |
421 | __be32 fw_rev; | |
422 | __be32 cmdif_rev_fw_sub; | |
423 | __be32 rsvd0[2]; | |
424 | __be32 cmdq_addr_h; | |
425 | __be32 cmdq_addr_l_sz; | |
426 | __be32 cmd_dbell; | |
427 | __be32 rsvd1[121]; | |
428 | struct health_buffer health; | |
429 | __be32 rsvd2[884]; | |
430 | __be32 health_counter; | |
2f6daec1 | 431 | __be32 rsvd3[1019]; |
e126ba97 EC |
432 | __be64 ieee1588_clk; |
433 | __be32 ieee1588_clk_type; | |
434 | __be32 clr_intx; | |
435 | }; | |
436 | ||
437 | struct mlx5_eqe_comp { | |
438 | __be32 reserved[6]; | |
439 | __be32 cqn; | |
440 | }; | |
441 | ||
442 | struct mlx5_eqe_qp_srq { | |
443 | __be32 reserved[6]; | |
444 | __be32 qp_srq_n; | |
445 | }; | |
446 | ||
447 | struct mlx5_eqe_cq_err { | |
448 | __be32 cqn; | |
449 | u8 reserved1[7]; | |
450 | u8 syndrome; | |
451 | }; | |
452 | ||
453 | struct mlx5_eqe_dropped_packet { | |
454 | }; | |
455 | ||
456 | struct mlx5_eqe_port_state { | |
457 | u8 reserved0[8]; | |
458 | u8 port; | |
459 | }; | |
460 | ||
461 | struct mlx5_eqe_gpio { | |
462 | __be32 reserved0[2]; | |
463 | __be64 gpio_event; | |
464 | }; | |
465 | ||
466 | struct mlx5_eqe_congestion { | |
467 | u8 type; | |
468 | u8 rsvd0; | |
469 | u8 congestion_level; | |
470 | }; | |
471 | ||
472 | struct mlx5_eqe_stall_vl { | |
473 | u8 rsvd0[3]; | |
474 | u8 port_vl; | |
475 | }; | |
476 | ||
477 | struct mlx5_eqe_cmd { | |
478 | __be32 vector; | |
479 | __be32 rsvd[6]; | |
480 | }; | |
481 | ||
482 | struct mlx5_eqe_page_req { | |
483 | u8 rsvd0[2]; | |
484 | __be16 func_id; | |
0a324f31 ML |
485 | __be32 num_pages; |
486 | __be32 rsvd1[5]; | |
e126ba97 EC |
487 | }; |
488 | ||
489 | union ev_data { | |
490 | __be32 raw[7]; | |
491 | struct mlx5_eqe_cmd cmd; | |
492 | struct mlx5_eqe_comp comp; | |
493 | struct mlx5_eqe_qp_srq qp_srq; | |
494 | struct mlx5_eqe_cq_err cq_err; | |
495 | struct mlx5_eqe_dropped_packet dp; | |
496 | struct mlx5_eqe_port_state port; | |
497 | struct mlx5_eqe_gpio gpio; | |
498 | struct mlx5_eqe_congestion cong; | |
499 | struct mlx5_eqe_stall_vl stall_vl; | |
500 | struct mlx5_eqe_page_req req_pages; | |
501 | } __packed; | |
502 | ||
503 | struct mlx5_eqe { | |
504 | u8 rsvd0; | |
505 | u8 type; | |
506 | u8 rsvd1; | |
507 | u8 sub_type; | |
508 | __be32 rsvd2[7]; | |
509 | union ev_data data; | |
510 | __be16 rsvd3; | |
511 | u8 signature; | |
512 | u8 owner; | |
513 | } __packed; | |
514 | ||
515 | struct mlx5_cmd_prot_block { | |
516 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
517 | u8 rsvd0[48]; | |
518 | __be64 next; | |
519 | __be32 block_num; | |
520 | u8 rsvd1; | |
521 | u8 token; | |
522 | u8 ctrl_sig; | |
523 | u8 sig; | |
524 | }; | |
525 | ||
526 | struct mlx5_err_cqe { | |
527 | u8 rsvd0[32]; | |
528 | __be32 srqn; | |
529 | u8 rsvd1[18]; | |
530 | u8 vendor_err_synd; | |
531 | u8 syndrome; | |
532 | __be32 s_wqe_opcode_qpn; | |
533 | __be16 wqe_counter; | |
534 | u8 signature; | |
535 | u8 op_own; | |
536 | }; | |
537 | ||
538 | struct mlx5_cqe64 { | |
539 | u8 rsvd0[17]; | |
540 | u8 ml_path; | |
541 | u8 rsvd20[4]; | |
542 | __be16 slid; | |
543 | __be32 flags_rqpn; | |
544 | u8 rsvd28[4]; | |
545 | __be32 srqn; | |
546 | __be32 imm_inval_pkey; | |
547 | u8 rsvd40[4]; | |
548 | __be32 byte_cnt; | |
549 | __be64 timestamp; | |
550 | __be32 sop_drop_qpn; | |
551 | __be16 wqe_counter; | |
552 | u8 signature; | |
553 | u8 op_own; | |
554 | }; | |
555 | ||
556 | struct mlx5_wqe_srq_next_seg { | |
557 | u8 rsvd0[2]; | |
558 | __be16 next_wqe_index; | |
559 | u8 signature; | |
560 | u8 rsvd1[11]; | |
561 | }; | |
562 | ||
563 | union mlx5_ext_cqe { | |
564 | struct ib_grh grh; | |
565 | u8 inl[64]; | |
566 | }; | |
567 | ||
568 | struct mlx5_cqe128 { | |
569 | union mlx5_ext_cqe inl_grh; | |
570 | struct mlx5_cqe64 cqe64; | |
571 | }; | |
572 | ||
573 | struct mlx5_srq_ctx { | |
574 | u8 state_log_sz; | |
575 | u8 rsvd0[3]; | |
576 | __be32 flags_xrcd; | |
577 | __be32 pgoff_cqn; | |
578 | u8 rsvd1[4]; | |
579 | u8 log_pg_sz; | |
580 | u8 rsvd2[7]; | |
581 | __be32 pd; | |
582 | __be16 lwm; | |
583 | __be16 wqe_cnt; | |
584 | u8 rsvd3[8]; | |
585 | __be64 db_record; | |
586 | }; | |
587 | ||
588 | struct mlx5_create_srq_mbox_in { | |
589 | struct mlx5_inbox_hdr hdr; | |
590 | __be32 input_srqn; | |
591 | u8 rsvd0[4]; | |
592 | struct mlx5_srq_ctx ctx; | |
593 | u8 rsvd1[208]; | |
594 | __be64 pas[0]; | |
595 | }; | |
596 | ||
597 | struct mlx5_create_srq_mbox_out { | |
598 | struct mlx5_outbox_hdr hdr; | |
599 | __be32 srqn; | |
600 | u8 rsvd[4]; | |
601 | }; | |
602 | ||
603 | struct mlx5_destroy_srq_mbox_in { | |
604 | struct mlx5_inbox_hdr hdr; | |
605 | __be32 srqn; | |
606 | u8 rsvd[4]; | |
607 | }; | |
608 | ||
609 | struct mlx5_destroy_srq_mbox_out { | |
610 | struct mlx5_outbox_hdr hdr; | |
611 | u8 rsvd[8]; | |
612 | }; | |
613 | ||
614 | struct mlx5_query_srq_mbox_in { | |
615 | struct mlx5_inbox_hdr hdr; | |
616 | __be32 srqn; | |
617 | u8 rsvd0[4]; | |
618 | }; | |
619 | ||
620 | struct mlx5_query_srq_mbox_out { | |
621 | struct mlx5_outbox_hdr hdr; | |
622 | u8 rsvd0[8]; | |
623 | struct mlx5_srq_ctx ctx; | |
624 | u8 rsvd1[32]; | |
625 | __be64 pas[0]; | |
626 | }; | |
627 | ||
628 | struct mlx5_arm_srq_mbox_in { | |
629 | struct mlx5_inbox_hdr hdr; | |
630 | __be32 srqn; | |
631 | __be16 rsvd; | |
632 | __be16 lwm; | |
633 | }; | |
634 | ||
635 | struct mlx5_arm_srq_mbox_out { | |
636 | struct mlx5_outbox_hdr hdr; | |
637 | u8 rsvd[8]; | |
638 | }; | |
639 | ||
640 | struct mlx5_cq_context { | |
641 | u8 status; | |
642 | u8 cqe_sz_flags; | |
643 | u8 st; | |
644 | u8 rsvd3; | |
645 | u8 rsvd4[6]; | |
646 | __be16 page_offset; | |
647 | __be32 log_sz_usr_page; | |
648 | __be16 cq_period; | |
649 | __be16 cq_max_count; | |
650 | __be16 rsvd20; | |
651 | __be16 c_eqn; | |
652 | u8 log_pg_sz; | |
653 | u8 rsvd25[7]; | |
654 | __be32 last_notified_index; | |
655 | __be32 solicit_producer_index; | |
656 | __be32 consumer_counter; | |
657 | __be32 producer_counter; | |
658 | u8 rsvd48[8]; | |
659 | __be64 db_record_addr; | |
660 | }; | |
661 | ||
662 | struct mlx5_create_cq_mbox_in { | |
663 | struct mlx5_inbox_hdr hdr; | |
664 | __be32 input_cqn; | |
665 | u8 rsvdx[4]; | |
666 | struct mlx5_cq_context ctx; | |
667 | u8 rsvd6[192]; | |
668 | __be64 pas[0]; | |
669 | }; | |
670 | ||
671 | struct mlx5_create_cq_mbox_out { | |
672 | struct mlx5_outbox_hdr hdr; | |
673 | __be32 cqn; | |
674 | u8 rsvd0[4]; | |
675 | }; | |
676 | ||
677 | struct mlx5_destroy_cq_mbox_in { | |
678 | struct mlx5_inbox_hdr hdr; | |
679 | __be32 cqn; | |
680 | u8 rsvd0[4]; | |
681 | }; | |
682 | ||
683 | struct mlx5_destroy_cq_mbox_out { | |
684 | struct mlx5_outbox_hdr hdr; | |
685 | u8 rsvd0[8]; | |
686 | }; | |
687 | ||
688 | struct mlx5_query_cq_mbox_in { | |
689 | struct mlx5_inbox_hdr hdr; | |
690 | __be32 cqn; | |
691 | u8 rsvd0[4]; | |
692 | }; | |
693 | ||
694 | struct mlx5_query_cq_mbox_out { | |
695 | struct mlx5_outbox_hdr hdr; | |
696 | u8 rsvd0[8]; | |
697 | struct mlx5_cq_context ctx; | |
698 | u8 rsvd6[16]; | |
699 | __be64 pas[0]; | |
700 | }; | |
701 | ||
3bdb31f6 EC |
702 | struct mlx5_modify_cq_mbox_in { |
703 | struct mlx5_inbox_hdr hdr; | |
704 | __be32 cqn; | |
705 | __be32 field_select; | |
706 | struct mlx5_cq_context ctx; | |
707 | u8 rsvd[192]; | |
708 | __be64 pas[0]; | |
709 | }; | |
710 | ||
711 | struct mlx5_modify_cq_mbox_out { | |
712 | struct mlx5_outbox_hdr hdr; | |
713 | }; | |
714 | ||
cd23b14b EC |
715 | struct mlx5_enable_hca_mbox_in { |
716 | struct mlx5_inbox_hdr hdr; | |
717 | u8 rsvd[8]; | |
718 | }; | |
719 | ||
720 | struct mlx5_enable_hca_mbox_out { | |
721 | struct mlx5_outbox_hdr hdr; | |
722 | u8 rsvd[8]; | |
723 | }; | |
724 | ||
725 | struct mlx5_disable_hca_mbox_in { | |
726 | struct mlx5_inbox_hdr hdr; | |
727 | u8 rsvd[8]; | |
728 | }; | |
729 | ||
730 | struct mlx5_disable_hca_mbox_out { | |
731 | struct mlx5_outbox_hdr hdr; | |
732 | u8 rsvd[8]; | |
733 | }; | |
734 | ||
e126ba97 EC |
735 | struct mlx5_eq_context { |
736 | u8 status; | |
737 | u8 ec_oi; | |
738 | u8 st; | |
739 | u8 rsvd2[7]; | |
740 | __be16 page_pffset; | |
741 | __be32 log_sz_usr_page; | |
742 | u8 rsvd3[7]; | |
743 | u8 intr; | |
744 | u8 log_page_size; | |
745 | u8 rsvd4[15]; | |
746 | __be32 consumer_counter; | |
747 | __be32 produser_counter; | |
748 | u8 rsvd5[16]; | |
749 | }; | |
750 | ||
751 | struct mlx5_create_eq_mbox_in { | |
752 | struct mlx5_inbox_hdr hdr; | |
753 | u8 rsvd0[3]; | |
754 | u8 input_eqn; | |
755 | u8 rsvd1[4]; | |
756 | struct mlx5_eq_context ctx; | |
757 | u8 rsvd2[8]; | |
758 | __be64 events_mask; | |
759 | u8 rsvd3[176]; | |
760 | __be64 pas[0]; | |
761 | }; | |
762 | ||
763 | struct mlx5_create_eq_mbox_out { | |
764 | struct mlx5_outbox_hdr hdr; | |
765 | u8 rsvd0[3]; | |
766 | u8 eq_number; | |
767 | u8 rsvd1[4]; | |
768 | }; | |
769 | ||
770 | struct mlx5_destroy_eq_mbox_in { | |
771 | struct mlx5_inbox_hdr hdr; | |
772 | u8 rsvd0[3]; | |
773 | u8 eqn; | |
774 | u8 rsvd1[4]; | |
775 | }; | |
776 | ||
777 | struct mlx5_destroy_eq_mbox_out { | |
778 | struct mlx5_outbox_hdr hdr; | |
779 | u8 rsvd[8]; | |
780 | }; | |
781 | ||
782 | struct mlx5_map_eq_mbox_in { | |
783 | struct mlx5_inbox_hdr hdr; | |
784 | __be64 mask; | |
785 | u8 mu; | |
786 | u8 rsvd0[2]; | |
787 | u8 eqn; | |
788 | u8 rsvd1[24]; | |
789 | }; | |
790 | ||
791 | struct mlx5_map_eq_mbox_out { | |
792 | struct mlx5_outbox_hdr hdr; | |
793 | u8 rsvd[8]; | |
794 | }; | |
795 | ||
796 | struct mlx5_query_eq_mbox_in { | |
797 | struct mlx5_inbox_hdr hdr; | |
798 | u8 rsvd0[3]; | |
799 | u8 eqn; | |
800 | u8 rsvd1[4]; | |
801 | }; | |
802 | ||
803 | struct mlx5_query_eq_mbox_out { | |
804 | struct mlx5_outbox_hdr hdr; | |
805 | u8 rsvd[8]; | |
806 | struct mlx5_eq_context ctx; | |
807 | }; | |
808 | ||
809 | struct mlx5_mkey_seg { | |
810 | /* This is a two bit field occupying bits 31-30. | |
811 | * bit 31 is always 0, | |
812 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation | |
813 | */ | |
814 | u8 status; | |
815 | u8 pcie_control; | |
816 | u8 flags; | |
817 | u8 version; | |
818 | __be32 qpn_mkey7_0; | |
819 | u8 rsvd1[4]; | |
820 | __be32 flags_pd; | |
821 | __be64 start_addr; | |
822 | __be64 len; | |
823 | __be32 bsfs_octo_size; | |
824 | u8 rsvd2[16]; | |
825 | __be32 xlt_oct_size; | |
826 | u8 rsvd3[3]; | |
827 | u8 log2_page_size; | |
828 | u8 rsvd4[4]; | |
829 | }; | |
830 | ||
831 | struct mlx5_query_special_ctxs_mbox_in { | |
832 | struct mlx5_inbox_hdr hdr; | |
833 | u8 rsvd[8]; | |
834 | }; | |
835 | ||
836 | struct mlx5_query_special_ctxs_mbox_out { | |
837 | struct mlx5_outbox_hdr hdr; | |
838 | __be32 dump_fill_mkey; | |
839 | __be32 reserved_lkey; | |
840 | }; | |
841 | ||
842 | struct mlx5_create_mkey_mbox_in { | |
843 | struct mlx5_inbox_hdr hdr; | |
844 | __be32 input_mkey_index; | |
845 | u8 rsvd0[4]; | |
846 | struct mlx5_mkey_seg seg; | |
847 | u8 rsvd1[16]; | |
848 | __be32 xlat_oct_act_size; | |
849 | __be32 bsf_coto_act_size; | |
850 | u8 rsvd2[168]; | |
851 | __be64 pas[0]; | |
852 | }; | |
853 | ||
854 | struct mlx5_create_mkey_mbox_out { | |
855 | struct mlx5_outbox_hdr hdr; | |
856 | __be32 mkey; | |
857 | u8 rsvd[4]; | |
858 | }; | |
859 | ||
860 | struct mlx5_destroy_mkey_mbox_in { | |
861 | struct mlx5_inbox_hdr hdr; | |
862 | __be32 mkey; | |
863 | u8 rsvd[4]; | |
864 | }; | |
865 | ||
866 | struct mlx5_destroy_mkey_mbox_out { | |
867 | struct mlx5_outbox_hdr hdr; | |
868 | u8 rsvd[8]; | |
869 | }; | |
870 | ||
871 | struct mlx5_query_mkey_mbox_in { | |
872 | struct mlx5_inbox_hdr hdr; | |
873 | __be32 mkey; | |
874 | }; | |
875 | ||
876 | struct mlx5_query_mkey_mbox_out { | |
877 | struct mlx5_outbox_hdr hdr; | |
878 | __be64 pas[0]; | |
879 | }; | |
880 | ||
881 | struct mlx5_modify_mkey_mbox_in { | |
882 | struct mlx5_inbox_hdr hdr; | |
883 | __be32 mkey; | |
884 | __be64 pas[0]; | |
885 | }; | |
886 | ||
887 | struct mlx5_modify_mkey_mbox_out { | |
888 | struct mlx5_outbox_hdr hdr; | |
3bdb31f6 | 889 | u8 rsvd[8]; |
e126ba97 EC |
890 | }; |
891 | ||
892 | struct mlx5_dump_mkey_mbox_in { | |
893 | struct mlx5_inbox_hdr hdr; | |
894 | }; | |
895 | ||
896 | struct mlx5_dump_mkey_mbox_out { | |
897 | struct mlx5_outbox_hdr hdr; | |
898 | __be32 mkey; | |
899 | }; | |
900 | ||
901 | struct mlx5_mad_ifc_mbox_in { | |
902 | struct mlx5_inbox_hdr hdr; | |
903 | __be16 remote_lid; | |
904 | u8 rsvd0; | |
905 | u8 port; | |
906 | u8 rsvd1[4]; | |
907 | u8 data[256]; | |
908 | }; | |
909 | ||
910 | struct mlx5_mad_ifc_mbox_out { | |
911 | struct mlx5_outbox_hdr hdr; | |
912 | u8 rsvd[8]; | |
913 | u8 data[256]; | |
914 | }; | |
915 | ||
916 | struct mlx5_access_reg_mbox_in { | |
917 | struct mlx5_inbox_hdr hdr; | |
918 | u8 rsvd0[2]; | |
919 | __be16 register_id; | |
920 | __be32 arg; | |
921 | __be32 data[0]; | |
922 | }; | |
923 | ||
924 | struct mlx5_access_reg_mbox_out { | |
925 | struct mlx5_outbox_hdr hdr; | |
926 | u8 rsvd[8]; | |
927 | __be32 data[0]; | |
928 | }; | |
929 | ||
930 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) | |
931 | ||
932 | enum { | |
933 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
934 | }; | |
935 | ||
936 | #endif /* MLX5_DEVICE_H */ |